JP4775239B2 - A / D conversion circuit - Google Patents

Description

  The present invention relates to a comparator for converting an analog input signal into a digital signal, a D / A converter for converting the output of the comparator back into an analog signal, and subtracting the output of the D / A converter from the analog input signal. Regarding an A / D conversion circuit (hereinafter simply referred to as a cascade A / D conversion circuit) configured by cascade-connecting a subtractor with a plurality of stages, in particular, generation of an offset voltage due to a change speed of an input signal of a comparator. The present invention relates to an A / D conversion circuit that can prevent the above-described problem.

  Prior art documents related to a conventional cascade A / D conversion circuit or a comparator include the following.

Japanese Patent Laid-Open No. 06-013854 JP 09-238077 A Japanese Patent Laid-Open No. 10-0779651 JP-A-11-261419 JP 2000-236238 A

  FIG. 6 is a circuit diagram showing an example of a conventional cascade A / D conversion circuit. In FIG. 6, 1, 4 and 7 are comparators functioning as 1-bit A / D converters for converting analog input signals into digital signals, 2, 5 and 8 are subtractors for subtracting analog signals, and 3, 6 And 9 are 1-bit D / A converters for converting a digital signal into an analog signal, 100 is an analog input signal, and 101, 102 and 103 are digital output signals.

  The subtracter 1, the subtracter 2, and the D / A converter 3 are a first stage that performs A / D conversion of 1 bit (most significant bit), a subtracter 4, a subtractor 5, and a D / A converter. Reference numeral 6 denotes a second stage that performs 1-bit A / D conversion, and subtracter 7, subtractor 8, and D / A converter 9 constitute a third stage that performs 1-bit A / D conversion.

  The analog input signal 100 is applied to the input terminal of the comparator 1 and the addition input terminal of the subtractor 2, and the output terminal of the comparator 1 outputs the digital output signal 101 and is connected to the input terminal of the D / A converter 3. Is done. The output terminal of the D / A converter 3 is connected to the subtraction input terminal of the subtractor 2.

  The output terminal of the subtractor 2 is connected to the input terminal of the comparator 4 and the addition input terminal of the subtractor 5, and the output terminal of the comparator 4 outputs the digital output signal 102 and the D / A converter 6. Connected to input terminal. The output terminal of the D / A converter 6 is connected to the subtraction input terminal of the subtracter 5.

  Similarly, the output terminal of the subtractor 5 is connected to the input terminal of the comparator 7 and the addition input terminal of the subtractor 8, respectively. The output terminal of the comparator 7 outputs the digital output signal 103 and the D / A converter 9 Connected to the input terminal. The output terminal of the D / A converter 9 is connected to the subtraction input terminal of the subtracter 8.

  Here, the operation of the conventional example shown in FIG. 6 will be described. The comparator 1 operates as a 1-bit A / D converter that converts an analog input signal into a 1-bit digital signal depending on whether the analog input signal is positive or negative, and outputs the conversion result as the most significant bit digital output signal 101.

  The digital output signal 101 thus converted in the comparator 1 is converted again into an analog signal by the D / A converter 3 and subtracted from the analog input signal 100 in the subtractor 2 to become a first residual signal. The signal is supplied to a circuit (specifically, the comparator 4 and the subtractor 5) constituting the second stage.

  Similarly, the comparator 4 operates as a 1-bit A / D converter that converts the first residual signal supplied from the previous stage into a 1-bit digital signal according to the sign of the first residual signal. Output as.

  The digital output signal 102 thus converted by the comparator 4 is converted again to an analog signal by the D / A converter 6 and subtracted from the first residual signal by the subtractor 5 to become a second residual signal. This is supplied to a circuit (specifically, the comparator 7 and the subtractor 8) constituting the third stage of the subsequent stage.

  Similarly, the comparator 7 operates as a 1-bit A / D converter that converts it into a 1-bit digital signal based on the sign of the second residual signal supplied from the previous stage, and outputs the conversion result as a digital output. Output as signal 103.

  The digital output signal 103 thus converted by the comparator 7 is converted again to an analog signal by the D / A converter 9 and subtracted from the second residual signal by the subtractor 8 to become a third residual signal. It is supplied to a circuit (not shown) constituting the fourth stage of the subsequent stage.

  As a result, an A / D conversion circuit (cascade A / D conversion circuit) that performs multi-bit A / D conversion can be realized by cascading a plurality of stages that perform 1-bit A / D conversion. .

  FIG. 7 is a circuit diagram showing a specific example of the comparators 1, 4 and 7 in FIG. 6, and illustrates a differential input / output comparator.

  In FIG. 7, 10, 11, 15, 18 and 21 are resistors, 12, 13, 14, 16, 17, 19 and 20 are transistors, 104 and 105 are differential input signals, 106 is a bias voltage signal, 107 and Reference numeral 108 denotes a differential output signal.

  10, 11, 12, 13, 14, and 15 constitute a differential circuit, and 16, 17, 18, 19, 20, and 21 constitute an output stage circuit composed of two emitter follower circuits, respectively.

  Further, the input signal 105 is an inverted signal of the input signal 104, and the output signal 108 is an inverted signal of the output signal 107.

  Input signal 104 and input signal 105 are applied to the bases of transistor 12 and transistor 13, respectively. The collector of the transistor 12 is connected to one end of the resistor 10 and the base of the transistor 19, and the collector of the transistor 13 is connected to one end of the resistor 11 and the base of the transistor 16, respectively.

  The emitter of the transistor 12 is connected to the emitter of the transistor 13 and the collector of the transistor 14, and the emitter of the transistor 14 is connected to one end of the resistor 15.

  An output signal 107 is output from the emitter of the transistor 16, the emitter of the transistor 16 is connected to the collector of the transistor 17, and the emitter of the transistor 17 is connected to one end of the resistor 18.

  An output signal 108 is output from the emitter of the transistor 19, the emitter of the transistor 19 is connected to the collector of the transistor 20, and the emitter of the transistor 20 is connected to one end of the resistor 21.

  Finally, the bias voltage signal 106 is applied to the bases of the transistors 14, 17 and 20, respectively, and the positive voltage source “VCC” is applied to the other ends of the resistors 10 and 11 and the collectors of the transistors 16 and 19, respectively. “VEE” is applied to the other ends of the resistors 15, 18 and 21, respectively.

  Here, the operation of the comparator shown in FIG. 7 will be described. The transistor 14 and the resistor 15 operate as a constant current source that outputs a current uniquely determined by the bias voltage applied to the base of the transistor 14 and the resistance value of the resistor 15.

That is, when the bias voltage is “Vbias”, the base-emitter voltage of the transistor 14 is “Vbe14”, and the resistance value of the resistor 15 is “R15”, the constant current “I1” is
I1 = (Vbias−Vbe14−VEE) / R15 (1)
It becomes.

  Since the transistors 12 and 13 constitute a differential circuit, the transistors 12 and 13 operate so as to switch the constant current “I1” according to the signal levels of the differential input signals 104 and 105 inputted.

  If the input signal 104 is high level (the input signal 105 which is an inverted signal is low level), the transistor 12 is “ON” and the transistor 13 is “OFF”.

  Therefore, if the resistance value of the resistor 10 is “R10”, the collector voltage of the transistor 12 becomes “VCC−R10 · I1” due to the current “I1” flowing through the resistor 10.

Since this voltage is output as an output signal 108 (inverted signal) through an emitter follower circuit composed of transistors 19 and 20 and a resistor 21, the voltage value is "V108" and the base-emitter voltage of the transistor 19 is If it is “Vbe19”,
V108 = VCC-R10 · I1-Vbe19 (2)
It becomes. Further, the voltage value of the expression (2) is at a low level.

  On the other hand, the collector voltage of the transistor 13 remains “VCC” because no current flows through the resistor 11.

Since this voltage is output as an output signal 107 (non-inverted signal) through an emitter follower circuit composed of transistors 16 and 17 and a resistor 18, the voltage value is “V107”, and the base-emitter voltage of the transistor 7. Is "Vbe16",
V107 = VCC-Vbe16 (3)
It becomes. Further, the voltage value of the expression (3) becomes a high level.

  Similarly, if the input signal 104 is low level (the input signal 105 which is an inverted signal is high level), the transistor 12 is turned “OFF”, the transistor 13 is turned “ON”, and the output signal 107 (non-inverted). Signal) and output signal 108 (inverted signal) have a low level voltage value and a high level voltage value, respectively.

  As a result, a differential input / output comparator can be realized by outputting the differential output of the differential circuit to which the differential input signal is applied via the output stage circuit.

  That is, one of the differential input signals of such a comparator is set as a reference voltage (for example, “0V”), the analog input signal 100 is applied as the other input signal, and the non-inverted signal is set as a digital signal. By outputting, it can be operated as a 1-bit A / D converter that converts the analog input signal into a 1-bit digital signal depending on whether the analog input signal is positive or negative.

  However, the comparator as shown in FIG. 7 has a problem that an offset voltage is generated due to the change speed of the input signal. FIG. 8 is an explanatory diagram for explaining the operation of the transistors in the input section of the comparator.

  When the voltage value of the input signal 104 is sufficiently smaller than the voltage value of the input signal 105, the transistor 12 is “OFF”, the transistor 13 is “ON”, and the constant current “I1” flows through the transistor 13.

Here, when the power consumption of the transistors 12 and 13 is “Pw12” and “Pw13”, the thermal resistance of the transistors 12 and 13 is “θ”, and the temperature rise due to the power consumption in the transistor 13 is “ΔT13”,
ΔT13 = Pw13 · θ [° C] (4)
It becomes.

On the other hand, since no current flows through the transistor 12 and there is no power consumption (Pw12 = 0), when the temperature rise due to power consumption in the transistor 12 is “ΔT12”,
ΔT12 = Pw12 · θ = 0 [° C] (5)
It becomes.

  In this state, as shown in FIG. 8, the voltages of the input signals 104 and 105 are set so that the currents flowing in the transistors 12 and 13 become equal in a time sufficiently shorter than the thermal time constant “τ” of the transistors 12 and 13. Assume that the value has changed.

  In this case, as shown in FIG. 8, since the current “I1 / 2” flows through the transistors 12 and 13 equally, the power consumption of both is almost the same (Pw12≈Pw13). However, since the change in the voltage value of the input signals 104 and 105 changes in a time shorter than the thermal time constant “τ”, no change in temperature occurs in the transistors 12 and 13.

  Therefore, when the temperature coefficient of the base-emitter voltage “Vbe” of the transistors 12 and 13 is “−2 mV / ° C.”, even if the current “I1 / 2” flows through the transistors 12 and 13 evenly. Thus, a voltage difference of “−2 · Pw13 · θ [mV]” is generated between the base-emitter voltages of the transistors 12 and 13.

  Further, when the current “I1 / 2” flows through the transistors 12 and 13 equally, the voltage values of the output voltages 107 and 108 are equal, so that the voltage difference “−2 · Pw13 · θ [mV]” is It will occur as an offset voltage.

  In contrast, as shown in FIG. 8, the transistors 12 and 13 are satisfied in a time sufficiently longer than the thermal time constant “τ” of the transistors 12 and 13 while satisfying the equations (4) and (5). Assume that the voltage values of the input signals 104 and 105 are changed so that the currents flowing in are equal.

  In this case, since the change in the voltage value of the input signals 104 and 105 changes in a time sufficiently longer than the thermal time constant “τ” of the transistors 12 and 13, the current “evenly” is supplied to the transistors 12 and 13 as shown in FIG. At the time when I1 / 2 "flows and the power consumption of both is almost the same (Pw12≈Pw13), the temperature changes occur in the transistors 12 and 13, and the temperature changes of both are substantially equal (ΔT12≈ΔT13).

  Therefore, the above-described voltage difference does not occur between the base-emitter voltages of the transistors 12 and 13, and no offset voltage is generated. In other words, an offset voltage is generated due to the change speed of the input signal.

That is, the occurrence of the offset voltage due to the change speed of the input signal of the comparator has a problem that the linearity of the conversion result of the A / D conversion circuit is affected.
Therefore, the problem to be solved by the present invention is to realize an A / D conversion circuit capable of preventing the generation of an offset voltage due to the change speed of the input signal of the comparator.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In an A / D conversion circuit configured by cascading multiple stages,
Analog signal polarity inverting means for inverting the polarity of the analog input signal based on the control signal; Digital signal polarity inverting means for inverting the polarity of the digital output signal that is the output of each comparator based on the control signal; Arithmetic control for supplying the control signal for reversing the polarity at random with a cycle shorter than the thermal time constant of the transistor constituting the input part of the comparator to the polarity inverting means for the analog signal and the polarity inverting means for the digital signal The offset voltage due to the change speed of the input signal of the comparator can be prevented.

The invention according to claim 2
A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In an A / D conversion circuit configured by cascading multiple stages,
Analog signal polarity inverting means for inverting the polarity of the analog input signal based on the control signal; Digital signal polarity inverting means for inverting the polarity of the digital output signal that is the output of each comparator based on the control signal; Generating the control signal for randomly inverting the polarity at a cycle shorter than the thermal time constant of the transistor constituting the input of the comparator to the polarity inverting means for the analog signal and the polarity inverting means for the digital signal The offset voltage due to the change speed of the input signal of the comparator can be prevented.

The invention described in claim 3
A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In the A / D conversion circuit of gray code output configured by cascade connection in multiple stages,
Analog signal polarity inversion means for inverting the polarity of the analog input signal based on the control signal, digital signal polarity inversion means for inverting the polarity of the most significant bit of the Gray code output based on the control signal, and the analog signal And an arithmetic control means for supplying the control signal for randomly inverting the polarity at a cycle shorter than a thermal time constant of a transistor constituting the input section of the comparator. As a result, it is possible to prevent the generation of the offset voltage due to the change speed of the input signal of the comparator.

The invention according to claim 4
A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In the A / D conversion circuit of gray code output configured by cascade connection in multiple stages,
Analog signal polarity inversion means for inverting the polarity of the analog input signal based on the control signal, digital signal polarity inversion means for inverting the polarity of the most significant bit of the Gray code output based on the control signal, and the analog signal And a signal generating means for supplying the control signal for randomly inverting the polarity at a cycle shorter than a thermal time constant of a transistor constituting the input section of the comparator. As a result, it is possible to prevent the generation of the offset voltage due to the change speed of the input signal of the comparator.

The invention according to claim 5
In the A / D conversion circuit according to any one of claims 1 to 4,
The arithmetic control means or the signal generating means is
The control signal causes the analog signal polarity inversion means and the digital signal polarity inversion means to operate in the same polarity inversion state, thereby preventing the occurrence of an offset voltage due to the change rate of the input signal of the comparator. It becomes possible to do.

The present invention has the following effects.
According to the inventions of claims 1, 2, 3, 4 and 5, the polarity inversion means of the analog signal is provided in the preceding stage of the cascade A / D conversion circuit, and the polarity of the digital output signal which is the output of each comparator, Alternatively, a digital signal polarity inversion means for inverting the polarity of the most significant bit of the Gray code is provided, and the polarity inversion states of the analog signal and the digital signal polarity inversion means are made the same to constitute the input section of each comparator. By reversing the polarity at random with a cycle shorter than the thermal time constant “τ” of the transistor, it is possible to prevent the occurrence of an offset voltage due to the change speed of the input signal of the comparator.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a cascade A / D conversion circuit according to the present invention.

  In FIG. 1, 1, 2, 3, 4, 5, 6, 7, 8 and 9 are given the same reference numerals as in FIG. 6, 22 is an analog signal polarity inversion means, and 23, 24 and 25 are exclusive. Digital signal polarity inversion means comprising an OR circuit, 26 is an analog signal polarity inversion means 22, arithmetic control means for controlling the digital signal polarity inversion means 23, 24 and 25, 100a is an analog input signal, 109, 110 and 111 are digital output signals, and 112 is a control signal.

  The analog input signal 100a is applied to the input terminal of the comparator 1 and the addition input terminal of the subtractor 2 via the polarity inversion means 22 of the analog signal, and the output terminal of the comparator 1 is the input terminal of the D / A converter 3. And one input terminal of the polarity inversion means 23 for the digital signal. The output terminal of the D / A converter 3 is connected to the subtraction input terminal of the subtractor 2.

  The output terminal of the subtracter 2 is connected to the input terminal of the comparator 4 and the addition input terminal of the subtractor 5, respectively. The output terminal of the comparator 4 is the input terminal of the D / A converter 6 and the polarity inversion of the digital signal. Each of the means 24 is connected to one input terminal. The output terminal of the D / A converter 6 is connected to the subtraction input terminal of the subtracter 5.

  Similarly, the output terminal of the subtractor 5 is connected to the input terminal of the comparator 7 and the addition input terminal of the subtractor 8, respectively. The output terminal of the comparator 7 is the input terminal of the D / A converter 9 and the polarity of the digital signal. Each is connected to one input terminal of the inverting means 25. The output terminal of the D / A converter 9 is connected to the subtraction input terminal of the subtracter 8.

  Finally, the control signal 112, which is the output of the arithmetic control means 26, is applied to the control input terminal of the polarity inversion means 22 for analog signals and to the other input terminals of the polarity inversion means 23, 24 and 25 for digital signals. Then, digital output signals 109, 110 and 111 are output from the output terminals of the polarity inversion means 23, 24 and 25 of the digital signal, respectively.

  The operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is an explanatory diagram showing an example of the control signal 112, and FIG. 3 is an explanatory diagram for explaining the operation of the polarity inversion means 23, 24 and the polarity inversion means 25 for digital signals composed of exclusive OR circuits.

  The control signal 112 is a random signal as indicated by “CS01” in FIG. 2, and all the periods indicated by “T1”, “T2”, “T3” and “T4” in FIG. And 7 are switched at a cycle shorter than the thermal time constant “τ” of the transistors 12 and 13 constituting the input section.

  Based on such a control signal 112, the analog signal polarity inverting means 22 outputs the input analog input signal 100a with non-inverted polarity or with the polarity inverted.

  For example, the polarity inversion means 22 of the analog signal outputs the non-inverted polarity when the control signal 112 is “low level”, and outputs the inverted polarity when the control signal 112 is “high level”. .

  On the other hand, since the control signal 112 is applied to the other input terminal of the digital signal polarity inversion means 23, 24, and 25 constituted by the exclusive OR circuit, the one input terminal according to the table shown in FIG. The digital output signals of the comparators 1, 4 and 7 applied to are output as non-inverted polarities or inverted as polarities and output as digital output signals 109, 110 and 111.

  For example, as shown in FIG. 3, when the control signal 112 is "low level", the polarity inversion means 23, 24 and 25 output the polarity of the digital output signals of the comparators 1, 4 and 7 in a non-inverted manner. When the control signal 112 is “high level”, the polarities of the digital output signals of the comparators 1, 4 and 7 are inverted and output as digital output signals 109, 110 and 111.

  That is, in the embodiment shown in FIG. 1, since the polarity of the digital input signals of the comparators 1, 4 and 7 which are digital signals is also reversed at the same time as the polarity of the analog input signal 100a is reversed, the polarity of each signal is not reversed. Or, the digital output signals 109, 110, and 111 have the same result regardless of inversion.

  In such a state, the polarity of the analog input signal 100a is randomly inverted. In other words, the input polarity of the comparators 1, 4 and 7 is randomly inverted. The time average of the voltage of the dynamic input signal is “0”. For this reason, the average power consumption of the transistors 12 and 13 constituting the inputs of the comparators 1, 4 and 7 is equal.

  On the other hand, the polarity inversion is performed in a cycle shorter than the thermal time constant “τ” of the transistors 12 and 13 constituting the input parts of the comparators 1, 4 and 7. Does not change (temperature change cannot follow), and the temperature rise is determined by the average power consumption of the transistors 12 and 13 constituting the input parts of the comparators 1, 4 and 7.

  Here, since the average power consumption of the transistors 12 and 13 constituting the input portions of the comparators 1, 4 and 7 is equal as described above, the transistors 12 and 13 constituting the input portions of the comparators 1, 4 and 7 have the same average power consumption. The temperature rise is also equal, and no offset voltage is generated due to the change rate of the input signal.

  As a result, analog signal polarity inversion means is provided in the previous stage of the cascade A / D conversion circuit, and digital signal polarity inversion means for inverting the polarity of the digital output signal that is the output of each comparator is provided. The polarity inversion state of the polarity inversion means is the same, and the polarity of the input signal of the comparator is reversed at random with a cycle shorter than the thermal time constant “τ” of the transistors constituting the input section of each comparator. It is possible to prevent the occurrence of the offset voltage due to the change speed of the.

  In the description of the embodiment shown in FIG. 1, the arithmetic control means 26 such as a CPU is exemplified as the control means for the polarity inversion means 22, 23, 24 and 25. Of course, the comparators 1, 4 and 7 are used. It may be a signal generating means capable of generating a random signal that switches at a cycle shorter than the thermal time constant “τ” of the transistors 12 and 13 constituting the input section.

  In the description of the embodiment shown in FIG. 1, a cascade A / D conversion circuit that is a binary code output is exemplified as a digital output signal, but a gray code output is used as a digital output signal of the cascade A / D conversion circuit. It doesn't matter. FIG. 4 is a circuit diagram showing an example of a conventional gray code output cascade A / D conversion circuit.

  4, 1, 2, 3, 4, 5, 6, 7, 8, and 9 are given the same reference numerals as in FIG. 6, 27 and 28 are exclusive OR circuits, 100b is an analog input signal, 113 , 114 and 115 are digital output signals.

  The analog input signal 100b is applied to the input terminal of the comparator 1 and the addition input terminal of the subtractor 2, and the output terminal of the comparator 1 outputs the digital output signal 113 and the exclusive input terminal of the D / A converter 3. Is connected to one input terminal of the logical OR circuit 27. The output terminal of the D / A converter 3 is connected to the subtraction input terminal of the subtractor 2.

  The output terminal of the subtractor 2 is connected to the input terminal of the comparator 4 and the addition input terminal of the subtractor 5, respectively. The output terminal of the comparator 4 is the input terminal of the D / A converter 6 and an exclusive OR circuit. 27 and the other input terminal of the exclusive OR circuit 28, respectively. The output terminal of the D / A converter 6 is connected to the subtraction input terminal of the subtracter 5.

  Similarly, the output terminal of the subtractor 5 is connected to the input terminal of the comparator 7 and the addition input terminal of the subtractor 8, respectively. The output terminal of the comparator 7 is connected to the input terminal of the D / A converter 9 and the exclusive OR. The other input terminals of the circuit 28 are respectively connected. The output terminal of the D / A converter 9 is connected to the subtraction input terminal of the subtracter 8.

  Finally, the exclusive OR circuit 27 outputs a digital output signal 114, and the exclusive OR circuit 28 outputs a digital output signal 115.

  Here, the basic operation of the conventional example shown in FIG. 4 is the same as that of the conventional example shown in FIG. 6, and the difference is that the digital output signals 113, 114, and 115 become gray code outputs.

  FIG. 5 is a circuit diagram showing another embodiment of the cascade A / D conversion circuit according to the present invention. In FIG. 5, 1, 2, 3, 4, 5, 6, 7, 8, 9, 27 and 28 are assigned the same reference numerals as in FIG. 4, 29 is an analog signal polarity inversion means, and 30 is exclusive. Digital signal polarity inversion means comprising an OR circuit, 31 an analog signal polarity inversion means 29, arithmetic control means for controlling the digital signal polarity inversion means 30, 100c an analog input signal, 116, 117 and 118 A digital output signal 119 is a control signal.

  The analog input signal 100c is applied to the input terminal of the comparator 1 and the addition input terminal of the subtractor 2 via the polarity inversion means 29 of the analog signal, and the output terminal of the comparator 1 is the input terminal of the D / A converter 3. Are connected to one input terminal of the polarity inversion means 30 of the digital output signal and one input terminal of the exclusive OR circuit 24, respectively. The output terminal of the D / A converter 3 is connected to the subtraction input terminal of the subtractor 2.

  The output terminal of the subtractor 2 is connected to the input terminal of the comparator 4 and the addition input terminal of the subtractor 5, respectively. The output terminal of the comparator 4 is the input terminal of the D / A converter 6 and an exclusive OR circuit. 27 and the other input terminal of the exclusive OR circuit 28, respectively. The output terminal of the D / A converter 6 is connected to the subtraction input terminal of the subtracter 5.

  Similarly, the output terminal of the subtractor 5 is connected to the input terminal of the comparator 7 and the addition input terminal of the subtractor 8, respectively. The output terminal of the comparator 7 is connected to the input terminal of the D / A converter 9 and the exclusive OR. The other input terminals of the circuit 28 are respectively connected. The output terminal of the D / A converter 9 is connected to the subtraction input terminal of the subtracter 8.

  Finally, the control signal 119, which is the output of the arithmetic control means 33, is applied to the control input terminal of the polarity inverting means 29 for the analog signal and to the other input terminal of the polarity inverting means 30 for the digital signal. Digital output signals 116, 117, and 118 are output from the output terminal of the polarity inversion means 30 of the digital signal and the output terminals of the exclusive OR circuit 27 and the exclusive OR circuit 28, respectively.

  Here, the operation of the embodiment shown in FIG. 5 will be described. However, the basic operation is the same as that of the embodiment shown in FIG.

  When the digital output signal is a clay code output, even if the polarity of the analog input signal 100c is inverted, only the most significant bit of the Gray code is inverted and the other bits are not affected. For this reason, the polarity inversion state of the polarity inversion means of the analog signal and the digital signal is substantially made the same by inverting the most significant bit of the Gray code in synchronization with the inversion of the polarity of the analog input signal 100c. Can do.

  In other words, the polarity inversion means 30 inverts the most significant bit of the Gray code based on the control signal 119 to invert the polarities of the digital output signals 116 and 117 and the digital output signal 118.

  As a result, the polarity inversion means for the analog signal is provided in the previous stage of the cascade A / D conversion circuit, and the polarity inversion means for the digital signal for inverting the polarity of the most significant bit of the digital output signal (Gray code) that is the output of each comparator. The polarity inversion state of the polarity inversion means for the analog signal and the digital signal is made the same, and the polarity is randomly inverted at a cycle shorter than the thermal time constant “τ” of the transistor constituting the input part of each comparator As a result, it is possible to prevent the occurrence of the offset voltage due to the change speed of the input signal of the comparator.

1 is a circuit diagram showing an embodiment of a cascade A / D conversion circuit according to the present invention. FIG. It is explanatory drawing which shows an example of a control signal. It is explanatory drawing explaining operation | movement of the polarity inversion means of the digital signal comprised by an exclusive OR circuit. It is a circuit diagram showing an example of a conventional cascade A / D conversion circuit of gray code output. It is a circuit diagram which shows the other Example of the cascade A / D conversion circuit based on this invention. It is a circuit diagram which shows an example of the conventional cascade A / D conversion circuit. It is a circuit diagram which shows the specific example of a comparator. It is explanatory drawing explaining operation | movement of the transistor of the input part of a comparator.

Explanation of symbols

1, 4, 7 Comparator 2, 5, 8 Subtractor 3, 6, 9 D / A converter 10, 11, 15, 18, 21 Resistor 12, 13, 14, 16, 17, 19, 20 Transistor 22, 23, 24, 25, 29, 30 Polarity inversion means 26, 31 Operation control means 27, 28 Exclusive OR circuit 100, 100a, 100b, 100c Analog input signals 101, 102, 103, 109, 110, 111, 113, 114, 115, 116, 117, 118 Digital output signal 104, 105 Input signal 106 Bias voltage signal 107, 108 Output signal 112, 119 Control signal

Claims (5)

A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In an A / D conversion circuit configured by cascading multiple stages,
Analog signal polarity inverting means for inverting the polarity of the analog input signal based on a control signal;
Digital signal polarity inverting means for inverting the polarity of the digital output signal that is the output of each comparator based on the control signal;
Arithmetic control means for supplying the control signal for randomly inverting the polarity at a cycle shorter than the thermal time constant of the transistor constituting the input part of the comparator to the polarity inverting means for the analog signal and the polarity inverting means for the digital signal An A / D conversion circuit comprising: A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In an A / D conversion circuit configured by cascading multiple stages,
Analog signal polarity inverting means for inverting the polarity of the analog input signal based on a control signal;
Digital signal polarity inverting means for inverting the polarity of the digital output signal that is the output of each comparator based on the control signal;
Signal generating means for supplying the control signal for inverting the polarity at random in a cycle shorter than the thermal time constant of the transistor constituting the input part of the comparator to the polarity inverting means for the analog signal and the polarity inverting means for the digital signal An A / D conversion circuit comprising: A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In the A / D conversion circuit of gray code output configured by cascade connection in multiple stages,
Analog signal polarity inverting means for inverting the polarity of the analog input signal based on a control signal;
A digital signal polarity inversion means for inverting the polarity of the most significant bit of the Gray code output based on the control signal;
Arithmetic control means for supplying the control signal for randomly inverting the polarity at a cycle shorter than the thermal time constant of the transistor constituting the input part of the comparator to the polarity inverting means for the analog signal and the polarity inverting means for the digital signal An A / D conversion circuit comprising: A comparator that converts an analog input signal into a digital signal, a D / A converter that converts the output of the comparator back into an analog signal, and a subtracter that subtracts the output of the D / A converter from the analog input signal In the A / D conversion circuit of gray code output configured by cascade connection in multiple stages,
Analog signal polarity inverting means for inverting the polarity of the analog input signal based on a control signal;
A digital signal polarity inversion means for inverting the polarity of the most significant bit of the Gray code output based on the control signal;
Signal generating means for supplying the control signal for inverting the polarity at random in a cycle shorter than the thermal time constant of the transistor constituting the input part of the comparator to the polarity inverting means for the analog signal and the polarity inverting means for the digital signal An A / D conversion circuit comprising: The arithmetic control means or the signal generating means is
The A / according to any one of claims 1 to 4, wherein the control signal causes the analog signal polarity inversion means and the digital signal polarity inversion means to operate in the same polarity inversion state. D conversion circuit.

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