JP4776396B2 - Adiabatic charging memory circuit and data writing method - Google Patents

Description

  The present invention relates to a technique for preventing an increase in current density generated when miniaturization of an element is advanced and disconnection of wiring due to electromigration in a memory circuit.

Conventionally, the SRAM (Static Random Access Memory) circuit that is generally used uses two CMOS inverters composed of a pMOS transistor and an nMOS transistor as shown in FIG. A flip-flop connecting the output terminal to the other input terminal is used as a memory element. The output signal of each CMOS inverter is connected to the bit line via an nMOS transistor, and one memory cell has a total of six transistors.
International weekly journal of science nature, vol 406, 31 August 2000, p. 1023-1026

  However, in recent years, the miniaturization of memory elements has progressed, and the wiring current density has increased as the cross-sectional area of the wiring has decreased. As a result, there has been a problem that wiring disconnection due to electromigration or the like occurs (Non-Patent Document 1). reference).

  The present invention has been made in view of the above, and an object of the present invention is to prevent disconnection of wiring due to electromigration caused by miniaturization of a memory element.

The adiabatic charging memory circuit according to the first aspect of the present invention includes a flip-flop circuit in which a CMOS inverter circuit composed of a pMOS transistor and an nMOS transistor connected in series is connected in a complementary manner, First voltage input means for inputting a voltage to be changed in a time longer than the time constant of the flip-flop circuit to the source electrode of the pMOS transistor, and one input terminal of the flip-flop circuit at the time of the flip-flop circuit A second voltage input means for inputting a voltage to be changed in a time longer than a constant; a first switch element provided between a constant voltage power supply and the memory cell power supply line; and the first voltage input means. And a second switch element provided between the memory cell power supply line and the first switch element When the second switch element is on, the first voltage input means steps down the potential of the memory cell power supply line from a high voltage to a low voltage in a time longer than the time constant of the flip-flop circuit. After the potential of the memory cell power supply line becomes a low voltage, the second switch element is turned off, and the flip-flop circuit is turned off with the first switch element and the second switch element turned off. The potential of the other input terminal of the flip-flop circuit is fixed at a low voltage, and the potential of one input terminal of the flip-flop circuit is reduced from the low voltage for a time longer than the time constant of the flip-flop circuit by the second voltage input means. By boosting to a high voltage, the potential of the memory cell power line is boosted from a low voltage to a high voltage in conjunction with a boost of the potential of one input terminal of the flip-flop circuit. Characterized in that that.

In the present invention, the potential of the memory cell power line is boosted from a low voltage to a high voltage in conjunction with the boosting of the potential at one input terminal of the flip-flop circuit, so that the data flows to the memory element. Maximum current can be reduced, and disconnection of wiring due to electromigration can be prevented. Thereby, for example, it is possible to step up and down the voltage input to the flip-flop circuit over a time of about 1 ns or more. Therefore, the current value in the wiring can be set to about 1/100 to 1/1000 or less without changing the values of the power supply voltage and the threshold voltage.

The adiabatic charging memory circuit according to the second aspect of the present invention includes a flip-flop circuit in which a CMOS inverter circuit composed of a pMOS transistor and an nMOS transistor connected in series is connected in a complementary manner, First voltage input means for inputting a voltage to be changed in a time longer than the time constant of the flip-flop circuit to the source electrode of the pMOS transistor, and one input terminal of the flip-flop circuit at the time of the flip-flop circuit A second voltage input means for inputting a voltage to be changed in a time longer than a constant; a first switch element provided between a constant voltage power supply and the memory cell power supply line; and the first voltage input means. And a second switch element provided between the memory cell power supply line and the first switch element When the second switch element is on, the first voltage input means steps down the potential of the memory cell power supply line from a high voltage to a low voltage in a time longer than the time constant of the flip-flop circuit. After the potential of the memory cell power supply line becomes a low voltage, the potential of the other input terminal of the flip-flop circuit is lowered with the first switch element turned off and the second switch element turned on. The voltage of the memory cell power supply line is boosted from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit by the first voltage input means, and in accordance with the boosting, The potential of one input terminal of the flip-flop circuit is boosted from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit by the second voltage input means. Accordingly, characterized by boosting the potential of the memory cell power supply line to one of the high voltage from the interlocked so a low voltage to boost the input of the potential of the flip-flop circuit.

In the present invention, the potential of the memory cell power line is boosted from a low voltage to a high voltage in conjunction with the boosting of the potential at one input terminal of the flip-flop circuit, so that the data flows to the memory element. Maximum current can be reduced, and disconnection of wiring due to electromigration can be prevented. Thereby, for example, it is possible to step up and down the voltage input to the flip-flop circuit over a time of about 1 ns or more. Therefore, the current value in the wiring can be set to about 1/100 to 1/1000 or less without changing the values of the power supply voltage and the threshold voltage.

In adiabatic charging memory circuit of the above, the first voltage input means, wherein are respectively connected between the memory cell power supply lines and a plurality of constant-voltage power supply line, a constant voltage outputted from the respective constant voltage power supply line a plurality of switching elements for inputting before Symbol memory cell power supply line, by sequentially switching on and off of said plurality of switching elements, the potential of the memory cell power supply line at a time longer than the time constant of the flip-flop circuit And a control circuit to be changed .

  In the present invention, the constant voltage output from each constant voltage power supply line is connected between the memory cell power supply line and the plurality of constant voltage power supply lines, and is changed in a time longer than the time constant of the flip-flop circuit. Thus, by turning on / off the plurality of switch elements that are input to the memory cell power supply line, the maximum current flowing through the memory element can be reduced, and disconnection of the wiring due to electromigration can be prevented.

In the above adiabatic charging memory circuit, the second voltage input means includes a transfer transistor in which a drain electrode, a source electrode, and a gate electrode are respectively connected to one input terminal, a bit line, and a word line of the flip-flop circuit. And an adiabatic charging circuit that boosts the potential of the bit line from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit, the potential of the word line being set to a high voltage and the transfer The bit line potential is boosted by the adiabatic charging circuit after the transistor is turned on.
In the above adiabatic charging memory circuit, the second voltage input means includes a transfer transistor in which a drain electrode, a source electrode, and a gate electrode are respectively connected to one input terminal , a bit line , and a word line of the flip-flop circuit. The potential of the word line is changed from a low voltage to a high voltage so that the potential input to one input terminal of the flip-flop circuit is boosted from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit. An adiabatic charging circuit for boosting the voltage, wherein the potential of the bit line is set to a high voltage before the potential of the word line reaches the threshold voltage of the transfer transistor .

  In the present invention, the voltage input to the gate electrode of the transfer transistor is boosted from a low voltage to a high voltage so that the time input to the flip-flop circuit is longer than the time constant of the flip-flop circuit. The maximum current flowing through the memory element can be reduced, and the disconnection of the wiring due to electromigration can be prevented.

  In the above adiabatic charging memory circuit, the low voltage of the memory cell power supply line is more than GND and less than 2/3 of the high voltage.

  In the present invention, the speed at which data is written to the memory can be adjusted by setting the low voltage of the memory cell power supply line to be equal to or higher than GND and lower than 2/3 of the high voltage.

According to a third aspect of the present invention, there is provided a data writing method comprising: a flip-flop circuit in which CMOS inverter circuits each composed of a pMOS transistor and an nMOS transistor connected in series are complementarily connected; and each pMOS through a memory cell power line. First voltage input means for inputting a voltage to be changed in a time longer than the time constant of the flip-flop circuit to the source electrode of the transistor, and a time constant of the flip-flop circuit to one input terminal of the flip-flop circuit A second voltage input means for inputting a voltage to be changed in a longer time, a first switch element provided between a constant voltage power supply and the memory cell power supply line, and the first voltage input means. using adiabatic charging memory circuit having a second switch element provided between the memory cell power supply line A data writing method of performing, the first switching element is turned off, the second switch element is in the ON state, the first voltage input means and said flip-flop circuit the potential of the memory cell power supply line by A step of stepping down from a high voltage to a low voltage in a time longer than a time constant; a step of turning off the second switch element after the potential of the memory cell power supply line becomes a low voltage; While the switch element and the second switch element are in an off state, the potential of the other input terminal of the flip-flop circuit is fixed to a low voltage, and one of the flip-flop circuits is fixed by the second voltage input means. By boosting the potential of the input terminal from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit, the potential of the memory cell power supply line is increased. And having a step of boosting from one of the low voltage in conjunction with the boosting of the input terminals of the potential of the flip-flop circuit to a high voltage.

According to a fourth aspect of the present invention, there is provided a data writing method comprising: a flip-flop circuit in which CMOS inverter circuits each composed of a pMOS transistor and an nMOS transistor connected in series are complementarily connected; and each pMOS through a memory cell power line. First voltage input means for inputting a voltage to be changed in a time longer than the time constant of the flip-flop circuit to the source electrode of the transistor, and a time constant of the flip-flop circuit to one input terminal of the flip-flop circuit A second voltage input means for inputting a voltage to be changed in a longer time, a first switch element provided between a constant voltage power supply and the memory cell power supply line, and the first voltage input means. using adiabatic charging memory circuit having a second switch element provided between the memory cell power supply line A data writing method of performing, the first switching element is turned off, the second switch element is in the ON state, the first voltage input means and said flip-flop circuit the potential of the memory cell power supply line by The step of stepping down from a high voltage to a low voltage in a time longer than a time constant and after the potential of the memory cell power supply line becomes a low voltage, the first switch element is turned off and the second switch element is turned on In this state, the potential of the other input terminal of the flip-flop circuit is fixed to a low voltage, and the potential of the memory cell power supply line is set longer than the time constant of the flip-flop circuit by the first voltage input means. Then, the voltage is boosted from a low voltage to a high voltage, and in accordance with the boosting, the potential of one input terminal of the flip-flop circuit is set to the flip-flop by the second voltage input means. By boosting the potential of the memory cell power line from a low voltage to a high voltage in a time longer than the time constant of the flop circuit, the potential of the memory cell power supply line is interlocked with the boost of the potential of one input terminal of the flip-flop circuit. And boosting the voltage to a voltage .

  According to the present invention, disconnection of wiring due to electromigration caused by miniaturization of a memory element can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram of a logic circuit of the adiabatic charging memory according to the first embodiment of the present invention. The configuration of the adiabatic charging memory in this embodiment is an SRAM configuration in which a flip-flop circuit FF in which the CMOS inverter circuit IV1 and the CMOS inverter circuit IV2 are cross-connected is used as a memory cell.

First, the configuration of the flip-flop circuit FF in the present invention will be described. The CMOS inverter circuit IV1 includes a pMOS transistor P1 and an nMOS transistor N1 connected in series between the power supply unit PS and the ground power supply V _SS 1. Similarly, CMOS inverter circuit IV2 is constituted by the pMOS transistor P2 and the nMOS transistor N2 connected in series between the power supply unit PS and the ground power supply _{V SS} 2.

  The output of the CMOS inverter circuit IV1 (the drain electrodes of the pMOS transistor P1 and the nMOS transistor N1) is connected to the input of the CMOS inverter circuit IV2 (the gate electrodes of the pMOS transistor P2 and the nMOS transistor N2). An output of the inverter circuit IV2 (drain electrodes of the pMOS transistor P2 and the nMOS transistor N2) is connected to an input of the CMOS inverter circuit IV1 (gate electrodes of the pMOS transistor P1 and the nMOS transistor N1).

  Further, an nMOS transistor N3 is connected between the gate electrodes of the pMOS transistor P1 and the nMOS transistor N1 and the bit line BL of the memory cell array, and the gate electrode of the nMOS transistor N3 is connected to the word line WL of the memory cell array. Yes. Similarly, an nMOS transistor N4 is connected between the gate electrodes of the pMOS transistor P2 and the nMOS transistor N2 and the bit line NBL of the memory cell array, and the gate electrode of the nMOS transistor N4 is also connected to the word line WL of the memory cell array. ing.

  Next, the configuration of the power supply unit PS, which is a characteristic part of the present invention, will be described. The power supply unit PS includes a switch S1 and is connected to the source electrodes of the pMOS transistor P1 and the pMOS transistor P2 via a memory cell power supply line (hereinafter referred to as “MCPL”) 10.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of writing data will be described with reference to FIGS. FIG. 2 is a timing chart showing an operation when data is written to the adiabatic charging memory according to the present embodiment.

First, the switch S1 is turned ON, and the potential of the MCPL 10 (the potential of the source electrodes of the pMOS transistor P1 and the pMOS transistor P2) is gradually lowered from V _DD to GND by the adiabatic charging signal A1 input to the power supply unit PS. (T1 → t2).

  Next, the potential of the MCPL 10 is lowered to GND, and then the switch S1 is turned off (t2).

  Subsequently, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is waited (t3).

The adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. In response to the adiabatic charging signal A2, the potential of the bit line BL is gradually increased from GND to V _DD (t3 → t4). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. The potential of the MCPL 10 is also boosted from GND to V _DD in conjunction with it.

The potential of the adiabatic charge signal A1 is also gradually increased from GND to V _DD (t3 → t4), similarly to the change in potential due to the adiabatic charge signal A2. After the potential of the adiabatic charging signal A1 reaches V _DD (t4), the switch S1 is turned on. The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

In the case of the operation of the adiabatic charging memory in the present embodiment described above, as shown in FIG. 2, the potential of the adiabatic charging signal A1 is increased (t3 → t4) and the potential is increased by the adiabatic charging signal A2 (t3). → t4) is synchronized, but it may be asynchronous. That is, it is only necessary to turn on the switch S1 when the potentials of the MCPL 10 and the adiabatic charging signal A1 become equal (V _DD ). For example, boost the potential of the adiabatic charging signal A2 to V _DD , that is, boost the potential of the MCPL 10 to V _DD, then boost the potential of the adiabatic charging signal A1 to V _DD , and then turn on the switch S1. Is also possible.

  Next, the configuration of the switch S1 will be described. As the switch S1, an nMOS transistor or a pMOS transistor itself can be used. Alternatively, the switch S1 can be realized by connecting an nMOS transistor and a pMOS transistor in parallel.

Subsequently, the adiabatic charging signal A1 and the adiabatic charging signal A2 described above will be described. Adiabatic charging is a method in which charging is performed more slowly than the time constant of the circuit, and the term adiabatic is used to change the system very slowly in physics. Is used. In other words, the term “gradually lowering the potential from V _DD to GND” used when explaining the operation of the present embodiment means that “the time for reducing the potential V _DD to GND is based on the time constant of the flip-flop circuit FF. It means "long". Similarly, “slowly boost from GND to V _DD ” means that “the time during which the potential GND is boosted to V _DD is longer than the time constant of the flip-flop circuit FF” (hereinafter, This also applies to all embodiments).

  A specific circuit for gradually boosting and stepping down the potentials of the adiabatic charging signal A1 and the adiabatic charging signal A2 includes an AC power supply circuit using an inductor and a capacitor that uses a method of reusing charges, and a capacitor N−1. It is possible to use a power supply circuit that generates a single N-stage stepped voltage. The charge reuse is a method of reusing the charge by returning the charge charged to the load capacity from the power supply to the power supply again without throwing it back to the GND.

FIG. 3 shows an example of an AC power supply circuit using an inductor L and a capacitor C, and FIG. 4 shows an example of a power supply circuit that generates four stepped voltages using three capacitors C1 to C3. In FIG. 4, the power supply circuit for generating the stepped voltage includes four constant voltage power supplies V _DD , 3 / 4V _DD , 2 / 4V _DD , 1 / 4V _DD , three capacitors C1 to C3, and eight nMOS transistors. It is the structure provided with N5-N12. The three capacitors C1 to C3 are charged with voltages of 3 / 4V _DD , 2 / 4V _DD , and 1 / 4V _DD , respectively. The input signal Pre is applied to the gate electrodes of the three nMOS transistors N5 to N7, the input signals T1 to T4 are applied to the gate electrodes of the four nMOS transistors N8 to N11, and the input to the gate of one nMOS transistor N12. A signal CL is applied. In addition, the power supplies of 3 / 4V _DD , 2 / 4V _DD , and 1 / 4V _DD naturally charge the capacitors C1 to C3 to 3 / 4V _DD , 2 / 4V _DD , and 1 / 4V _DD , respectively, without these power supplies. Is in a stable state. First, the input signal Pre is set to High for a predetermined time, the nMOS transistors N5 to N7 are turned on, and the capacitors C1 to C3 are charged to voltages of 3 / 4V _DD , 2 / 4V _DD and 1 / 4V _DD , respectively. Next, the input signals T1 to T4 are set to High for a predetermined time in the order of T1, T2, T3, T4, T3, T2, and T1, and the nMOS transistors N8 to N11 are turned on to charge the capacitors C1 to C3. The voltages 3 / 4V _DD , 2 / 4V _DD , and 1 / 4V _DD are output as the output voltage Vout in a time-sharing manner. Finally, when the input signal T1 becomes Low, the input signal CL is set High and the nMOS transistor N12 is set for a predetermined time. The output voltage _{Vout is set} to the ground potential. By such timing control, the output voltage _Vout of the power supply circuit that generates the staircase voltage has a waveform having four steps on the rising and falling edges. In these power supply circuits, an AC waveform (repetitive waveform) in which the output voltage is gradually increased and gradually decreased can be obtained. In addition, as another example of the AC voltage generated in the power supply circuit that reuses the charge, a triangular wave shown in FIG. 5A and a trapezoidal wave shown in FIG. 5B can be used. Furthermore, voltage waveforms generated from the sine waves shown in FIGS. 5C, 5D, and 5E can be used. The generation of the triangular wave can be performed approximately by passing the voltage of the staircase waveform through the integrating circuit and allowing it to be smoothed, for example.

  Further, a resistance value that enables the voltage to be changed in a time longer by about one digit or more than the time constant of the flip-flop circuit when turned on as shown in FIG. 6 without reusing the charge. It is also possible to step up and down using an inverter using a large transistor. Specifically, there are a method of increasing the gate length, a method of reducing the transistor width, and a method of reducing the ion implantation doping concentration of the source and drain. Alternatively, a method for increasing the threshold voltage of the transistor may be used.

According to the present embodiment, the adiabatic charging signal A1 gradually decreases the potential of the MCPL 10 from V _DD to GND, and the adiabatic charging signal A2 gradually increases the potential of the bit line BL from GND to V _DD. Therefore, disconnection of the wiring inside the memory cell due to electromigration can be prevented. Further, since the potential of the bit line BL can be boosted from GND to V _DD by the adiabatic charging signal A2, data can be written into the adiabatic charging memory without supplying a voltage from the power supply unit PS to the MCPL 10. Further, by turning ON the switch S1 when the potential between the MCPL 10 and the adiabatic charging signal A1 becomes equal (V _DD ), the MCPL 10 and the adiabatic charging signal A1 can be connected without giving a potential difference. Similarly to the above, it is possible to prevent disconnection of wiring due to electromigration. In addition, when the potential of the bit line BL is boosted (t3 → t4), the switch S1 is turned OFF, so that the waste of power can be saved without the charging current to the adiabatic charging memory flowing into the power supply unit PS.

  The generation of the step waveform has been described with reference to the circuit of FIG. 4 using a capacitor. However, the circuit is not limited to this, and the circuit of FIG. 7 may be used. This may be repeated by setting the input signal to High in the order of T0, T1, T2, T3, T4, T3, T2, T1, and T0.

[Second Embodiment]
FIG. 8 is a timing chart showing an operation when data is written in the adiabatic charging memory according to the second embodiment of the present invention. Since the configuration in this embodiment is the same as that in the first embodiment, the description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS.

First, the switch S1 is turned ON, and the potential of the MCPL 10 (the potential of the source electrodes of the pMOS transistor P1 and the pMOS transistor P2) is gradually lowered from V _DD to GND by the adiabatic charging signal A1 input to the power supply unit PS. (T1 → t2).

  Next, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is waited (t3).

The adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. In response to the adiabatic charging signal A2, the potential of the bit line BL is gradually increased from GND to V _DD (t3 → t4). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. The potentials of the MCPL 10 and the adiabatic charging signal A1 are also boosted from GND to V _DD in conjunction with each other.

At the same time that the adiabatic charge signal A2 is boosted, the potential of the MCPL 10 is gradually increased from GND to V _DD by the adiabatic charge signal A1 (t3 → t4). Thereby, the written data can be held.

  Note that the configuration of the switch S1 and the power supply circuit that performs adiabatic charging are the same as those in the first embodiment, and thus the description thereof is omitted here.

According to the present embodiment, the adiabatic charging signal A1 gradually decreases the potential of the MCPL 10 from V _DD to GND, and the adiabatic charging signal A2 gradually increases the potential of the bit line BL from GND to V _DD. Therefore, disconnection of the wiring inside the memory cell due to electromigration can be prevented. Further, since the adiabatic charging signal A2 can be boosted and the potential of the MCPL 10 can be boosted from GND to V _DD by the adiabatic charging signal A1, high-speed operation can be performed.

[Third Embodiment]
FIG. 9 is a circuit diagram of a logic circuit of the adiabatic charging memory according to the third embodiment of the present invention. The power supply unit PS in the present embodiment includes a switch S1 that connects the power supply voltage V _DD and the MCPL10, and a switch S2 that connects the adiabatic charging signal A1 and the MCPL10. Since other configurations are the same as those in the first embodiment, description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS. FIG. 10 is a timing chart illustrating an operation when data is written to the adiabatic charging memory according to the present embodiment.

First, switch S1 is switched from ON to OFF, switch S2 is switched from OFF to ON, and the potential of MCPL10 (the potential of the source electrode of pMOS transistor P1 and pMOS transistor P2) is gradually decreased from V _DD to GND by adiabatic charging signal A1. Decrease (t1 → t2).

  Next, after the potential of the MCPL 10 is lowered to GND, the switch S2 is turned OFF, and the MCPL 10 is brought into a high impedance state (t2).

  Subsequently, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is waited (t3).

The adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. In response to the adiabatic charging signal A2, the potential of the bit line BL is gradually increased from GND to V _DD (t3 → t4). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. The potential of the MCPL 10 is also boosted from GND to V _DD in conjunction with it.

Thereafter, the switch S1 is turned on (t4). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the first embodiment, the description thereof is omitted here.

  According to the present embodiment, not only the adiabatic charging signal A1 but also the constant voltage power supply line can be used together to provide a constant potential to the flip-flop circuit, so that data can be retained. Since other effects are the same as those of the first embodiment, description thereof is omitted here.

[Fourth Embodiment]
FIG. 11 is a timing chart showing an operation when data is written in the adiabatic charging memory according to the fourth embodiment of the present invention. Since the configuration in the present embodiment is the same as that in the third embodiment, the description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS.

First, switch S1 is switched from ON to OFF, switch S2 is switched from OFF to ON, and the potential of MCPL10 (the potential of the source electrode of pMOS transistor P1 and pMOS transistor P2) is gradually decreased from V _DD to GND by adiabatic charging signal A1. Decrease (t1 → t2).

  Next, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is waited (t3).

The adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. Without changing the state of the switch S2, the potential of the bit line BL is gradually increased from GND to V _DD by the adiabatic charging signal A2 (t3 → t4). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. The potential of the MCPL 10 is also boosted from GND to V _DD in conjunction with it.

At the same time that the adiabatic charge signal A2 is boosted, the potential of the MCPL 10 is gradually increased from GND to V _DD by the adiabatic charge signal A1 (t3 → t4).

Thereafter, the switch S2 is turned from ON to OFF, and the switch S1 is turned from OFF to ON (t4). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the third embodiment, the description thereof is omitted here.

  According to the present embodiment, not only the adiabatic charging signal A1 but also the constant voltage power supply line can be used together to provide a constant potential to the flip-flop circuit, so that data can be retained. Other effects are the same as those in the second embodiment, and thus the description thereof is omitted here.

[Fifth Embodiment]
FIG. 12 is a timing chart showing an operation when data is written to the adiabatic charging memory according to the fifth embodiment of the present invention. Since the configuration in the present embodiment is the same as that in the third embodiment, the description thereof is omitted here.

In the third and fourth embodiments, the minimum voltage V _{low of the} MCPL 10 is set to GND (0 V). However, the present invention is not limited to this, and may be set to V _DD / 2, for example. . Generally, the minimum voltage V _low may be less than V _DD . In particular, when the minimum voltage V _{low is set} to k × V _DD (0 ≦ k ≦ 2/3), the waveform that rises and falls slowly and the constant power supply voltage V _DD can be more clearly differentiated.

  Next, the operation of the adiabatic charging memory according to this embodiment, particularly the operation at the time of data writing will be described with reference to FIGS.

First, the switch S1 is switched from ON to OFF, the switch S2 is switched from OFF to ON, and the potential of the MCPL10 (the potential of the source electrodes of the pMOS transistor P1 and the pMOS transistor P2) is changed from V _DD to V _DD / 2 by the adiabatic charging signal A1. Is gradually lowered (t1 → t2).

Next, after the potential of the MCPL 10 is lowered to V _DD / 2, the switch S2 is turned from ON to OFF, and the MCPL 10 is brought into a high impedance state (t2).

Subsequently, the adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. In response to the adiabatic charging signal A2, the potential of the bit line BL is gradually increased from GND to V _DD / 2 (t3 → t4).

Thereafter, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of the signals from the bit line BL and the bit line NBL is waited (t5). By adiabatic charging signal A2, is gradually boosted the potential of the bit line BL from _{V DD} / 2 to _{V DD} (t5 → t6). Thereby, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. It is boosted to _{V DD} from _{V DD} / 2 in conjunction also for the potential of MCPL10.

Thereafter, the switch S1 is turned on (t7). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the third embodiment, the description thereof is omitted here.

According to the present embodiment, since it is not necessary to lower the potential of the MCPL 10 from V _DD to GND, higher speed operation is possible during data writing. Since other effects are the same as those of the first embodiment, description thereof is omitted here.

[Sixth Embodiment]
FIG. 13 is a timing chart showing an operation when data is written to the adiabatic charging memory according to the sixth embodiment of the present invention. Since the configuration in the present embodiment is the same as that in the third embodiment, the description thereof is omitted here.

The operation in the present embodiment is such that the minimum voltage V _{low of the} MCPL 10 is, for example, V _DD / 2, as in the fifth embodiment, but unlike the fifth embodiment, the switch S2 is used during data writing. It has the feature which makes the state of ON.

First, the switch S1 is switched from ON to OFF, the switch S2 is switched from OFF to ON, and the potential of the MCPL10 (the potential of the source electrodes of the pMOS transistor P1 and the pMOS transistor P2) is changed from V _DD to V _DD / 2 by the adiabatic charging signal A1. Is gradually lowered (t1 → t2).

Next, the adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. In response to the adiabatic charging signal A2, the potential of the bit line BL is gradually increased from GND to V _DD / 2 (t3 → t4).

Thereafter, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of the signals from the bit line BL and the bit line NBL is waited (t5). Then, without changing the state of the switch S2, the adiabatic charging signal A2, it is slowly raised to the potential of the bit line BL _{V DD} / 2 from _{V DD} (t5 → t6). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. It is boosted to _{V DD} from _{V DD} / 2 in conjunction also for the potential of MCPL10.

The potential of the adiabatic charging signal A1 is also gradually increased from GND to V _DD in the same manner as the potential change caused by the adiabatic charging signal A2 (t5 → t6).

And at the same time boosting the adiabatic charging signal A2, it is slowly raised to _{V DD} by adiabatic charging signal A1 the potential of MCPL10 from _{V DD / 2 (t5 → t6} ).

Thereafter, the switch S2 is turned off and the switch S1 is turned on (t7). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the third embodiment, the description thereof is omitted here.

According to the present embodiment, since it is not necessary to lower the potential of the MCPL 10 from V _DD to GND, higher speed operation is possible during data writing. Other effects are the same as those in the second embodiment, and thus the description thereof is omitted here.

[Seventh Embodiment]
FIG. 14 is a circuit diagram of a logic circuit of the adiabatic charging memory according to the seventh embodiment of the present invention. The power supply section PS in the present embodiment includes a switch S1 that connects the constant voltage power supply line V1 having the potential V _DD and the MCPL10, and a switch S2 that connects the constant voltage power supply line V2 having the GND potential and the MCPL10. It is a configuration. The switch S1 and the switch S2 include a transistor having a large resistance value that changes the potential input to the flip-flop circuit in a time longer than the time constant of the flip-flop circuit. Since other configurations are the same as those in the first embodiment, description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS. FIG. 15 is a timing chart showing an operation when data is written in the adiabatic charging memory according to the present embodiment.

First, by switching the switch S1 from ON to OFF and the switch S2 from OFF to ON, the potential of the MCPL 10 (the potential of the source electrodes of the pMOS transistor P1 and the pMOS transistor P2) is gradually lowered from V _DD to GND ( t1 → t2).

  Next, after the potential of the MCPL 10 is lowered to GND, the switch S2 is turned from ON to OFF, and the MCPL 10 is brought into a high impedance state (t2).

  Subsequently, ON is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is waited (t3).

The adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. Then, the adiabatic charging signal A2 is gradually increased from GND to V _DD (t4 → t5). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. The potential of the MCPL 10 is also boosted from GND to V _DD in conjunction with it.

Thereafter, the switch S1 is turned on (t5). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the first embodiment, the description thereof is omitted here.

According to the present embodiment, the potential of the MCPL 10 can be gradually lowered from V _DD to GND by operating the switch S1 and the switch S2 using the constant voltage power supply line V1 and the constant voltage power supply line V2. This can prevent disconnection of the wiring inside the memory cell.

[Eighth Embodiment]
FIG. 16 is a timing chart showing an operation when data is written to the adiabatic charging memory according to the eighth embodiment of the present invention. Since the configuration of this embodiment is the same as that of the seventh embodiment, description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS.

First, by switching the switch S1 from ON to OFF and the switch S2 from OFF to ON, the potential of the MCPL 10 (the potential of the source electrodes of the pMOS transistor P1 and the pMOS transistor P2) is gradually lowered from V _DD to GND ( t1 → t2).

  Next, ON is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is awaited (t3).

By switching the switch S2 from ON to OFF and the switch S1 from OFF to ON, the potential of the MCPL 10 is gradually increased from GND to _VDD by the constant voltage power line V1 (t4 → t5).

At the same time as boosting the potential of the MCPL 10, the adiabatic charging signal A2 is input to the bit line BL, and the adiabatic charging signal A2 is gradually boosted from GND to V _DD (t4 → t5). With both the constant voltage power supply line V1 and the adiabatic charging signal A2, the adiabatic charging memory can be slowly charged to write data. Further, since the potential of the MCPL 10 is fixed to V _DD by the constant voltage power supply line V1, written data can be held.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the seventh embodiment, the description thereof is omitted here.

According to the present embodiment, the potential of the MCPL 10 can be gradually lowered from V _DD to GND by operating the switch S1 and the switch S2 using the constant voltage power supply line V1 and the constant voltage power supply line V2. This can prevent disconnection of the wiring inside the memory cell.

[Ninth Embodiment]
FIG. 17 is a timing chart showing an operation when data is written to the adiabatic charging memory according to the ninth embodiment of the present invention. Unlike the seventh and eighth embodiments, in the present embodiment, the voltage of the constant voltage power supply line V2 is set to V _DD / 2. Since other configurations are the same as those of the seventh embodiment, the description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS.

First, the switch S1 is switched from ON to OFF and the switch S2 is switched from OFF to ON, thereby lowering the potential of the MCPL 10 (the potential of the source electrode of the pMOS transistor P1 and the pMOS transistor P2) from V _DD to V _DD / 2. (T1 → t2).

Next, after the potential of the MCPL 10 is lowered to V _DD / 2, the switch S2 is turned from ON to OFF, and the MCPL 10 is brought into a high impedance state (t2).

Subsequently, the adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. The adiabatic charging signal A2 is gradually increased from GND to V _DD / 2 (t3 → t4).

Enter the ON to the word line WL, and the nMOS transistor N3 and the nMOS transistor N4 is changed to the state ON, the gently raised to _{V DD} adiabatic charging signal A2 from _{V DD / 2 (t4 → t5} ). At this time, the potential of MCPL10 is gently raised to _{V DD} from _{V DD} / 2 in conjunction with the potential of the adiabatic charging signal A2.

Thereafter, the switch S1 is turned on (t5). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the seventh embodiment, the description thereof is omitted here.

According to the present embodiment, since it is not necessary to lower the potential of the MCPL 10 from V _DD to GND, higher speed operation is possible during data writing. Since other effects are the same as those of the first embodiment, description thereof is omitted here.

[Tenth embodiment]
FIG. 18 is a timing chart showing an operation when data is written to the adiabatic charging memory according to the tenth embodiment of the present invention. Unlike the seventh and eighth embodiments, in the present embodiment, the voltage of the constant voltage power supply line V2 is set to V _DD / 2. Since other configurations are the same as those of the seventh embodiment, the description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of data writing will be described with reference to FIGS.

First, the switch S1 is switched from ON to OFF and the switch S2 is switched from OFF to ON, thereby lowering the potential of the MCPL 10 (the potential of the source electrode of the pMOS transistor P1 and the pMOS transistor P2) from V _DD to V _DD / 2. (T1 → t2).

Next, the adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. The adiabatic charging signal A2 is gradually increased from GND to V _DD / 2 (t3 → t4).

ON is input to the word line WL, and the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state. Then, OFF the switch S2 from ON, by the ON switch S1 from OFF, it is slowly raised to the constant-voltage power supply line V1 to the potential of MCPL10 from _{V DD / 2 V DD (t4} → t5).

And at the same time boosting the potential of MCPL10, it is slowly raised to _{V DD} adiabatic charging signal A2 from _{V DD / 2 (t4 → t5} ). Accordingly, the adiabatic charging memory can be slowly charged and data can be written by both the constant voltage power supply line V1 and the adiabatic charging signal A2. Further, since the potential of the MCPL 10 is fixed to V _DD by the constant voltage power supply line V1, written data can be held.

  Since the configuration of the switch S1 (including the switch S2) and the power supply circuit that performs adiabatic charging are the same as those in the seventh embodiment, the description thereof is omitted here.

According to this embodiment, since it is not necessary to lower the potential of the MCPL 10 from V _DD to GND, a higher speed operation can be performed at the time of data writing. Other effects are the same as those in the second embodiment, and thus the description thereof is omitted here.

[Eleventh embodiment]
FIG. 19 is a circuit diagram of a logic circuit of the adiabatic charging memory according to the eleventh embodiment of the present invention. Power unit PS in this embodiment, the switch S2 connects the switches S1, the potential _{V DD} / 2 constant-voltage power supply line V2 and MCPL10 with connecting the MCPL10 the constant-voltage power supply line V1 having a potential _{V DD} and, This is a configuration including a switch S3 that connects the constant voltage power supply line V3 having the GND potential and the MCPL10. Each of the switches S1 to S3 includes a transistor having a large resistance value that changes the potential input to the flip-flop circuit in a time longer than the time constant of the flip-flop circuit. Since other configurations are the same as those in the first embodiment, description thereof is omitted here. In the present embodiment, the potential of the constant voltage power supply line V2 is described as V _DD / 2. The potential of the constant voltage power supply line V2 may be between the potentials of the constant voltage power supply line V1 and the constant voltage power supply line V3.

  Next, the operation of the adiabatic charging memory according to this embodiment, particularly the operation at the time of data writing will be described with reference to FIGS. FIG. 20 is a timing chart illustrating an operation when data is written to the adiabatic charging memory according to the present embodiment.

First, OFF the switch S1 from the ON, by the ON switch S2 from OFF, gently potential of MCPL10 the (potential of the source electrode of the pMOS transistor P1 and the pMOS transistor P2) to _{V DD} / 2 from _{V DD} Decrease (t1 → t2).

Next, by switching the switch S2 from ON to OFF and the switch S3 from OFF to ON, the potential of the MCPL 10 is gradually lowered from V _DD / 2 to GND (t2 → t3).

  Subsequently, after the potential of the MCPL 10 is lowered to GND, the switch S3 is turned from ON to OFF, and the MCPL 10 is brought into a high impedance state (t3).

  High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is awaited (t4).

The adiabatic charging signal A2 is input to the bit line BL, and the GND signal is input to the bit line NBL. The adiabatic charging signal A2 is gradually increased from GND to V _DD / 2 (t5 → t6). Further, the voltage is gradually increased from V _DD / 2 to V _DD (t6 → t7). Thereby, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory can be slowly charged to write data. The potential of the MCPL 10 is also boosted from GND to V _DD / 2, and V _DD / 2 to V _DD in conjunction with each other.

Thereafter, the switch S1 is turned on (t7). The potential of MCPL10 by fixing to _{V DD,} can hold the written data.

  The method for boosting the adiabatic charging signal A2 described above has two steps (t5 → t6, t6 → t7), but it can be performed in one step or three or more steps.

  Since the configuration of the switch S1 (including the switch S2 and the switch S3) and the power supply circuit that performs adiabatic charging are the same as those in the first embodiment, the description thereof is omitted here.

  According to the present embodiment, the potential of the MCPL 10 can be gently lowered by the operation of the switches S1 to S3, and the voltage of the bit line BL can be gradually raised by the adiabatic charging signal A2, so that the data Wiring disconnection due to electromigration during writing can be prevented.

[Twelfth embodiment]
FIG. 21 is a circuit diagram of a logic circuit of the adiabatic charging memory according to the twelfth embodiment of the present invention. Since the configuration of this embodiment is the same as that of the eleventh embodiment, the description thereof is omitted here.

  Next, the operation of the adiabatic charging memory according to the present embodiment, particularly the operation at the time of writing data will be described with reference to FIGS.

First, OFF the switch S1 from the ON, by the ON switch S2 from OFF, gently potential of MCPL10 the (potential of the source electrode of the pMOS transistor P1 and the pMOS transistor P2) to _{V DD} / 2 from _{V DD} Decrease (t1 → t2).

Next, by switching the switch S2 from ON to OFF and the switch S3 from OFF to ON, the potential of the MCPL 10 is gradually lowered from V _DD / 2 to GND (t2 → t3).

  Subsequently, High is input to the word line WL, the nMOS transistor N3 and the nMOS transistor N4 are changed to the ON state, and the input of signals from the bit line BL and the bit line NBL is waited (t4).

By switching the switch S3 from ON to OFF and the switch S2 from OFF to ON, the potential of the MCPL 10 is gradually increased from GND to V _DD / 2 by the constant voltage power supply line V2 (t5 → t6). At the same time, the adiabatic charging signal A2 is gradually increased from GND to V _DD / 2 (t5 → t6).

Thereafter, OFF the switch S2 from ON, by the ON switch S1 from OFF, it is slowly raised to the constant-voltage power supply line V1 to the potential of MCPL10 from _{V DD / 2 V DD (t6} → t7). At the same time, to be gradually raised to _{V DD} the adiabatic charging signal A2 from _{V DD / 2 (t6 → t7} ). Accordingly, the adiabatic charging memory can be slowly charged and data can be written by both the constant voltage power supply line V1 and the constant voltage power supply line V2 and the adiabatic charging signal A2. Further, since the potential of the MCPL 10 is fixed to V _DD by the constant voltage power supply line V1, written data can be held.

  Since the configuration of the switch S1 (including the switch S2 and the switch S3) and the power supply circuit that performs adiabatic charging are the same as those in the first embodiment, the description thereof is omitted here.

  According to the present embodiment, the potential of the MCPL 10 can be gradually lowered by the operation of the switches S1 to S3, and further, the voltage is applied by both the constant voltage power supply line V1, the constant voltage power supply line V2, and the adiabatic charge signal A2. Since the voltage can be gradually increased, wiring disconnection due to electromigration during data writing can be prevented.

[Thirteenth embodiment]
FIG. 22 is a circuit diagram of a logic circuit of the adiabatic charging memory according to the thirteenth embodiment of the present invention. The configuration of the adiabatic charging memory according to the present embodiment is a configuration in which the power supply unit PS and the MCPLs 10 of the plurality of adiabatic charging memories are connected via a shared power line. In FIG. 22, the power supply unit PS has the same configuration as the power supply unit PS described in the eleventh embodiment, but is not limited thereto.

  According to the present embodiment, a plurality of adiabatic charging memories can be controlled by a single power supply unit PS via a shared power supply line, so that the number of power supply units PS (transistors constituting the power supply unit PS) can be reduced. Can do.

[Fourteenth embodiment]
FIG. 23 is a circuit diagram of a transistor according to the fourteenth embodiment of the present invention. The configuration of the transistor of this embodiment is a transfer transistor in which a word line WL is connected to a gate electrode and a bit line BL is connected to a source electrode, and the voltage input to the word line WL is slowly charged. To do.

First, the operation of a conventional transistor will be described. As shown in FIG. 24, the bit line BL is boosted from GND to V _DD , and then the word line WL is boosted from GND to V _DD at the same speed as the time constant of the memory cell. As a result, the output voltage OUT rises at the same speed as the time constant of the memory cell.

Next, the operation of the transistor in this embodiment will be described. As shown in FIG. 25, the word line WL is boosted from GND to V _DD sufficiently more slowly than the time constant of the memory cell. At this time, after the word line WL reaches the threshold voltage (t3), this transistor is turned on, and the output voltage OUT rises more slowly than the time constant of the memory cell.

  The transistors in this embodiment can be used as the nMOS transistors N3 and N4 described in the first to thirteenth embodiments and the switches.

  According to the present embodiment, the voltage can be gradually increased by gently charging the word line instead of gently charging the bit line, thereby preventing wiring disconnection due to electromigration during data writing. Can do.

It is a circuit diagram of the logic circuit of the adiabatic charging memory of the first embodiment. It is a timing chart figure which shows operation in the case of writing data in adiabatic charge memory of a 1st embodiment. FIG. 3 is a circuit diagram of an AC power supply circuit using an inductor L and a capacitor C as a power supply circuit for reusing charges. FIG. 3 is a circuit diagram of a power supply circuit that generates a staircase voltage as a power supply circuit that reuses charges. It is a figure which shows another voltage waveform etc. as a power supply circuit which reuses an electric charge. It is a circuit diagram of an inverter with a large resistance value used as a method of not reusing electric charges. It is a circuit diagram which shows another example of the power supply circuit which generate | occur | produces a step-like voltage as a power supply circuit which reuses an electric charge. It is a timing chart figure which shows operation in the case of writing data in adiabatic charge memory of a 2nd embodiment. It is a circuit diagram of the logic circuit of the heat insulation charge memory of 3rd Embodiment. It is a timing chart figure which shows the operation | movement in the case of writing data in the heat insulation charge memory of 3rd Embodiment. It is a timing chart figure which shows operation in the case of writing data in adiabatic charge memory of a 4th embodiment. It is a timing chart figure which shows operation in the case of writing data in the heat insulation charge memory of a 5th embodiment. It is a timing chart figure which shows operation in the case of writing data in adiabatic charge memory of a 6th embodiment. It is a circuit diagram of the logic circuit of the heat insulation charge memory of 7th Embodiment. It is a timing chart figure which shows the operation in the case of writing data in the heat insulation charge memory of a 7th embodiment. It is a timing chart figure which shows operation in the case of writing data in the heat insulation charge memory of an 8th embodiment. It is a timing chart figure showing operation in the case of writing data in adiabatic charge memory of a 9th embodiment. It is a timing chart figure which shows operation in the case of writing data in the heat insulation charge memory of a 10th embodiment. It is a circuit diagram of the logic circuit of the heat insulation charge memory of 11th Embodiment. It is a timing chart figure showing operation in the case of writing data in the heat insulation charge memory of an 11th embodiment. It is a timing chart figure which shows operation in the case of writing data in the heat insulation charge memory of a 12th embodiment. It is a circuit diagram of the logic circuit of the heat insulation charge memory of 13th Embodiment. It is a circuit diagram of the transistor in 14th Embodiment. It is a timing chart which shows operation | movement of the conventional transistor. It is a timing chart figure showing operation of a transistor in a 14th embodiment. It is a circuit diagram which shows the logic circuit of the conventional SRAM.

Explanation of symbols

A1, A2 ... adiabatic charging signals BL, NBL ... bit lines C, C1-C3 ... capacitors CL ... input signals FF ... flip-flop circuits IV1, IV2 ... CMOS inverter circuits L ... inductors N1-N12 ... nMOS transistors P1, P2 ... pMOS transistor PS ... power supply unit Pre ... input signal S1 to S3 ... switch T0 to T4 ... input signal V1 to V3 ... constant-voltage power supply line _{V ss 1,} V _ss 2 ... ground power WL ... word lines 10 ... memory cell power supply line (MCPL )

Claims (8)

A flip-flop circuit in which CMOS inverter circuits composed of a pMOS transistor and an nMOS transistor connected in series are complementarily connected;
First voltage input means for inputting a voltage to be changed over a time longer than the time constant of the flip-flop circuit to the source electrode of each pMOS transistor through a memory cell power line;
Second voltage input means for inputting, to one input terminal of the flip-flop circuit, a voltage to be changed in a time longer than a time constant of the flip-flop circuit;
A first switch element provided between a constant voltage power source and the memory cell power source line;
A second switch element provided between the first voltage input means and the memory cell power line,
With the first switch element off and the second switch element on, the first voltage input means increases the potential of the memory cell power supply line for a time longer than the time constant of the flip-flop circuit. Step down from voltage to low voltage,
After the potential of the memory cell power supply line becomes a low voltage, the second switch element is turned off,
While the first switch element and the second switch element are off, the potential of the other input terminal of the flip-flop circuit is fixed to a low voltage, and the flip-flop is connected by the second voltage input means. By boosting the potential of one input terminal of the circuit from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit, the potential of the memory cell power supply line is increased at one input terminal of the flip-flop circuit. An adiabatic charging memory circuit, wherein voltage is boosted from a low voltage to a high voltage in conjunction with a potential boost . A flip-flop circuit in which CMOS inverter circuits composed of a pMOS transistor and an nMOS transistor connected in series are complementarily connected;
First voltage input means for inputting a voltage to be changed over a time longer than the time constant of the flip-flop circuit to the source electrode of each pMOS transistor through a memory cell power line;
Second voltage input means for inputting, to one input terminal of the flip-flop circuit, a voltage to be changed in a time longer than a time constant of the flip-flop circuit;
A first switch element provided between a constant voltage power source and the memory cell power source line;
A second switch element provided between the first voltage input means and the memory cell power line,
With the first switch element off and the second switch element on, the first voltage input means increases the potential of the memory cell power supply line for a time longer than the time constant of the flip-flop circuit. Step down from voltage to low voltage,
After the potential of the memory cell power supply line becomes a low voltage, the potential of the other input terminal of the flip-flop circuit is set to a low voltage with the first switch element turned off and the second switch element turned on. And the first voltage input means boosts the potential of the memory cell power supply line from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit, and in accordance with the boosting, By boosting the potential of one input terminal of the flip-flop circuit from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit by the voltage input means of 2, the potential of the memory cell power supply line is increased. one of adiabatic charging memory circuit you characterized in that in conjunction to the boosting boosts the low voltage to a high voltage potential at the input terminal of the flip-flop circuit. The first voltage input means includes
Wherein are respectively connected between the memory cell power supply lines and a plurality of constant-voltage power supply line, and a plurality of switching elements for inputting the constant voltage output from each constant-voltage power supply line before Symbol memory cell power supply line,
A control circuit that changes the potential of the memory cell power line in a time longer than the time constant of the flip-flop circuit by sequentially switching on and off the plurality of switch elements;
Adiabatic charging memory circuit according to claim 1 or 2, characterized in that it has a. The second voltage input means includes
A transfer transistor in which a drain electrode, a source electrode, and a gate electrode are respectively connected to one input terminal, a bit line, and a word line of the flip-flop circuit;
An adiabatic charging circuit that boosts the potential of the bit line from a low voltage to a high voltage in a time longer than a time constant of the flip-flop circuit,
3. The adiabatic charging according to claim 1, wherein the potential of the bit line is boosted by the adiabatic charging circuit after the potential of the word line is set to a high voltage and the transfer transistor is turned on. Memory circuit. The second voltage input means includes
A transfer transistor in which a drain electrode, a source electrode, and a gate electrode are respectively connected to one input terminal , a bit line , and a word line of the flip-flop circuit;
The potential of the word line is boosted from a low voltage to a high voltage so that the potential input to one input terminal of the flip-flop circuit is boosted from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit. anda adiabatic charging circuit for,
3. The adiabatic charging memory circuit according to claim 1 , wherein the potential of the bit line is set to a high voltage before the potential of the word line reaches the threshold voltage of the transfer transistor . The low voltage of the memory cell power supply line, adiabatic charging memory circuit according to any one of claims 1 to 5, characterized in that less than 2/3 of the GND or more and a high voltage. A flip-flop circuit in which CMOS inverter circuits composed of a pMOS transistor and an nMOS transistor connected in series are complementarily connected ;
First voltage input means for inputting a voltage to be changed over a time longer than the time constant of the flip-flop circuit to the source electrode of each pMOS transistor through a memory cell power line;
Second voltage input means for inputting, to one input terminal of the flip-flop circuit, a voltage to be changed in a time longer than a time constant of the flip-flop circuit;
A first switch element provided between a constant voltage power source and the memory cell power source line;
A data writing method performed using an adiabatic charging memory circuit having a second switch element provided between the first voltage input means and the memory cell power supply line ,
With the first switch element off and the second switch element on, the first voltage input means increases the potential of the memory cell power supply line for a time longer than the time constant of the flip-flop circuit. Step down from voltage to low voltage;
Turning off the second switch element after the potential of the memory cell power line becomes low;
While the first switch element and the second switch element are off, the potential of the other input terminal of the flip-flop circuit is fixed to a low voltage, and the flip-flop is connected by the second voltage input means. By boosting the potential of one input terminal of the circuit from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit, the potential of the memory cell power supply line is increased at one input terminal of the flip-flop circuit. Stepping up from a low voltage to a high voltage in conjunction with the boosting of the potential ;
A data writing method comprising: A flip-flop circuit in which CMOS inverter circuits composed of a pMOS transistor and an nMOS transistor connected in series are complementarily connected ;
First voltage input means for inputting a voltage to be changed over a time longer than the time constant of the flip-flop circuit to the source electrode of each pMOS transistor through a memory cell power line;
Second voltage input means for inputting, to one input terminal of the flip-flop circuit, a voltage to be changed in a time longer than a time constant of the flip-flop circuit;
A first switch element provided between a constant voltage power source and the memory cell power source line;
A data writing method performed using an adiabatic charging memory circuit having a second switch element provided between the first voltage input means and the memory cell power supply line ,
With the first switch element off and the second switch element on, the first voltage input means increases the potential of the memory cell power supply line for a time longer than the time constant of the flip-flop circuit. Step down from voltage to low voltage;
After the potential of the memory cell power supply line becomes a low voltage, the potential of the other input terminal of the flip-flop circuit is set to a low voltage with the first switch element turned off and the second switch element turned on. And the first voltage input means boosts the potential of the memory cell power supply line from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit, and in accordance with the boosting, By boosting the potential of one input terminal of the flip-flop circuit from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit by the voltage input means of 2, the potential of the memory cell power supply line is increased. Stepping up from a low voltage to a high voltage in conjunction with boosting the potential of one input terminal of the flip-flop circuit;
A data writing method comprising:

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