JP4776419B2 - Synchronization control method and synchronization control apparatus - Google Patents

Description

  The present invention relates to a synchronous control method and a synchronous control device for synchronizing an output voltage phase of an AC output power converter such as an inverter with a voltage phase of another AC power source.

  FIG. 4 is a block diagram showing a conventional synchronous control device described in Patent Document 1. In FIG. FIG. 4 shows a synchronous control device applied to an uninterruptible power supply. In the figure, 1 is an AC power supply for bypass circuit, 2 is an AC input power supply, 3 is an uninterruptible power supply, and 4 is a load. The numbers in the 10th range indicate the main components of the uninterruptible power supply 3, 11 is a rectifier, 12 is a storage battery, 13 is an inverter, 14 and 15 are switches as switches, and 16 is an AC power supply for bypass circuit 1. And a voltage sensor 17 for detecting the voltage of the AC input power supply 2, and 17 is a synchronous control device for the uninterruptible power supply 3.

Numbers in the 20s indicate main components of the synchronous control device 17, 21 is a CPU (microprocessor), 22 is a memory for storing programs and data, 23 is an analog signal detected by the voltage sensor 16, and is a digital signal 24 is a pulse width modulation (PWM) circuit that generates a switching command for the inverter 13 from the voltage command of the CPU 21, 25 is an oscillator that oscillates the reference frequency fa, and 26 is a frequency division command N for the CPU 21. The rate multi as a variable frequency circuit that outputs the frequency fb (= fa × N / N ₀ , N = ₀ to N ₀ ), 27 is a counter as a frequency divider that divides the frequency fb by K, An interrupt signal is output to the CPU 21 every round.

  Next, the operation of the uninterruptible power supply shown in FIG. 4 will be described. When the AC input power supply 2 is normal, the rectifier 11 supplies the DC power to the inverter 13 while charging the storage battery 12, and the inverter 13 supplies the AC power to the load 4 via the switch 14. When the AC input power supply 2 fails, the rectifier 11 stops and the inverter 13 converts the DC power of the storage battery 12 into AC and supplies it to the load 4 via the switch 14. The switch 15 is normally in an off state and the switch 14 is in an on state. However, when the load 4 is overloaded and exceeds the power supply capacity of the inverter 13, or when the inverter 13 fails, the switch 14 is turned off, the switch 15 is turned on, and power is supplied from the AC power supply 1 for the bypass circuit to the load 4.

  At this time, by setting the phase of the output voltage of the bypass circuit AC power supply 1 and the inverter 13 to the same phase, it is possible to stably switch from the inverter power supply to the bypass power supply without giving a sudden phase change to the load 4. In addition, even when switching from bypass power supply to inverter power supply after canceling the overload state or after restoring the inverter failure, by setting the phase of the output voltage of the bypass circuit AC power supply 1 and the inverter 13 to the same phase, A sudden phase change to the load 4 can be eliminated.

  In the synchronous control device 17, the output voltage Vinv of the inverter 13 is detected by the voltage sensor 16 and converted into a digital signal by the analog / digital conversion circuit 23, so that the output voltage Vinv of the inverter 13 matches the output voltage command value. Then, the control calculation is performed using the CPU 21 and the memory 22, and the voltage command value is written in the PWM circuit 24. The PWM circuit 24 outputs a switching command for the inverter 13 by comparing a voltage signal with a carrier signal such as a triangular wave. Here, in order to make the output voltage Vinv of the inverter 13 and the AC power supply 1 for the bypass circuit in the same phase, first, it is necessary to have phase information in the same phase as the AC power supply 1 for the bypass circuit.

In FIG. 4, a digital synchronous control device is constituted by an oscillator 25, a rate multi 26, a counter 27, and a CPU 21 that performs arithmetic processing. FIG. 5 shows an example of timing in the synchronization control device 17. For example, when a 1/2 frequency division command is given to the rate multi 26 (N / N ₀ = 1/2), the output frequency fb is 1 of the output frequency fa of the oscillator 25 as shown in FIG. The frequency is / 2. When the counter 27 is an up / down counter, the output value fb of the rate multi 26 is divided, and the count value changes like a triangular wave. The counter 27 generates an output pulse fc at the peaks and troughs of the triangular wave to generate an interrupt signal to the CPU 21, and performs sampling control of the output voltage of the inverter 13 for each interrupt signal. For example, when the interrupt is 200 times per cycle, the phase information is advanced by 2π / 200 for each interrupt, and a voltage command value is created from this phase information. Therefore, the phase difference between the phase information and the AC power supply for the bypass circuit is obtained and controlled to zero.

  FIG. 6 shows a program flowchart executed by the CPU 21. This program is started at every frequency division ratio (every interrupt) set by the frequency divider, similarly to the voltage control of the inverter 13. Each process will be described below. First, in STEP 10, each phase voltage VBu, VBv, VBw of the bypass circuit three-phase AC power supply 1 is converted into a digital signal by the analog / digital conversion circuit 23. In STEP 20, the phase counter stored in the memory 22 is incremented. For example, when performing 200 interrupts per cycle, the phase counter is a modulo counter from 0 to 199.

  In STEP 30, the next sin and cos are read from the sine wave data table using the value of the phase counter.

sinU = sin (2πC / C ₀ ) (1)
sinV = sin (2πC / C ₀ −2π / 3) (2)
sinW = sin (2πC / C ₀ + 2π / 3) (3)
cosU = cos (2πC / C ₀ ) (4)
cosV = cos (2πC / C ₀ −2π / 3) (5)
cosW = cos (2πC / C ₀ + 2π / 3) (6)
However, C is the phase counter value in a program, C ₀ is the interrupt number per cycle.

  Next, in STEP 40, the detected bypass phase voltages VBu, VBv, VBw and the sinU, sinV, sinW, cosU, cosV, cosW obtained by the above equations (1) to (6) on the phase counter of the program. Bypass AC input voltage d-axis component and q-axis component are obtained.

FIG. 7 is a vector display of the bypass AC input voltage on the dq axis. It can be seen that the phase difference between the bypass AC input voltage and the program phase counter is equal to the phase difference between the bypass AC input voltage vector and the d-axis. In STEP 50, the phase difference dθ between the bypass AC input voltage vector and the program phase counter (d-axis) is calculated. In STEP 60, PI calculation is performed on the phase difference dθ by the following equation.
OUT = Kp (1 + Ki / S) × dθ
Here, Kp is a proportional gain, Ki is an integral gain, and S is a Laplace operator.

  When the phase difference dθ is advanced by the bypass AC input voltage, the PI calculation result OUT is adjusted in the positive direction, and when the phase difference dθ is delayed by the bypass AC input voltage, the PI calculation result OUT is adjusted in the negative direction. In STEP 70, the PI calculation result OUT is output to the rate multi 26. FIG. 8 shows a characteristic example of the rate multi 26. The input n to the rate multi 26 is set on the horizontal axis. When n is positive, the output frequency fb increases, and when n is negative, the output frequency fb decreases. The output frequency F0 (free-running frequency) when the output to the rate multi 26 is zero is a frequency corresponding to the rated frequency of the bypass AC input voltage.

  As a result, when the phase difference is the advance of the bypass AC input voltage, the input of the rate multi 26 is adjusted in the positive direction. As a result, fb is increased, the interrupt cycle is shortened, and the phase counter of the program is counted up quickly. Accordingly, the phase counter of the program and the phase of the bypass input voltage are consistent with each other.

  In this way, the interrupt program is started at the timing of multiplying the output frequency of the variable frequency circuit, the phase difference between the phase counter in the program and the bypass AC input voltage is obtained by calculation with software, and the rate is calculated from this phase difference. The output to the multi 26 is calculated and the interrupt cycle is made variable.

JP 11-89217 A

However, when Δθ is detected at an arbitrary time, it cannot be determined whether the phase difference is seen as Δθ ₁ advance (Δθ ₁ > 0) or Δθ ₂ delay (Δθ ₂ <0). For example, when the internal reference frequency is fo and the frequency of VB is fvb (fo ≠ fvo), the vector locus of VB in FIG. ).
When the vector shown in FIG. 9 is obtained, ΔV is detected so as to increase the internal reference frequency when VB rotates in the advance direction, and the internal reference frequency when VB rotates in the delay direction. Stable synchronization performance can be obtained by detecting Δθ so as to decrease.

  For this reason, in the conventional technique, it is determined when VB crosses quadrants I → IV and IV → I to determine in which direction the VB is rotating, the flag, the quadrant at the previous processing, and the current processing. Processing STEP 53 (FIG. 6) for determining Δθ is provided depending on the quadrant of the time.

  FIG. 10 shows the input-output characteristics of the prior art. For example, when a PLL (phase-locked loop) is started in the state of quadrant I and the flag setting is delayed, a -LIMIT value is output as the phase difference even though the actual phase difference is Δθ. The internal reference frequency is controlled to decrease. As the vector of VB, the transition from quadrant I → II → III → IV is made, and when quadrant IV → I, Δθ is output as the phase difference when the flag is set to advance, and stable synchronous control Become. Since the conventional method is configured as described above, if the flag is set incorrectly at the start of the PLL, the correct phase difference cannot be detected unless the quadrants I → IV and IV → I are straddled. In the worst case, it is necessary to rotate 360 °, and there is a problem that it takes extra time to reach the synchronized state.

  The present invention has been made to solve the above-mentioned problems, can shorten the synchronization time, and quickly change the output voltage phase of an AC output power converter such as an inverter to the voltage phase of another AC power supply. It is an object to obtain a synchronization control method or a synchronization control device that can be synchronized.

  A synchronization control method or synchronization control device according to the present invention includes an oscillator, a processor, a variable frequency circuit that can vary an oscillation frequency of the oscillator in response to a command from the processor, and a frequency output of the variable frequency circuit. A frequency detector, a voltage detector that detects a voltage of a three-phase AC power supply, and an AC output power converter that generates AC output power based on phase information of the divider, the AC output power converter A synchronous control method or a synchronous control device that synchronizes an output voltage phase with a voltage phase of another AC power source, and is output from the voltage detector on the processor for each frequency division ratio set by the frequency divider. The three-phase alternating current signal of the other alternating current power source is taken into the processor, the three-phase alternating current signal is converted into a vector on rotational coordinates, and the reference of the vector and the rotational coordinates Is obtained by calculation at the timing of multiplying the output frequency of the variable frequency circuit, the obtained phase difference signal is output from the processor to the variable frequency circuit, and the output frequency of the variable frequency circuit is divided. Synchronizing the three-phase AC signal and the divider output by varying the frequency divider output, and synchronizing the output voltage phase of the AC output power converter with the voltage phase of the other AC power supply In the control method or the synchronous control device, with respect to the phase difference between the vector and the reference axis of the rotation coordinate, the reference position of the rotation coordinate is set with respect to the position of the vector on the rotation coordinate at the time of the previous program execution of the processor. When the position of the current vector on the rotational coordinates exceeds the direction of delay or the direction of advance, when the phase difference is determined to be delay or advance, Is a reference position that is adapted to a plurality of locations set on the rotating coordinates.

  According to the synchronization control method or the synchronization control device of the present invention, the synchronization time can be shortened, and the output voltage phase of the AC output power converter such as an inverter can be quickly synchronized with the voltage phase of another AC power source. A control method or a synchronous control device can be obtained.

Embodiment 1 FIG.
In the first embodiment, the configuration and operation of FIGS. 4 to 8 described in the background art are the same, and the description thereof is used to mainly describe quadrant determination of VB vectors that are different portions. FIG. 1 is a flowchart of a processor program showing a processing procedure according to the first embodiment of the present invention. FIG. 2 is a diagram showing quadrant division according to the first embodiment, in which the entire quadrant area is divided into eight and Δθ is limited by ± π. FIG. 3 is a diagram showing the conditions shown in the flowchart of FIG.

  In FIG. 9 in which the bypass AC input voltage is vector-displayed on the dq axis, when the bypass AC input voltage vector is in the quadrant II, the phase difference is determined as “advance of dθ1”. This is “frequency of bypass AC input”. And “the operation frequency of the phase counter in the current program” are correct, but when these frequencies are different, it is not correctly known whether “dθ1 advance” or “dθ2 delay”. When the advance / delay is erroneously detected, the feedback control system operates so as to increase the phase difference, so that synchronous control cannot be performed.

  Therefore, in the first embodiment, even if the frequency of the bypass AC input fluctuates from the past behavior of the VB vector, it is carried out in STEP 53 in order to quickly and correctly determine the advance / delay of the phase difference. FIG. 1 is a program flowchart showing in detail the processing of STEP 53 in FIG. 6. Each processing will be described below.

  In STEP 53-1, the quadrant [(1) to (8)] of the VB vector is determined. In STEP 53-2, the processing flow is divided depending on whether the “phase difference flag” stored in the memory 22 is “advance” or “delay”.

  In the case of “phase difference flag = advance”, the current (current) VB vector VBarea and the previous VB vector VBaraOLD are compared in STEP 53-3, and in any of the conditions 1 in FIG. The VB vector is determined to be delayed, and the “phase difference flag” is set to “delayed” in STEP 53-4. As the phase difference dθ, the value obtained in STEP 50 is used as it is.

  If the condition of STEP53-3 is not satisfied, in STEP53-5, if the current VB vector VBarea satisfies the condition 2 of FIG. 3, the phase difference dθ obtained in STEP50 is used as it is. In other cases, the phase difference dθ is handled as the limiter upper limit value + LIMT (example: π / 2 advance) in STEP 53-6.

  In the case of “phase difference flag = delayed”, the current (current) VB vector VBarea and the previous VB vector VBaraOLD are compared in STEP 53-7, and in any of the condition 3 in FIG. 3 (the VB vector is counterclockwise) Rotation), the VB vector is determined to be advanced, and the “phase difference flag” is set to “advance” in STEP 53-8. As the phase difference dθ, the value obtained in STEP 50 is used as it is.

  If the condition of STEP53-7 is not satisfied, in STEP53-9, if the current VB vector VBarea satisfies the condition 4 of FIG. 3, the phase difference dθ obtained in STEP50 is used as it is. In other cases, the phase difference dθ is treated as the limiter lower limit value−LIMT (eg, π / 2 delay) in STEP 53-10.

  In STEP 53-11, the current VB vector quadrant [(1) to (8)] is stored and used as the “previous VB vector quadrant” in the next interrupt process.

  Thus, for example, when the PLL control is started with the VB vector in the quadrant (1) and the phase flag is erroneously set to be delayed, -LIMIT is output as the phase difference in the same manner as the conventional technique, When the control is performed in the direction of lowering the internal reference frequency, the VB vector changes from quadrant (1) to (2). However, the flag is set to advance according to condition 3, and Δθ is output as the phase difference. At this time, it is possible to correct the flag setting error, and normal flag setting is possible without rotating the VB vector by 360 ° as in the prior art, and the time for the synchronization state can be shortened.

  Therefore, with respect to the phase difference between the vector and the reference axis of the rotation coordinate, the reference position (boundary between adjacent quadrants) of the rotation coordinate is set to the current ( When the position of the vector on the rotational coordinate of the current time exceeds the direction of delay or advance, when determining that the phase difference is delayed or advance, multiple reference positions of the rotational coordinate are set on the rotational coordinate. As a result, normal flag setting is possible, and the time required for synchronization can be shortened. Therefore, it is possible to obtain a synchronous control method or a synchronous control device that can quickly synchronize the output voltage phase of an AC output power converter such as an inverter with the voltage phase of another AC power supply.

Even in the first embodiment, it is possible to process with a case statement in the C language.
Although a plurality of quadrants can be set as described above, the maximum value of the interrupt frequency fc determined by the phase difference θ and the gain of the PI controller and the control amount Δθ of the phase difference per processing time. Set to within. As a result, the VB vector does not transition beyond the set quadrant (for example, the transition from the quadrant (1) to the quadrant (3)), and the switching of the flag setting becomes stable. As a result, stable synchronous control is achieved. realizable.

  As described above, the interval between the reference positions of the rotation coordinates set at a plurality of positions on the rotation coordinates is determined by the division ratio set by the frequency divider and the amplification gain of the phase difference between the vector and the reference axis of the rotation coordinates. By setting it larger than the phase difference, stable synchronization control can be realized as a result.

It is a flowchart of the program of the processor which shows the process sequence of Embodiment 1 of this invention. 4 is a diagram showing quadrant division according to Embodiment 1. FIG. It is a figure which shows each condition shown with the flowchart of FIG. It is a block diagram which shows a synchronous control apparatus. It is a figure which shows the example of a timing in a synchronous control apparatus. It is a figure which shows the program flowchart performed with CPU. It is the figure which carried out the vector display of the bypass alternating current input voltage on the dq axis. It is a figure which shows the example of a characteristic of rate multi. It is a vector diagram explaining phase difference correction. It is a figure which shows an input-output characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 AC power supply for bypass circuits 2 AC input power supply 3 Uninterruptible power supply 4 Load 11 Rectifier 12 Storage battery 13 Inverter 14,15 Switch 16 Voltage sensor 17 Synchronous control device 21 CPU (microprocessor) 22 Memory 23 Analog / digital conversion circuit 24 Pulse width modulation (PWM) circuit 25 Oscillator 26 Variable frequency circuit (Rate multi)
27 Divider (Counter)

Claims (3)

An oscillator, a processor, a variable frequency circuit capable of changing the oscillation frequency of the oscillator according to a command from the processor, a frequency divider that divides the output frequency of the variable frequency circuit, and a voltage of a three-phase AC power source are detected And an AC output power converter that generates AC output power based on phase information of the frequency divider, and synchronizes the output voltage phase of the AC output power converter with the voltage phase of another AC power supply. A synchronization control method,
For each division ratio set by the frequency divider, on the processor, the three-phase AC signal of the other AC power source output from the voltage detector is taken into the processor, and the three-phase AC signal is rotated into coordinates. Convert to the above vector
The phase difference between the vector and the reference axis of the rotating coordinate is obtained by calculation at the timing of multiplication of the output frequency of the variable frequency circuit,
The obtained phase difference signal is output from the processor to the variable frequency circuit, and a frequency divider output obtained by dividing the output frequency of the variable frequency circuit is varied, whereby the three-phase AC signal and the frequency divider output are In the synchronous control method of synchronizing the output voltage phase of the AC output power converter with the voltage phase of the other AC power supply,
About the phase difference between the vector and the reference axis of the rotation coordinate,
When the reference position of the rotational coordinate exceeds the position on the rotational coordinate of the vector at the time of the previous program execution of the processor in the direction in which the position of the current vector on the rotational coordinate is delayed or advanced, A synchronous control method in which when the phase difference is determined to be delayed or advanced, a plurality of reference positions of the rotational coordinates are set on the rotational coordinates. The interval between the reference positions of the rotation coordinates set at a plurality of locations on the rotation coordinates is as follows.
The synchronous control method according to claim 1, wherein the synchronous control method is set to be larger than a phase difference determined by a frequency division ratio set by the frequency divider and an amplification gain of a phase difference between the vector and a reference axis of the rotation coordinate. An oscillator, a processor, a variable frequency circuit capable of changing the oscillation frequency of the oscillator according to a command from the processor, a frequency divider that divides the output frequency of the variable frequency circuit, and a voltage of a three-phase AC power source are detected And an AC output power converter that generates AC output power based on phase information of the frequency divider, and synchronizes the output voltage phase of the AC output power converter with the voltage phase of another AC power supply. A synchronous control device,
For each division ratio set by the frequency divider, on the processor, the three-phase AC signal of the other AC power source output from the voltage detector is taken into the processor, and the three-phase AC signal is rotated into coordinates. Convert to the above vector
The phase difference between the vector and the reference axis of the rotating coordinate is obtained by calculation at the timing of multiplication of the output frequency of the variable frequency circuit,
The obtained phase difference signal is output from the processor to the variable frequency circuit, and a frequency divider output obtained by dividing the output frequency of the variable frequency circuit is varied, whereby the three-phase AC signal and the frequency divider output are In the synchronous control device for synchronizing the output voltage phase of the AC output power converter with the voltage phase of the other AC power supply,
About the phase difference between the vector and the reference axis of the rotation coordinate,
When the reference position of the rotational coordinate exceeds the position on the rotational coordinate of the vector at the time of the previous program execution of the processor in the direction in which the position of the current vector on the rotational coordinate is delayed or advanced, A synchronous control device configured to set a plurality of reference positions of the rotation coordinates on the rotation coordinates when determining that the phase difference is delayed or advanced.

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