JP4778014B2 - Duty detection circuit and CDR circuit - Google Patents

Description

  The present invention relates to a duty detection circuit that detects the duty of input data, and a CDR circuit that corrects the duty of input data using the duty detection circuit and identifies data.

  FIG. 16 shows a conventional duty detection circuit (see, for example, Patent Document 1). As shown in FIG. 16, the conventional duty detection circuit includes a driver 400 that receives input data Din, and a low-pass filter (LPF) 500 including a resistor Rf and a capacitor Cf.

  In order to explain the operation of the duty detection circuit, FIGS. 17A and 17B are waveform diagrams in the case where a crossing pattern such as a clock is input as the input data Din. The input data Din is a signal string in which “H” and “L” repeatedly appear as “H”, “L”, “H”, “L”, and “H” that is one bit of the input data Din is When the duty is 100%, the high level continues for the time Tsec of 1 UI (unit interval), and “L” continues the low level for the time Tsec of 1 UI. The input data Din is input N bits from the starting point.

  Driver 400 charges capacitor Cf with current I when input data Din is “H”, and discharges capacitor Cf with current I when input data Din is “L”. When the duty of the input data Din is 100%, the time when the output of the driver 400 becomes “H” is equal to the time when it becomes “L”, so the operation of the driver 400 charging / discharging the capacitor Cf is balanced, The potential of the output Out of the duty detection circuit remains constant at Vo.

Next, consider a case where the duty of “H” of the input data Din is reduced by δ with respect to 1 UI. At this time, the duty of “L” of the input data Din increases by δ with respect to 1 UI. The time for the charge / discharge current I of the capacitor Cf is T · (1 ± δ). In addition, because of the crossing pattern, if the number of “H” bits and the number of “L” bits in the input N bits are equal to N / 2, the potential difference ΔV1 from the potential Vo of the output Out is as follows. expressed.
ΔV1 = {(1−δ) · T · I · N / 2− (1 + δ) · T · I · N / 2
-(T.I.N / 2-T.I.N / 2)}. (1 / C)
= -Δ · I · T · (1 / C) · N (1)
Thus, according to the conventional technique, in the crossing pattern, the potential difference ΔV1 proportional to the difference δ from 100% of the duty and proportional to the number of input bits N appears in the output Out as the duty detection result.
Japanese Patent Laid-Open No. 11-243327

  FIGS. 17C and 17D are waveform diagrams showing that the duty cannot be accurately detected when input data Din that is not a crossing pattern is input to the conventional duty detection circuit shown in FIG. It is. The input data Din includes a series of “H” bits and a series of “L” bits, but when viewed in a sufficiently long time, the signal sequence in which the number of bits of the “H” bits matches the number of bits of the “L” bits. Assuming

Here, a case where the duty of “H” of the input data Din is decreased by δ with respect to 1 UI is considered. At this time, the duty of “L” of the input data Din increases by δ with respect to 1 UI. Since δ is visible only when the input data Din has a transition from “H” to “L” or “L” to “H”, the transition probability η of the input data Din is expressed in Equation (1). When introduced, the potential difference ΔV1 ′ from the potential Vo of the output Out is expressed as follows.
ΔV1 ′ = η {(1-δ) · T · I · N / 2− (1 + δ) · T · I · N / 2
-(T.I.N / 2-T.I.N / 2)}. (1 / C)
= -Η · δ · I · T · (1 / C) · N (2)

Here, attention is paid to the case where “L” bits appearing in succession of n bits appear in the input data Din. In this case, the potential difference ΔV2 applied to the potential difference ΔV1 ′ from the potential Vo of the output Out is expressed by replacing δ by 1, η by 1, and N by n in the equation (2).
ΔV2 = −I · T · (1 / C) · n (3)

  That is, when “L” bits that are n consecutive bits appear in the input data Din, the proportionality coefficient (η · δ · N) representing the difference from 100% of the duty is (n + η · δ · N), Considering that (η · δ) takes a value of about 0.5 × 0.1 = 0.05, the coefficient (η · δ · N) representing the difference in duty depends on the pattern of the input data Din. In order to display a value sufficiently larger than the coefficient n, it is necessary to detect a bit number N that is about 200 times the number of consecutive bits n.

  Therefore, in the conventional duty detection circuit, in order to detect the duty of the input data Din other than the crossing pattern, it is necessary to receive a large number of bits, and it takes a long time to obtain a correct detection value. The potential of the output Out greatly fluctuates as shown in the equation (3) due to the influence of the pattern of the input data Din, so that the detection accuracy cannot be increased.

  The above problems also occur in a CDR (Clock Data Recovery) circuit using a duty detection circuit. The CDR circuit reproduces a clock from input data and identifies the input data based on the clock. However, if the duty of the input data deviates greatly from 100%, a normal identification operation cannot be performed. Therefore, the CDR circuit uses a duty detection circuit and a data duty correction circuit to correct the duty of input data and perform data identification. Therefore, the above problem also occurs in the CDR circuit using the duty detection circuit.

The present invention has been made to solve the above-described problem, and provides a duty detection circuit capable of detecting a duty with high speed and high accuracy even when input data is other than a crossing pattern. Objective.
It is another object of the present invention to provide a CDR circuit capable of performing data identification by correcting the duty of input data with high speed and high accuracy.

  The duty detection circuit according to the present invention receives the input data and a clock having a frequency and phase synchronized with the input data, and a first pulse signal and a reference pulse whose pulse width increases or decreases in accordance with a change in the duty of the input data. A pulse signal generation circuit that outputs a second pulse signal indicating a width; a selector that selectively outputs either the first pulse signal or the second pulse signal; and A pulse signal transition determination circuit that causes the selector to select the second pulse signal when there is no transition, and causes the selector to select the first pulse signal when there is a transition of the second pulse signal; The difference between the average voltage level of the signal output from the selector and the average voltage level of the second pulse signal is calculated from the duty of 100% of the input data. It is characterized in that an output circuit that outputs a detection signal indicative of the dynamic content.

Further, in one configuration example of the duty detection circuit of the present invention, the pulse signal generation circuit includes a D-type flip-flop that latches the input data in synchronization with the clock and outputs the second pulse signal, The input data is output as the first pulse signal.
In one configuration example of the duty detection circuit of the present invention, the pulse signal transition determination circuit includes a first gating circuit that detects a rising edge of the second pulse signal, and an output of the first gating circuit. A first counter that outputs a significant signal when the clock is counted for the first predetermined number of times and a second gate that detects the rising of the output signal of the first counter. A second signal that outputs a significant signal when the output signal of the first gating circuit is counted as a reset input and the output signal of the first gating circuit is continuously counted for a second predetermined number of times. And when the significant signal is output from the second counter, the selector selects the first pulse signal and the second gating When the reset signal from the road is output and is characterized in that it consists of an SR-type full flip-flops for selecting the second pulse signal to the selector.
In one configuration example of the duty detection circuit according to the present invention, the output circuit includes a first current source to which a first power supply potential is applied at one end and a second current to which a second power supply potential is applied to one end. A first switch that is provided between a power source, the other end of the first current source, and a detection signal output terminal and that uses the input data as a control input; the other end of the second current source; and the detection A second switch provided between the signal output terminal and the pulse signal as a control input; and a capacitor provided between the detection signal output terminal and the second power supply potential. It is what.

Further, the CDR circuit of the present invention includes a duty detection circuit and a data duty for outputting correction data obtained by correcting the duty of the input data to be identified according to the level of the detection signal output from the duty detection circuit. A correction circuit; a clock recovery circuit that generates a recovery clock synchronized with an edge timing of the correction data; and a data identification circuit that performs data identification of the correction data based on the recovery clock, wherein the duty detection circuit includes the correction circuit The data and the reproduction clock are input, and a detection signal indicating a variation of the correction data from a duty of 100% is output as a signal indicating a duty correction amount.
Further, in one configuration example of the CDR circuit of the present invention, the clock recovery circuit generates a gating circuit that detects an edge of the correction data and the recovered clock that is phase-synchronized with the edge detected by the gating circuit. And a gated VCO.
In one configuration example of the CDR circuit of the present invention, the data duty correction circuit includes a delay circuit that extends both or one of the rising time and the falling time of the input data, and outputs the delay circuit from the delay circuit. It is characterized by comprising a threshold circuit that outputs a threshold value determined by a detection signal.

  According to the duty detection circuit of the present invention, since it is difficult to be affected by the same sign continuity of input data, it is possible to detect a duty several hundred times faster than the prior art with the same accuracy as the conventional duty detection circuit. In addition, the duty detection can be performed with extremely high accuracy in the same detection time as that of the conventional duty detection circuit. Further, according to the present invention, it is possible to detect the duty with high speed and high accuracy with a simple circuit configuration. Furthermore, in the present invention, by providing a selector and a pulse signal transition determination circuit, when the duty of the input data is extremely small or extremely large, the potential of the detection signal gradually varies and the duty variation is not reflected. The problem of becoming a value can be avoided.

  Further, according to the CDR circuit of the present invention, high-speed and high-precision duty correction can be performed without being affected by the same sign continuity of input data, and the duty of the input data greatly deviates from 100%. However, a normal identification operation is possible.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the duty detection circuit according to the first embodiment of the present invention.
The duty detection circuit according to the present embodiment receives an input data Din and a clock signal CK having a frequency and phase synchronized with the input data Din, and a pulse signal Err whose pulse width increases or decreases in accordance with a change in duty of the input data Din A pulse signal generation circuit 1 that outputs a pulse signal Ref indicating a reference pulse width (1 UI), a selector 2 that selectively outputs either the pulse signal Err or the pulse signal Ref, and a transition of the pulse signal Ref are determined. When there is no transition of the pulse signal Ref, the selector 2 selects the pulse signal Ref, and when there is the transition of the pulse signal Ref, the selector 2 selects the pulse signal transition determination circuit 3 that selects the pulse signal Err. The average voltage level of the output pulse signal Selo and the average voltage level of the pulse signal Ref The difference, and an output circuit 4 that outputs a detection signal Out indicating the variation from a duty of 100% of the input data Din.

  2 is a block diagram showing an example of the configuration of the pulse signal generation circuit 1, and FIGS. 3A to 3C are waveform diagrams showing the operation of the pulse signal generation circuit 1 of FIG. In FIG. 3A, δ is the duty fluctuation amount from 100% of the input data Din. In other words, the pulse width of the input data Din increases or decreases by the duty variation δ.

  The pulse signal generation circuit 1 includes a D-type flip-flop (hereinafter referred to as D-FF) 10. The D-FF 10 receives the input data Din and the clock CK synchronized in frequency and phase with the input data Din, latches the input data Din in synchronization with the falling edge of the clock CK, and sets the reference pulse width (1 UI). The pulse signal Ref shown is output (FIG. 3C). Further, as described above, the pulse width of the input data Din is increased or decreased by the duty variation δ. Therefore, in the present embodiment, the input data Din is output as it is as the pulse signal Err.

  4 is a block diagram showing an example of the configuration of the pulse signal transition determination circuit 3, and FIGS. 5A to 5F are waveform diagrams showing the operation of the pulse signal transition determination circuit 3. FIG. The pulse signal transition determination circuit 3 includes a gating circuit 30, an 8-bit counter 31, a gating circuit 32, a 4-bit counter 33, and an SR type flip-flop (hereinafter referred to as SR-FF) 34. The

5 (A) and 5 (B) show an operation in which the selector 2 is switched at the input head of burst data, and FIGS. 5 (C) to 5 (F) show a standby state when data input is completed and there is no signal. The operation to return to is shown.
The gating circuit 30 detects the rising edge of the pulse signal Ref output from the pulse signal generation circuit 1. That is, the gating circuit 30 outputs a signal Ref ′ that rises when the pulse signal Ref rises from “L” to “H” and falls after a predetermined time (for example, UI / 2).

  The 8-bit counter 31 counts the clock CK, and outputs “H” from the output terminal MSB when the clock CK is counted 256 times continuously. The 8-bit counter 31 is reset when the output signal Ref ′ of the gating circuit 30 becomes “H”, and outputs “L” from the output terminal MSB.

  The gating circuit 32 detects the rising edge of the output signal of the 8-bit counter 31. That is, the gating circuit 32 outputs a signal that rises when the output signal of the 8-bit counter 31 rises from “L” to “H” and falls after a predetermined time (for example, UI / 2).

  The 4-bit counter 33 counts the output signal Ref ′ of the gating circuit 30 and outputs “H” from the output terminal MSB when the output signal Ref ′ is counted 16 times continuously. The 4-bit counter 33 is reset when the output signal Rst of the gating circuit 32 becomes “H”, and outputs “L” from the output terminal MSB.

  The SR-FF 34 is set when the output signal of the 4-bit counter 33 becomes “H”, and sets the selector switching signal Selc to “H”. The SR-FF 34 is reset when the output signal Rst of the gating circuit 32 becomes “H”, and the selector switching signal Selc is set to “L”.

  First, when the input data Din is input, the selector switching signal Selc is “L” as shown in FIG. In response to the selector switching signal Selc, the selector 2 selects the pulse signal Ref output from the pulse signal generation circuit 1 and outputs it as the signal Selo.

  Subsequently, when the input data Din is continuously input, the 4-bit counter 33 counts the output signal Ref ′ (FIG. 5A) of the gating circuit 30 and continuously counts 16 times. To output “H” from the output terminal MSB. As a result, the SR-FF 34 sets the selector switching signal Selc to “H” as shown in FIG. In response to the selector switching signal Selc, the selector 2 selects the pulse signal Err output from the pulse signal generation circuit 1 and outputs it as the signal Selo.

Next, when the input of the input data Din is completed and no signal is generated, the pulse signal Ref output from the pulse signal generation circuit 1 is constant at “L”, and the output signal Ref ′ (see FIG. 5 (C)) is also constant at “L”.
Therefore, since the signal input to the reset terminal of the 8-bit counter 31 remains “L”, the 8-bit counter 31 counts the clock CK and continues the clock CK 256 times as shown in FIG. At the time of counting, “H” is output from the output terminal MSB.

The gating circuit 32 detects the rising edge of the output signal of the 8-bit counter 31 and outputs the reset signal Rst (FIG. 5E).
Since the reset signal Rst has become “H”, the SR-FF 34 sets the selector switching signal Selc to “L” (FIG. 5F). In response to the selector switching signal Selc, the selector 2 selects the pulse signal Ref output from the pulse signal generation circuit 1 and outputs it as the signal Selo.

  When the duty of the input data Din is extremely small, for example, 25% or less, the pulse signal Ref output from the pulse signal generation circuit 1 is constant at “L”. Therefore, when the duty is extremely small, the operation is the same as that shown in FIGS.

  When the duty of the input data Din is extremely large, for example, 125% or more, the pulse signal Ref becomes “H” and constant. On the other hand, since the gating circuit 30 detects the rising edge of the pulse signal Ref, when the pulse signal Ref is “H” and constant, the output signal Ref ′ of the gating circuit 30 becomes “L” and constant. Therefore, even when the duty is extremely large, the operation is the same as in FIGS.

  FIG. 6 is a block diagram showing an example of the configuration of the output circuit 4, and FIGS. 7A and 7B are waveform diagrams showing the operation of the output circuit 4. The output circuit 4 includes a current source 40 to which a power supply voltage + V (first power supply potential) is applied at one end, a current source 41 to which a ground potential (second power supply potential) is applied to one end, and the other end of the current source 40. Between the switch 42 that receives the output signal Selo of the selector 2 as a control input, and the other end of the current source 41 and the detection signal output terminal of the duty detection circuit. The switch 43 is provided with the pulse signal Ref as a control input, and the capacitor 44 is provided between the detection signal output terminal and the ground.

The examples of FIGS. 7A and 7B show a case where the duty of “H” of the input data Din is smaller by δ than 100%.
The current source 40 charges the capacitor 44 when the switch 42 is on. The current source 41 discharges the capacitor 44 when the switch 43 is on. The switch 42 is turned on only when the output signal Selo of the selector 2 is “H”. The switch 43 is turned on only when the pulse signal Ref is “H”.

  When the duty of the input data Din is 100%, the selector 2 selects the pulse signal Err output from the pulse signal generation circuit 1 by the operation described with reference to FIGS. Output as Selo. Therefore, when the duty of the input data Din is 100%, the time when the output signal Selo of the selector 2 is “H” and the time when the pulse signal Ref is “H” are equal, that is, the switch 42 is in the ON state. Since the time and the time during which the switch 43 is on are equalized, the charging operation and the discharging operation of the capacitor 44 are balanced, and the potential of the detection signal Out, which is the output of the duty detection circuit, remains constant at the center potential Vo. .

On the other hand, even when input data Din as shown in FIG. 7A is input, the selector 2 selects the pulse signal Err and outputs it as the signal Selo. However, since the pulse width of the output signal Selo of the selector 2 is narrower by the duty variation δ than the pulse signal Ref, the time for charging the capacitor 44 compared to the time for discharging the capacitor 44 is δ · T (T is 1 UI), and the potential of the detection signal Out output from the duty detection circuit decreases from Vo by the following ΔV.
ΔV = −η · δ · T · I · (1 / C) · N (4)

  In Equation (4), η is the transition probability of the input data Din, which is 0.5 for the random pattern and 1.0 for the crossing pattern. I is the charge / discharge current of the capacitor 44, C is the capacity of the capacitor 44, and N is the number of input bits. Expression (4) is the same as the above expression (2), and in the present embodiment as well, it is shown that the potential difference ΔV is represented by the duty variation δ from 100% of the input data Din as in the conventional case. ing.

  Even when the duty of “H” of the input data Din is increased by δ with respect to 100%, the selector 2 selects the pulse signal Err and outputs it as the signal Selo. However, since the output signal Selo of the selector 2 is wider in pulse width by the duty variation δ than the pulse signal Ref, the time for charging the capacitor 44 is longer by δ · T than the time for discharging the capacitor 44. Contrary to the case of FIG. 7B, the potential of the detection signal Out output from the duty detection circuit rises above Vo. The potential difference from Vo at this time is a value obtained by setting the potential difference ΔV shown in Expression (4) to a positive sign.

  The difference between the present embodiment and the conventional duty detection circuit shown in FIG. 16 is that when the input data Din continues with the same sign, the switches 42 and 43 remain off or remain on, 44 is that the charging operation and the discharging operation are balanced, and the potential of the output signal Out of the duty detection circuit is maintained. That is, when “L” of the input data Din continues for n bits as shown in FIG. 7A, both the input data Din and the pulse signal Ref remain “L”, and the switches 42 and 43 are turned off. If the input data Din continues to be “H”, both the input data Din and the pulse signal Ref remain “H”, and the switches 42 and 43 remain on.

  Therefore, the potential difference ΔV2 expressed by the equation (3) as seen in the conventional duty detection circuit does not occur at all and does not affect the potential difference ΔV. There is no need to set the length to thousands of unit bits. The capacity of the capacitor 44 may be set to such an extent that a change in potential during one charge / discharge does not affect ΔV (or the accuracy of duty correction). As a result, the time constant of the change in ΔV can be increased to about one tenth of the conventional duty detection circuit, and the duty can be detected several tens of times faster than the conventional one. Thus, in the present embodiment, the duty fluctuation δ from 100% of the input data Din can be accurately detected from data with a small number of bits, and high-speed and highly accurate duty detection can be performed.

  Further, the inventor has proposed a duty detection circuit using a circuit as shown in FIG. 8 instead of the D-FF 10 in FIG. 2 (Japanese Patent Application No. 2007-075749). In the pulse signal generation circuit 1 of FIG. 8, 11 and 12 are D-FFs, 13 and 15 are exclusive OR circuits, and 14 and 16 are AND circuits.

However, since the pulse signal generation circuit 1 shown in FIG. 8 uses an exclusive OR circuit or an AND circuit having a narrow transmission frequency band, there is a problem that an error occurs during high-speed operation.
On the other hand, when the D-FF 10 of FIG. 2 is used as the pulse signal generation circuit 1, such an error does not occur, and the duty can be normally detected even for high-speed input data Din. . Further, since the same function as that of the circuit of FIG. 8 can be realized by one FF, the circuit scale can be reduced.

The operation of the output circuit 4 is when the duty fluctuation δ of the input data Din is 0 or a value that is generally assumed, and the duty of the input data Din is extremely small or extremely large. In this case, the operation is as follows.
As described above, when the duty of the input data Din is extremely small or extremely large, the operation is performed as shown in FIGS. 5C to 5F, and the selector 2 is output from the pulse signal generation circuit 1. The pulse signal Ref is selected and output as a signal Selo.

  When the duty of the input data Din is extremely small, the pulse signal Ref output from the pulse signal generation circuit 1 is constant at “L”, and the switches 42 and 43 of the output circuit 4 are turned off. Therefore, the charging operation and discharging operation of the capacitor 44 of the output circuit 4 are both stopped, and the potential of the detection signal Out, which is the output of the duty detection circuit, is the value immediately before the selection of the selector 2 is switched from the pulse signal Err to Ref. Maintained.

  On the other hand, when the duty of the input data Din is extremely large, the pulse signal Ref output from the pulse signal generation circuit 1 is constant at “H”, and the switches 42 and 43 of the output circuit 4 are turned on. Therefore, the charging operation and discharging operation of the capacitor 44 are balanced, and the potential of the detection signal Out is maintained at a value immediately before the selection of the selector 2 is switched from the pulse signal Err to Ref.

  When the pulse signal generation circuit 1 and the output circuit 4 are directly connected without providing the selector 2 and the pulse signal transition determination circuit 3 of the present embodiment and the pulse signal Err is used as the control input of the switch 42, the input data Din When the duty cycle of the output circuit 4 is extremely small, the pulse signal Ref is constant at “L”, and the discharging operation of the capacitor 44 of the output circuit 4 is stopped. On the other hand, since the switch 42 is turned on by the input of the pulse signal Err, the charging operation of the capacitor 44 is continued. For this reason, although the duty of the input data Din is small, the potential of the detection signal Out gradually increases, and the potential difference ΔV from the center potential Vo becomes a value that does not reflect the duty variation δ.

  On the other hand, in this embodiment, by providing the selector 2 and the pulse signal transition determination circuit 3, when the duty of the input data Din is extremely small, the selection of the selector 2 is switched from the pulse signal Err to Ref. Since the potential of the detection signal Out is maintained as it is immediately before, the problem that the potential of the detection signal Out gradually increases can be avoided.

  Similarly, when the pulse signal generation circuit 1 and the output circuit 4 are directly connected and the pulse signal Err is used as the control input of the switch 42, when the duty of the input data Din is extremely large, the pulse signal Ref is constant at “H”. As a result, the switch 43 remains on, and the discharging operation of the capacitor 44 of the output circuit 4 is continuously performed. On the other hand, the switch 42 is intermittently turned on by the input of the pulse signal Err. However, since the switch 43 remains on, the time for charging the capacitor 44 is shorter than the time for discharging the capacitor 44. For this reason, although the duty of the input data Din is large, the potential of the detection signal Out gradually decreases, and the potential difference ΔV from the center potential Vo becomes a value that does not reflect the duty variation δ.

  In contrast, in the present embodiment, when the duty of the input data Din is extremely large, the potential of the detection signal Out is maintained as it is immediately before the selection of the selector 2 is switched from the pulse signal Err to Ref. The problem that the potential of the signal Out gradually decreases can be avoided.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 9 is a block diagram showing a configuration of a CDR circuit according to the second embodiment of the present invention.
The CDR circuit includes a data duty correction circuit 100, a duty detection circuit 110, a clock recovery circuit 120, and a data identification circuit 130. As the duty detection circuit 110, the one described in the first embodiment is used.

FIG. 10 is a block diagram showing an example of the configuration of the clock recovery circuit 120 and the data identification circuit 130. The clock recovery circuit 120 includes a gating circuit 121 and a gated VCO (Voltage Controlled Oscillator) 122. The gating circuit 121 includes a buffer 123, a delay circuit 124, and a negative logical product circuit 125, and the gated VCO 122 includes inverters 126 and 127 and a negative logical product circuit 128.
The gating circuit 121 detects the rising edge of the input data Din. The gated VCO 122 generates a recovered clock CK that is phase-synchronized with the rising edge of the input data Din. The data identification circuit 130 is composed of a D-FF.

  The operation of the clock recovery circuit 120 and the data identification circuit 130 will be described with reference to FIGS. 11A to 11C show a case where the duty of the input data Din is 100%. The gating circuit 121 generates a pulse of width UI / 2 at the rising edge of the input data Din shown in FIG. 11A and inputs the pulse to the NAND circuit 128 of the gated VCO 122, thereby changing the phase of the recovered clock CK. Match the phase of the input data Din. As a result, the recovered clock CK that is phase-synchronized with the rising edge of the input data Din is output from the clock recovery circuit 120 (FIG. 11B).

  In the data identification circuit 130, the input data Din is input to the data input terminal D, and the reproduction clock CK is input to the clock input terminal C. The recovered clock CK is in phase with the input data Din. The D-FF constituting the data identification circuit 130 shapes the input data Din starting from the falling edge of the recovered clock CK and outputs the recovered output data Dout from the output terminal Q (FIG. 11C). .

FIG. 12 is a block diagram showing an example of the configuration of the data duty correction circuit 100. The data duty correction circuit 100 includes a driver 101, a capacitor 102, and a threshold circuit 103.
The input data Da is connected to the input of the driver 101, and the capacitor 102 and the input of the threshold circuit 103 are connected to the output of the driver 101. The other end of the capacitor 102 is grounded. The driver 101 and the capacitor 102 constitute a delay circuit that extends the rising time and / or the falling time of the input data Da.

  The threshold circuit 103 outputs a signal obtained by extending the rising time and / or the falling time of the input data Da with the detection signal Out being the output of the duty detection circuit 110 as a threshold, and outputs the signal. Is the correction data Din which is the output of the data duty correction circuit 100.

  Next, the operation of the data duty correction circuit 100 will be described with reference to FIGS. 13 (A) to 13 (C). By the capacitor 102 connected to the output of the driver 101 of the data duty correction circuit 100, the data Da2 that is the output of the driver 101 is data in which the rise time and the fall time of the input data Da shown in FIG. (FIG. 13B). The next-stage threshold circuit 103 sets the voltage level of the detection signal Out as the threshold value TH, and outputs the “H” level correction data Din to the output terminal when the voltage of the input data Da2 exceeds the threshold value TH. When the voltage falls below the threshold value TH, the circuit outputs the “L” level correction data Din to the output terminal (FIG. 13C).

  The voltage level of the detection signal Out at which the duty of the output data Dout becomes 100% when a signal having a duty of 100% is input as the input data Da to the data Da2 obtained by extending the rise time and fall time of the input data Da. Is set to the center potential of the detection signal Out (Vo in the first embodiment). When the detection signal Out becomes lower than the center potential Vo, the data duty correction circuit 100 outputs a signal having a duty larger than that of the input data Da as the correction data Din. When the detection signal Out becomes higher than the center potential Vo, the data duty correction circuit 100 outputs a signal having a duty smaller than that of the input data Da as the correction data Din. As described above, the data duty correction circuit 100 corrects the duty of the input data Da according to the level of the detection signal Out and outputs the corrected data Din.

  By using the detection signal Out, which is the output of the duty detection circuit 110, as the threshold value of the data duty correction circuit 100, and using the correction data Din, which is the output of the data duty correction circuit 100, as an input to the duty detection circuit 110, FIG. As shown in FIG. 14A, when the duty of the input data Da is 100%, the detection signal Out stops at the center potential Vo (FIG. 14B), and the input data Da is output as it is as the correction data Din (FIG. 14). 14 (C)). The operations of the clock recovery circuit 120 and the data identification circuit 130 are as described above, and the output data Dout is output from the data identification circuit 130 (FIG. 14E).

  On the other hand, when the duty of the input data Da is extremely smaller than 100% as shown in FIG. 15A, the detection signal Out moves to a potential lower than the center potential Vo (FIG. 15B), and the input data Da. Is increased and output as correction data Din (FIG. 15C). Therefore, even when the duty of the input data Da is smaller than 100%, the data identification circuit 130 performs a normal identification operation and outputs normal output data Dout (FIG. 15E).

  Although not particularly illustrated, when the duty of the input data Da is extremely larger than 100%, the detection signal Out is moved to a potential higher than the center potential Vo, the duty of the input data Da is reduced, and the correction data Din Is output as Therefore, even when the duty of the input data Da is greater than 100%, the data identification circuit 130 performs a normal identification operation and outputs normal output data Dout.

  Here, the time required for the data duty correction of this embodiment will be described. In the present embodiment, the average value of the input data itself is used as in a conventional amplifier circuit or the like, and a correction signal corresponding to the “H” level time and the “L” level time is used. Absent. This is because, in this conventional method, the potential fluctuation of the correction signal largely depends on the continuous bit length of the same code of the input data. That is, as the continuous bit length of the input data becomes longer, unless the averaging time is set longer, the voltage level of the correction signal largely fluctuates until the end of the continuous signal, and the duty also fluctuates greatly.

  In contrast, in the present embodiment, by using the duty detection circuit 110 described in the first embodiment, the capacitor of the duty detection circuit 110 does not depend on the continuous bit length of the same sign of the input data Da. Focusing on only the fluctuation of the average value of 44 outputs, it has a degree of freedom in design that can determine the data duty correction time. As a result, in the present embodiment, duty correction can be performed at high speed even for input data Da in which consecutive bits of the same code continue for a long time.

  The characteristics of the present embodiment are summarized as follows. First, in the present embodiment, a normal identification operation can be performed even when the duty of the input data Da is greatly deviated from 100%. That is, when the duty of the input data Da deviates from 100%, the detection signal Out indicating the duty correction amount can be obtained from the duty detection circuit 110, and input by the data duty correction circuit 100 in accordance with the detection signal Out. By performing the duty correction of the data Da, a normal identification operation can be performed. Next, in the present embodiment, the detection of the duty of the input data Da is not the average value of the “H” level and “L” level of the data, but the time position between the falling edge of the input data Da and the reproduction clock CK. Therefore, the time for completing the duty correction can be determined without depending on the continuous code length of the input data Da. As a result, in the present embodiment, duty correction can be realized at high speed even for input data Da in which consecutive bits of the same code continue for a long time.

  The present invention can be applied to a technique for detecting the duty of input data and a technique for regenerating a clock from the input data and identifying the input data based on the clock.

It is a block diagram which shows the structure of the duty detection circuit which concerns on the 1st Embodiment of this invention. It is a block diagram which shows one example of a structure of the pulse signal generation circuit of the duty detection circuit which concerns on the 1st Embodiment of this invention. It is a wave form diagram showing operation of a pulse signal generation circuit of a duty detection circuit concerning a 1st embodiment of the present invention. It is a block diagram which shows one example of a structure of the pulse signal transition determination circuit of the duty detection circuit based on the 1st Embodiment of this invention. It is a wave form diagram which shows the operation | movement of the pulse signal transition determination circuit of the duty detection circuit based on the 1st Embodiment of this invention. It is a block diagram which shows an example of a structure of the output circuit of the duty detection circuit which concerns on the 1st Embodiment of this invention. It is a wave form diagram which shows operation | movement of the output circuit of the duty detection circuit which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the other structural example of the pulse signal generation circuit of the duty detection circuit based on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows one example of the structure of the clock reproduction circuit and data identification circuit of the CDR circuit which concerns on the 2nd Embodiment of this invention. It is a wave form diagram which shows operation | movement of the clock reproduction circuit and data identification circuit of the CDR circuit which concern on the 2nd Embodiment of this invention. It is a block diagram which shows one example of a structure of the data duty correction circuit of the CDR circuit which concerns on the 2nd Embodiment of this invention. It is a wave form diagram which shows operation | movement of the data duty correction circuit of the CDR circuit which concerns on the 2nd Embodiment of this invention. It is a wave form diagram which shows operation | movement in case the duty of input data is 100% in the CDR circuit based on the 2nd Embodiment of this invention. It is a wave form diagram which shows operation | movement when the duty of input data is smaller than 100% in the CDR circuit based on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the conventional duty detection circuit. It is a wave form diagram which shows operation | movement of the conventional duty detection circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pulse signal generation circuit, 2 ... Selector, 3 ... Pulse signal transition determination circuit, 4 ... Output circuit, 100 ... Data duty correction circuit, 110 ... Duty detection circuit, 120 ... Clock reproduction circuit, 130 ... Data identification circuit

Claims (7)

A first pulse signal whose pulse width is increased or decreased according to a change in duty of the input data and a second pulse signal indicating a reference pulse width, which are input with input data and a clock whose frequency and phase are synchronized with the input data A pulse signal generation circuit that outputs
A selector that selectively outputs either the first pulse signal or the second pulse signal;
When there is no transition of the second pulse signal, the selector selects the second pulse signal, and when there is a transition of the second pulse signal, the selector selects the first pulse signal. A pulse signal transition determination circuit;
An output circuit that outputs a difference between an average voltage level of the signal output from the selector and an average voltage level of the second pulse signal as a detection signal indicating a variation from a duty of 100% of the input data. A duty detection circuit. The duty detection circuit according to claim 1,
The pulse signal generation circuit includes a D-type flip-flop that latches the input data in synchronization with the clock and outputs the second pulse signal.
A duty detection circuit that outputs the input data as the first pulse signal. The duty detection circuit according to claim 1,
The pulse signal transition determination circuit includes:
A first gating circuit for detecting a rising edge of the second pulse signal;
A first counter that outputs a significant signal when the output signal of the first gating circuit is used as a reset input and the clock is continuously counted for a first predetermined number of times;
A second gating circuit for detecting the rising edge of the output signal of the first counter;
A second counter that outputs a significant signal when the output signal of the second gating circuit is used as a reset input and the output signal of the first gating circuit is continuously counted a second predetermined number of times;
When a significant signal is output from the second counter, the selector selects the first pulse signal, and when a reset signal is output from the second gating circuit, the selector A duty detection circuit comprising an SR-type flip-flop for selecting a second pulse signal. The duty detection circuit according to claim 1,
The output circuit is
A first current source having a first power supply potential applied to one end;
A second current source to which a second power supply potential is applied at one end;
A first switch provided between the other end of the first current source and a detection signal output terminal and having the input data as a control input;
A second switch provided between the other end of the second current source and the detection signal output terminal and having the pulse signal as a control input;
A duty detection circuit comprising a capacitor provided between the detection signal output terminal and the second power supply potential. A duty detection circuit according to any one of claims 1 to 4,
A data duty correction circuit that outputs correction data obtained by correcting the duty of input data to be identified according to the level of the detection signal output from the duty detection circuit;
A clock recovery circuit for generating a recovery clock synchronized with the edge timing of the correction data;
A data identification circuit for performing data identification of the correction data by the reproduction clock,
The duty detection circuit receives the correction data and the recovered clock, and outputs a detection signal indicating a variation of the correction data from a duty of 100% as a signal indicating a duty correction amount. circuit. The CDR circuit of claim 5,
The clock recovery circuit includes:
A gating circuit for detecting an edge of the correction data;
A CDR circuit comprising: a gated VCO that generates the reproduction clock phase-synchronized with an edge detected by the gating circuit. The CDR circuit of claim 5,
The data duty correction circuit includes:
A delay circuit for extending the rise time and / or fall time of the input data;
A CDR circuit comprising: a threshold circuit that outputs the output of the delay circuit by making a threshold determination with the detection signal.

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