JP4779906B2 - LSI test system - Google Patents

Description

  The present invention relates to an LSI test system, and more particularly to speeding up a test.

  In the LSI test system, as a test for a semiconductor to be tested (hereinafter referred to as DUT), a direct current test by voltage / current value measurement, a function test by pattern running, and the like are performed. FIG. 3 is a block diagram of each test system, where (A) shows a DC test system and (B) shows a function test system. FIG. 4 is a waveform diagram of each test system, where (A) shows a DC test system and (B) shows a function test system.

  In the DC test, when the voltage output VF and the current output IF are input to the predetermined pins of the DUT 20 from the output terminal of the source / measure unit 12 controlled by the control unit 11 of the test system 10, the voltage output VF and the current output are output. Based on IF, a voltage input VS and a current input IS based on the voltage output VF and the current output IF are output from a predetermined pin of the DUT 20 to the input terminal of the source / measure unit 12. Here, if the measurement results of the voltage input VS and the current input IS in the source / measure unit 12 after a predetermined time elapses after the voltage output VF and the current output IF are applied, the control unit 11 DUT 20 determines that the product is non-defective.

  In the function test, when the pattern output PO1 and the pattern output PO2 are input from the predetermined output terminal of the pattern generation unit 13 of the test system 10 to the predetermined pin of the DUT 20 via the pin electronics unit 14, these pattern output PO1 and A pattern input PI is output from a predetermined pin of the DUT 20 to a comparator (not shown) via a predetermined input terminal of the pin electronics unit 14 based on the pattern output PO2. Here, if the pattern input PI input to the pin electronics unit 14 coincides with the expected pattern output from the pattern generation unit 13 when a predetermined time elapses after the pattern output PO1 and the pattern output PO2 are applied, the pin electronics The unit 14 determines that the DUT 20 is a non-defective product.

  FIG. 5 is a flowchart of the test execution processing in these test systems, where (A) shows a DC test system and (B) shows a function test system. In FIG. 5, along with the flow of execution processing, test program description, control processing, and time measurement are shown together.

  Focusing on the flow of control processing in the DC test, after setting parameters necessary for the DC test in various registers (step SP1), a fixed post-processing time is set (step SP2). Next, a predetermined waiting time is set (step SP3). Thereafter, measurement preparation processing is performed (step SP4), and measurement start processing is executed (step SP5). As a result, a predetermined voltage output VF and a current output IF are added from the source / measure unit 12 to the DUT 20, and the source / measure unit 12 measures the voltage input VS and the current input IS output from the DUT 20 to the source / measure unit 12. A series of DC test measurement processes are terminated (step SP6).

  Here, paying attention to the test program description of the DC test, step SP1 and step SP2 of the control process are “setting”, step SP3 is “waiting time setting”, and steps SP4 to SP6 are “voltage / current measurement”.

  Further, paying attention to the time measurement of the DC test, the control processing steps SP1 and SP2 are “set time”, step SP3 is “no processing time”, and steps SP4 to SP6 are “measurement time”.

  Focusing on the flow of control processing in the function test, after setting parameters necessary for the function test in various registers (step SP1), a fixed post-processing time is set (step SP2). Next, a predetermined waiting time is set (step SP3). Thereafter, preprocessing is performed (step SP4), pattern running preparation processing is executed (step SP5), pattern running start processing is executed (step SP6), and necessary for function tests set in various registers after a predetermined time. A series of pattern travel processing based on the parameters is terminated (step SP7).

  Here, paying attention to the test program description of the function test, steps SP1 and SP2 of the control process are “setting”, step SP3 is “waiting time setting”, and steps SP4 to SP7 are “pattern running”.

  Further, paying attention to the time measurement of the function test, step SP1 and step SP2 of the control processing are “set time”, step SP3 is “no processing time”, and steps SP4 to SP7 are “pattern running time”.

  FIG. 6 is a timing chart example corresponding to the function test flowchart of FIG. Assuming that various register settings are executed at time t2, the soft processing time starts from time t1 preceding time t2 and ends at time t3 when the post-processing time Te corresponding to the settling time elapses. The preprocessing time Ts up to the time t4 following the postprocessing time Te is a non-processing time with respect to the soft processing time. The pattern travel preparation time Tp is from time t4 to time t5 when the predetermined pattern travel starts.

JP 2001-296333 A

By the way, the waiting time that the user of the test system 10 wants to set by the test program description is the time from when the specified electrical condition is met until immediately before the start of the test.
DC test wait time setting value =
DUT20 specification wait time-(post-processing time Te + measurement preparation time Tm)
Function test wait time setting value =
DUT20 specification waiting time-(post-processing time Te + pre-processing time Ts + preparation time Tp)

  However, the “waiting time setting” in the test program description of FIG. 5 is a value determined by the electrical specifications of the DUT 20. That is, the time required for “pre-processing”, “post-processing”, “measurement preparation”, and “pattern travel preparation” in the control processing of FIG. 5 is a waste time other than the waiting time that the user wants to set. This increases the execution time of the test program for testing, and is one of the factors that hinder productivity improvement.

  The present invention pays attention to such a conventional problem, and the purpose thereof is to optimize the “waiting time setting” in the test program description to improve the productivity by shortening the test program program execution time. The object is to provide an LSI test system.

The invention of claim 1 which achieves such a problem,
In an LSI test system configured to execute a predetermined test after parameters required for the test of a test target semiconductor are set in various registers and electrical conditions specified for the test target semiconductor are prepared,
In setting the time from when the specified electrical condition is met to immediately before the start of a predetermined test as a waiting time by the test program description,
A time measuring unit for measuring the post-processing time Te and the measurement preparation time Tm in the DC test and the post-processing time Te, the pre-processing time Ts and the preparation time Tp in the function test ;
Based on the measurement result of this time measurement unit , a control unit that performs the calculation of the following equation representing the time from when the specified electrical condition is met until just before the start of the test;
DC test waiting time set value = specification waiting time of the test target semiconductor− (post-processing time T e + measurement preparation time Tm)
Wait time setting value of the function test = the test semiconductor Specifications latency - (trailing processing time Te + pretreatment time Ts + preparation time Tp)
A display unit is provided to display the calculation results of this control unit as dead time from various register settings to the start of measurement ,
Based on these measured and displayed dead times, the test program program execution time is shortened by setting the optimum waiting time in the test program description of the DC test and the function test as follows .
DC test wait time setting value = specification wait time of the semiconductor to be tested-dead time
Function test wait time set value = Specification wait time of the test target semiconductor-Waste time

  As a result, it is possible to realize an LSI test system capable of optimizing the “waiting time setting” in the test program description and reducing the test program program execution time.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the main part of one embodiment of the present invention, and the same reference numerals are given to the parts common to FIG. The setting unit 15 sets and stores predetermined parameters necessary for a desired DC test or function test in various registers 16.

  The time measuring unit 17 measures the post-processing time Te and the measurement preparation time Tm in the DC test shown in FIG. 5 and the post-processing time Te, the pre-processing time Ts and the preparation time Tp in the function test, and these measurement results are filed. Store in the storage unit 18.

Based on these measurement results stored in the file storage unit 18, the control unit 11 performs the test after the specified electrical condition, which is the waiting time that the user of the test system 10 wants to set by the test program description, is prepared. The calculation of the following expression representing the time until immediately before the start is performed, and the calculation result is stored in the file storage unit 18 and displayed on the display unit 19 as “dead time”.
DC test wait time setting value =
DUT20 specification wait time-(post-processing time Te + measurement preparation time Tm)
Function test wait time setting value =
DUT20 specification waiting time-(post-processing time Te + pre-processing time Ts + preparation time Tp)

The user of the test system 10 visually confirms the dead time displayed on the display unit 19 by the actual measurement of the time measuring unit 17, and based on the calculation results reflecting these dead times, the DC test and the function test are performed. Set the optimal waiting time in the test program description.
DC test wait time set value = DUT20 specification wait time-dead time Function test wait time set value = DUT20 specification wait time-dead time

  As a result, the optimum waiting time in the test program description can shorten the dead time of (post-processing time Te + measurement preparation time Tm) for the DC test than the conventional DUT 20 specification waiting time, and the function test for the conventional DUT 20 specification. Since the dead time of (the post-processing time Te + the pre-processing time Ts + the preparation time Tp) can be shortened rather than the waiting time, the test program program execution time can be shortened and the productivity can be increased.

  FIG. 2 is a flowchart of a test execution process based on the present invention, where (A) shows a DC test system and (B) shows a function test system. In FIG. 2, the test program description, the control process, and the time measurement are shown along the execution process flow as in FIG.

  Focusing on the flow of control processing in the DC test, after setting parameters necessary for the DC test in various registers (step SP1), a fixed post-processing time is set (step SP2). Thereafter, measurement preparation processing is performed (step SP3), and measurement start processing is executed (step SP4). As a result, a predetermined voltage output VF and a current output IF are added from the source / measure unit 12 to the DUT 20, and the source / measure unit 12 measures the voltage input VS and the current input IS output from the DUT 20 to the source / measure unit 12. A series of DC test measurement processes are terminated (step SP5).

  Here, paying attention to the test program description of the DC test, step SP1 and step SP2 of the control processing are “setting”, and steps SP3 to SP5 are “voltage / current measurement”.

  Further, when paying attention to the time measurement of the DC test, step SP1 and step SP2 of the control process become “set time”, step SP3 to step SP5 become “measurement time”, and step SP2 and step SP3 are set based on the setting according to the present invention. It becomes “dead time measurement” until measurement.

  Focusing on the flow of control processing in the function test, after setting parameters necessary for the function test in various registers (step SP1), a fixed post-processing time is set (step SP2). Thereafter, pre-processing is performed (step SP3), pattern travel preparation processing is performed (step SP4), pattern travel start processing is performed (step SP5), and necessary for function tests set in various registers after a predetermined time. A series of pattern travel processing based on the parameters is terminated (step SP6).

  Here, paying attention to the test program description of the function test, steps SP1 and SP2 of the control processing are “setting”, and steps SP3 to SP6 are “pattern running”.

  Further, when paying attention to the time measurement of the function test, step SP1 and step SP2 of the control process are “set time”, step SP3 to SP6 are “pattern travel time”, and step SP2 to step SP4 are set according to the present invention. It becomes "dead time measurement" from the start to the pattern running.

  As described above, according to the present invention, it is possible to provide an LSI test system capable of improving the productivity by optimizing the “waiting time setting” in the test program description and reducing the test program program execution time.

It is a block diagram which shows the principal part of one Example of this invention. It is a flowchart of the test execution process based on this invention. It is a block diagram of each test system in an LSI test system. It is a wave form diagram of each test system. It is a flowchart of the test execution process in each test system. 6 is a timing chart example corresponding to the flowchart of the function test in FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Test system 11 Control part 12 Source measure part 13 Pattern generation part 14 Pin electronics part 15 Various registers 16 Setting part 17 Time measurement part 18 Time data storage part 19 Display part 20 DUT

Claims (1)

In an LSI test system configured to execute a predetermined test after parameters required for the test of a test target semiconductor are set in various registers and electrical conditions specified for the test target semiconductor are prepared,
In setting the time from when the specified electrical condition is met to immediately before the start of a predetermined test as a waiting time by the test program description,
A time measuring unit for measuring the post-processing time Te and the measurement preparation time Tm in the DC test and the post-processing time Te, the pre-processing time Ts and the preparation time Tp in the function test ;
Based on the measurement result of this time measurement unit , a control unit that performs the calculation of the following equation representing the time from when the specified electrical condition is met until just before the start of the test;
DC test waiting time set value = specification waiting time of the test target semiconductor− (post-processing time T e + measurement preparation time Tm)
Wait time setting value of the function test = the test semiconductor Specifications latency - (trailing processing time Te + pretreatment time Ts + preparation time Tp)
A display unit is provided to display the calculation results of this control unit as dead time from various register settings to the start of measurement ,
An LSI characterized in that the test program program execution time is shortened by setting the optimum waiting time in the test program description of the DC test and the function test based on the dead time measured and displayed as follows: Test system.
DC test wait time setting value = specification wait time of the semiconductor to be tested-dead time
Function test wait time set value = Specification wait time of the test target semiconductor-Waste time

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