JP4783387B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that includes a plurality of arithmetic circuits arranged in a matrix and is configured such that a wiring path between arithmetic circuits can be changed.

  In accordance with Moore's Law, integrated circuits are on the path of miniaturization year by year. Although LSI performance continues to improve due to advances in manufacturing technology, variations in circuit performance due to variations in device characteristics have become serious. As shown in FIG. 17, previously, a variation component called device-to-chip variation in which device characteristics fluctuate smoothly on the wafer was dominant. However, in recent microprocesses, device characteristics have a probability distribution within a chip. The variation in the chip that changes based on this is dominant. In the figure, frequency corresponds to the performance of the chip. In-chip variation in a fine process is caused by random variation in impurity density that affects the threshold voltage of a transistor.

  In order to solve such variations in device characteristics, a design that takes into account variations due to statistical static delay analysis (SSTA) (see, for example, Non-Patent Document 1) or DFM has been devised. The conventional method for intra-chip variation only suppresses the variation using process technology or circuit technology. For example, there is substrate bias control for controlling the substrate voltage for each chip or functional block (see Non-Patent Document 2). However, as described in Non-Patent Document 3, since it is impossible to supply various voltages to a small region having different characteristics, the substrate bias control is effective in the high frequency band and the current fine process. small.

  It is expected that it will be difficult to suppress device variations in future miniaturization processes. Therefore, the inventor of the present application has proposed a device that can use intra-chip variation instead of suppressing variation and can be reconfigured according to the variation (see Non-Patent Document 4). Thereby, the circuit performance can be further improved as the variation in the chip becomes larger.

  In order to observe variations in FPGA (Field Programmable Gate Array (registered trademark)) in the current fine process, an island-style FPGA was prototyped in a 90 nm process. FIG. 18A is a schematic view showing the entire structure of the FPGA, and FIG. 18B is a photograph of the chip.

  As shown in FIG. 18A, the FPGA has a 48 × 48 logic block array, and the chip area is 3 mm square. This chip further includes a PLL, an SRAM, and a counter.

  FIG. 19 is a schematic diagram illustrating the structure of the FPGA. The FPGA includes a plurality of CLBs 130 (variable logic blocks), SB140 (switch blocks) and CB170 (input / output switches). It is provided as a component. By arranging the layout units in the figure as macros and arranging them in an array of 48 × 48, 47 × 47 becomes a substantially homogeneous layout.

  FIG. 20A is a circuit diagram showing a configuration of the CLB 130. FIG. The CLB 130 includes a four-input LUT 131, four selectors 132a, 132b, 132c, and 132d, and five DFFs 133a, 133b, 133c, 133d, and 133e. In this prototype FPGA, selectors 132a, 132b, 132d and DFFs 133b, 133d are added. The area overhead due to this addition is 23%, but the increase in the entire chip is only 1%.

  FIG. 20B is a circuit diagram showing the DFF 133b. The DFF 133b is used as a frequency divider, divides the oscillation waveform from the selector 132c several times, and outputs a divided waveform. Since this oscillation frequency depends on the performance (delay time) of the logic block array, the performance can be determined by measuring the oscillation frequency.

  The oscillation waveform is generated by providing a ring oscillator (RO) in the FPGA. FIG. 21A is a circuit diagram showing a configuration example of the ring oscillator. The ring oscillator oscillates by connecting a plurality of inverters in a ring shape.

As shown in FIG. 21B, such a ring oscillator is configured using one logic block and oscillated. The oscillation waveform is divided by the DFF 133b shown in FIG. 20B, and the number of oscillations for a predetermined time is counted by the counter. Here, when the frequency division frequency is d, the oscillation frequency is N, and the counting time is T, the frequency f is
f = (N × 2 ^d ) / T
It becomes.

  In this manner, the frequency f is measured in 47 × 48 × 8 blocks per chip. FIG. 22 is a schematic diagram showing the variation measurement result of FPGA, and the shade of each logical block is determined by the performance. Even in the same place in the samples A to D, the speed varies depending on the configuration, and even the adjacent logical blocks may have completely different performance. Thus, it can be seen that random variations without positional correlation are dominant in the prototype chip.

  FIG. 23 is a histogram showing the results of FPGA variation measurement, and shows the oscillation frequency distribution of 16192 ring oscillators per chip. This histogram almost coincides with the curve obtained by substituting μ and σ of the measurement result into the probability density function of the normal distribution, the 10-chip average of skewness is 0.0055, and the 10-chip average of kurtosis is 0.025. From this, it can be seen that the in-chip delay variation follows a normal distribution.

  Non-Patent Document 5 discloses three methods of function allocation (region relocation), multiple configurations (multiple configurations), and critical path reconfiguration (critical path reconfiguration) that use intra-chip variation in an FPGA. ing.

  The function assignment according to the region is suitable for systematic variations in which device characteristics smoothly change on the chip. If the systematic variation is dominant, the device characteristics change depending on the position on the chip. Thus, if there is a correlation between the variations of adjacent elements, it is easy to obtain a variation map for each chip by measuring the delay variation. In multiple configurations and critical path reconfiguration, functional blocks having relatively long critical paths are assigned to areas that are faster due to systematic variations to prevent circuit performance degradation due to random variations.

  However, as shown in FIG. 22, random variations without positional correlation are dominant in the current fine process. If uncorrelated random variations are dominant, the characteristics of the individual transistors constituting these elements are all different. For example, each switch constituting the switch block has a different speed.

  Therefore, it is very difficult to predict the performance of each logical block, switch block, and connection block and measure the speed variation of each switch by the function allocation method according to the area. As pointed out in Non-Patent Document 6, since it is difficult to obtain detailed variation information for optimal arrangement for each chip, an optimal configuration is obtained for each chip based on the measured variation map. It is impossible.

  For this reason, critical path reconfiguration and multiple configurations are suitable as methods for improving the reduction in speed and yield due to random variations.

  FIG. 24 is a conceptual diagram of multiple configurations. Non-Patent Document 7 proposes a multi-configuration technique called MECPCs (Mutual Exclusive Critical Path Configurations). This provides multiple configurations with approximately the same performance. The configuration is wired so that the critical path does not use elements already used by the critical path of the configuration generated earlier. The configuration generated here is mounted on the FPGA, and timing verification is performed until a configuration satisfying the timing constraint is found.

  FIG. 25 is a conceptual diagram of critical path reconstruction. In the critical path reconfiguration, the initial configuration is the same for all chips. Rewiring critical paths that do not meet timing constraints and verifying timing. Rewiring and timing verification are repeated until all critical paths satisfy timing constraints or exceed a certain number of times.

  For multiple configurations, test all configurations. As the number of critical paths increases, the probability that the critical path violates the timing constraint also increases.

  On the other hand, in critical path reconfiguration, critical paths that satisfy timing constraints are fixed, and only paths that violate timing constraints are rerouted. The configuration is gradually optimized to meet the random variations of individual chips.

  FIG. 26 is a block diagram showing a configuration of a conventional semiconductor device 91. The semiconductor device 91 is configured by a field programmable device and includes a substrate 2. On the substrate 2, a plurality of CLBs 93a to CLB 93o are arranged in a matrix. Further, SBs 94a to 94h are provided at positions surrounded by four CLBs. A plurality of tracks 5 are provided between adjacent CLBs 93, and each SB 94 includes one of the tracks 5 between adjacent CLBs 93 and one of the tracks 5 between other adjacent CLBs 93. Connect the book.

  The SB 94 is a switch block disclosed in Non-Patent Document 8 that discloses a general FPGA of an island-style architecture. FIG. 27 is a schematic diagram showing the structure of the SB 94, and there are four wiring tracks between CLBs. The wiring track L1 can be connected to the wiring tracks T1, R1, and B1. Similarly, each wiring track can be connected to a wiring track in three directions. Thus, in SB94, the degree of freedom Fs of the switch block is 3. Here, the degree of freedom refers to the number of other wiring tracks to which each wiring track can be connected (see Non-Patent Document 9).

  FIG. 28 is a conceptual diagram showing track replacement of a critical path. When the critical path violates the timing constraint, the wiring path changing unit 6 shown in FIG. 26 reroutes the path between the CLBs to the adjacent wiring track. Only rewiring that will improve delay when rewired to an adjacent wiring track is accepted.

  Further, in order to execute rewiring, it is necessary to know which path is the optimum path (critical path). In FIG. 29, consider a case where a critical path is searched for in the paths CLB93a to CLB93e to CLB93i to CLB93l and the paths CLB93d to CLB93k to CLB93o.

FIG. 30 is an explanatory diagram showing a critical path search method based on the Path-Delay method. The Path-Delay method is a general search method disclosed in Non-Patent Document 10, Non-Patent Document 11, and the like. In the Path-Delay method, when searching for a critical path of CLB 93a to CLB 93e to CLB 93i to CLB 93l, CLB 93a is set as a signal transmission start point (SRC), and CLB 93l is set as a signal transmission end point (SINK). Further, in order to accurately measure the delay time between CLBs, measurement is performed by changing the clock cycle. This is a method of measuring how much a signal can be normally transmitted between CLBs by changing the clock cycle little by little.
M.M. Chao, L.C. Wang, K.K. Cheng, and S.C. Kundu. Static Statistical timing Analysis for Latch-based Pipeline Design. Proceedings of the International Conference of Computer Aided Design, pages 468-472, 2004. Proceedings of the International Conference of Computer Aided Design, pages 468-472, 2004. M.M. Sumita, S .; Sakiyama, M .; Kinoshita, Y. et al. Araki, Y. et al. Ikeda, and K.K. Fukuoka. Mixed body-bias technologies with ￣xed Vt and Ids generation circuits. IEEE International Solid-State Circuits Conference, XVII, pages 158-159, 2004. S. Ohkawa, M .; Aoki, and H.A. Masuda. Analysis and Characterisation of Device Variations in an LSI Chip Using an Integrated Device Matrix Array. IEEE Trans. on Semiconductor Manufacturing, Vol. 17, no. 2, pages 155-165, 2004. K. Katsuki, M .; Kotani, K .; Kobayashi, and H.K. Onodera. A Yield and Speed Enhancement Scheme under With-die Variations on 90 nm LUT Array. In Proceedings of IEEE 2005 Custom Integrated Circuits Conference, pages 601-604, 2005. P. Sedcore and P.M. Cheung. Parametric Yields in FPGAs due to within-die delay variations: a quantitative analysis. Proceedings of the 2007 ACM / SIGDA 15th international symposium on Field programmable gate arrays, pages 178-187, 2007. L. Cheng, J.M. Xiong, L.A. He, and M.M. Hutton. FPGA Performance Optimization via Chipwise Placement Concealing Process Variations. Proceedings of 2006, International Conference on Field, Programmable Logic and Applications, pages 44-49, 2006. Y. Matsumoto, M .; Hioki, T .; Kawanami, T .; Tsutsumi, K .; Nakagawa, T .; Sekikawa, and H.K. Koike. Performance and Yield Enhancement of FPGAs with With-die Variation using multiple Conjugations. International Symposium on Field-Programmable Gate Arrays, pages 169-177, 2007. Y. -W. Chang, D.C. F. Wong, and C.W. K. Wong. Universal switch modules for fpga design. ACM Trans. Des. Autom. Electron. Syst. , 1 (1): 80-101, 1996. J. et al. Rose, S.M. Brown, “Flexibility of interconnection structures for field-programmable gate arrays” IEEE Journal of Solid-State Circuits, Vol. 26: 277-282, 1991. S. Bose, P.M. Agrawal, and V.A. D. Agrawal, “A rated-clock test method for path delay faults,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 323-331. H. Chang, J. et al. A. Abraham, “Delay test techniques for boundary scan based architectures,” 1992 IEEE Custom Integrated Circuits Conference.

  However, the conventional critical path reconstruction method has a problem that it is difficult to reconfigure the configuration so as to satisfy the timing constraint.

  FIG. 31A is a schematic diagram showing a connection relationship in the initial wiring, and five paths A to E pass through the switch block. It is assumed that Path A is a critical path and the others are not critical paths. Here, since Path A violates the timing constraint, a case where rewiring from track 1 to track 0 is considered.

  FIG. 31B is a schematic diagram showing a connection relationship after rewiring when the SB 94 with Fs = 3 shown in FIG. 27 is used. When Path A is rewired from Track 1 to Track 0, Path B and C must also be rewired to Tracks 1 and 0 for the entire path. As a result, another switch block needs to be rewired for another path, and the wiring topology may be changed. Therefore, the path delay distribution of the circuit may change and a new critical path may occur.

  FIG. 32 is a schematic diagram showing a rewiring connection relationship in the semiconductor device 91. FIG. 32A shows the initial wiring, and FIG. 32B shows the wiring after the path change. As indicated by the arrows, by replacing the track of the critical path A, the paths B, C, and D also need to be rewired. This can increase the delay.

Further, in the Path-Delay method shown in FIG. 30, in order to extract the shortest path among a plurality of paths, it is necessary to know the absolute value of the delay of each path. For example, in the path of CLB 93d to CLB 93k to CLB 93o, there are two sections CLB 93d to CLB 93k and CLB 93k to CLB 93o, and there are two wiring paths in each section. Therefore, since CLB93d to CLB93o have a total of 2 ² = 4 wiring paths, four measurements are required to know the absolute value of the delay of each wiring path. Similarly, in the paths CLB93a to CLB93e to CLB93i to CLB931, there are three sections CLB93a to CLB93e, CLB93e to CLB93i, and CLB93i to CLB93l, and there are two wiring paths in each section. Therefore, since CLB 93a to CLB 93l have a total of 2 ³ = 8 wiring paths, eight measurements are required to know the absolute value of the delay of each wiring path. Thus, since many measurement frequency is required, there exists a problem that a measurement cost will increase.

The present invention has been made in view of the above problems, and an object of the present invention is to realize a semiconductor device capable of suppressing the measurement cost of a critical path between a plurality of arithmetic circuits.

  In order to solve the above-described problem, a semiconductor device according to the present invention includes a plurality of arithmetic circuits arranged in a matrix and an adjacent one of four arithmetic circuits adjacent to each other among the plurality of arithmetic circuits. A plurality of wiring tracks arranged between the two arithmetic circuits, and a plurality of wiring tracks provided between the two arithmetic circuits adjacent to each other. And a switch block for connecting one of the plurality of wiring tracks between the other two arithmetic circuits adjacent to each other, and one of the plurality of arithmetic circuits. In order to transmit a signal to the other one of the arithmetic circuits in order to compare the delay of the first wiring path and the second wiring path respectively constituted by the wiring track and the switch block. A first delay comparator provided in another one and a wiring block and a switch block for transmitting a signal from another one of the plurality of arithmetic circuits to another one, respectively; And a second delay comparator provided in another one of the arithmetic circuits in order to compare the delay of the third wiring path and the fourth wiring path configured by .

One of a plurality of arithmetic circuits is a signal transmission start point, and the other one of the arithmetic circuits is a signal transmission end point via the other one of the arithmetic circuits. When searching for a critical path, the conventional Path-Delay method requires 2 ² = 4 measurement times. On the other hand, according to the above configuration, in the first measurement, the first delay comparator compares the delays of the first wiring path and the second wiring path, and in the second measurement, the second delay comparator The delays of the third wiring path and the fourth wiring path are compared. That is, the number of measurements required for searching the critical path is only two, and there is no need to measure the absolute value of the delay. Therefore, there is an effect that it is possible to realize a semiconductor device capable of suppressing the measurement cost of a critical path between a plurality of arithmetic circuits.

  In the semiconductor device according to the present invention, it is preferable that the first delay comparator and the second delay comparator are configured by SR latches.

  According to the above configuration, the first delay comparator and the second delay comparator can determine which of the input signals has arrived first, and can be configured with two NANDs. Therefore, the increase in circuit area is small.

  In the semiconductor device according to the present invention, it is preferable that the other one of the arithmetic circuits and the other one have a clustered LUT provided in the preceding stage of the SR latch.

  According to the above configuration, the arithmetic circuit can be a signal transmission start point by configuring the LUT with an inverter, and the arithmetic circuit can be the signal transmission end point by configuring the LUT with NAND.

  In the semiconductor device according to the present invention, each arithmetic circuit may be constituted by a variable logic block.

As described above, the semiconductor device according to the present invention includes a plurality of arithmetic circuits arranged in a matrix, and two adjacent ones of four arithmetic circuits adjacent to each other among the plurality of arithmetic circuits. A plurality of wiring tracks arranged so as to pass between the four arithmetic circuits and a position surrounded by the four arithmetic circuits, out of the plural wiring tracks between the two arithmetic circuits adjacent to each other. A switch block connecting one and one of a plurality of wiring tracks between two other arithmetic circuits adjacent to each other, and one of the plurality of arithmetic circuits to another one One of the arithmetic circuits to compare the delay of the first wiring path and the second wiring path formed by the wiring track and the switch block, respectively. A first delay comparator, and a wiring block and a switch block, respectively, for transmitting a signal from another one of the plurality of arithmetic circuits to the other one. In order to compare the delays of the third wiring path and the fourth wiring path, the second delay comparator provided in the other one of the arithmetic circuits is provided, so that the criticality between the plural arithmetic circuits is provided. There is an effect that it is possible to realize a semiconductor device capable of reducing the path measurement cost.

  An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 has a configuration in which CLB 93a to 93o are replaced with CLB 3a to 3o and SB 94a to 94h are replaced with SB 4a to 4h in the semiconductor device 91 shown in FIG. The degree of freedom Fs of SBs 94a to 94h is 3, whereas the degree of freedom Fs of SBs 4a to 4h is 6. In FIG. 1, the illustration of CB shown in FIG. 19 is omitted.

  FIG. 2 is a schematic diagram showing the connection relationship of SB4. Compared to SB94 shown in FIG. 27, the track L1 of SB4 can be connected to the tracks T0, R0, B0 in addition to the tracks T1, R1, B1. Similarly, each track can be connected to the other six tracks.

  FIG. 3 is a schematic diagram showing a connection relationship after rewiring from the initial wiring in FIG. 31A when SB4 with Fs = 6 is used. When SB94 with Fs = 3 is used, when Path A is rewired from Track 1 to Track 0, Path B and C are also rewired to Tracks 1 and 0 as shown in FIG. There must be. On the other hand, in FIG. 3, only Path B is rewired by rewiring Path A, and other Paths C to E do not need to be rewired. For this reason, the possibility that the rewiring of the path is required in other switch blocks is reduced, and the configuration can be easily reconfigured.

  FIG. 4A is a schematic diagram showing initial wiring when SB4 with Fs = 6 is used, and FIG. 4B is a schematic diagram showing a connection relationship after rewiring. FIG. 4A is the same as FIG. In this case, it is not necessary to reroute Path B and C as a whole by changing the track of Path A, and only a small part of Path B is rewired. Therefore, the influence of the critical path rewiring on other paths is negligible, and the influence of the track replacement on the path delay distribution of the circuit is small. In this way, by increasing the degree of freedom of the switch block from 3 to 6, it becomes easy to reroute critical paths that violate the timing constraints by changing the track.

  As described above, since the track change of the chain path can be suppressed by increasing the degree of freedom Fs of the switch block, the configuration can be easily reconfigured. In the present embodiment, the case of increasing from Fs = 3 (FIG. 5A) to Fs = 6 (FIG. 5B) has been described, but Fs = 9 may be set for some wiring tracks (FIG. c)).

  FIG. 5C is a schematic diagram showing the SB 14 with Fs = 9 for some of the wiring tracks. The dots in the switch block indicate connection switches. In SB14, Fs = 6 for tracks L0, L3, B0, B3, R0, R3, T0, T3, and Fs = 9 for tracks L1, L2, B1, B2, R1, R2, T1, T2. . As described above, by further increasing the degree of freedom of wiring, it is possible to increase the delay reduction effect using variation. Further, Fs may be set to a multiple of 3 that is 9 or more, and the effect of reducing delay can be further increased.

  On the other hand, if the degree of freedom of the switch block is increased, an extra circuit is required. Since NMOS switches are provided between tracks, when there are four wiring tracks, 24 (= 6 × 4) switches are required to form a switch block with Fs = 3, and Fs = 6. 48 (= 6 × 4 × 2) switches are required to construct the switch block. In the switch block with Fs = 6, track 0 and track 1 and track 2 and track 3 can be interchanged. However, in the conventional switch block composed of CMOS and NMOS switches, the area is doubled when Fs = 6. . In a fine process, when such a non-buffering switch is used, signal attenuation and slew rate deterioration become problems.

  Therefore, if the switch of the buf architecture shown in FIG. 6 is used, the area penalty becomes very small. When Fs = 6, compared with Fs = 3, the number of 12 NMOS switches in the center (FIG. 6A) is doubled (FIG. 6B), but the other elements are the same. It is a configuration.

  Table 1 shows the relationship among the number of NMOS switches, area, and delay in the switch block shown in FIG. Since the number of NMOS switches is proportional to Fs, it is doubled. However, the area and delay are only 18.5% and 5.0%, respectively, and it can be seen that the area overhead is small.

  Next, the track replacement procedure will be described.

  FIG. 7 is a flowchart of critical path reconstruction by track replacement. After the manufacturing process (step S1), an initial configuration is created by a conventional placement and routing tool without considering variations (step S2). This is a common configuration for all chips. In the critical path reconstruction method, paths that can become critical paths are rewired, so it is necessary to estimate which paths are likely to become critical paths (step S3). The delay of the estimated critical path candidate is measured, and if the delay constraint is violated (“fail” in step S4), rewiring is performed by track replacement (step S5). After rewiring, delay measurement is performed again (step S6). If the replacement destination track is also used by a critical path candidate ("pass" in step S6), the replacement is not performed (step S7). A path that violates the delay constraint may be rewired with the topology changed (step S8), or the optimization may be completed when all critical path candidates satisfy the delay constraint. Note that the track replacement in step S5 is performed between two adjacent tracks as shown in FIG.

  Next, a critical path search method according to this embodiment will be described.

  As shown in FIG. 30, in the conventional Path-Delay method, eight measurements are required to extract the critical paths of CLB 93a to CLB 93l. In contrast, in the present embodiment, a critical path is searched using a delay comparator.

  FIG. 9 is an explanatory diagram of the critical path search method according to the present embodiment. When searching for a critical path in a path of CLB3a to CLB3e to CLB3i to CLB3l and a path of CLB3d to CLB3k to CLB3o, as shown in FIG. Compare delays of two paths in each section of ~ CLB3k. At this time, CLB 3a, CLB 3i, and CLB 3d serve as signal transmission start points (SRC), and a delay comparator (DD, first delay comparator) is provided for each of CLB 3e, CLB 31, and CLB 3k that are signal transmission end points. The delay comparator compares delays of two wiring paths (first wiring path and second wiring path) in each section. Thereby, the route of each section is selected as shown by the broken line in FIG.

  Furthermore, in the second measurement, the delays of the two paths in each section of CLB3e to CLB3i and CLB3k to CLB3o are compared. At this time, CLB 3e and CLB 3k serve as signal transmission start points (SRC), and a delay comparator (DD, second delay comparator) is provided for each of CLB 3i and CLB 3o serving as signal transmission end points. The delay comparator compares the delays of two wiring paths (third wiring path and fourth wiring path) in each section, and selects a path in each section.

  As described above, the critical paths in the paths CLB3a to CLB3e to CLB3i to CLB3l and the paths CLB3d to CLB3k to CLB3o can be searched by two measurements. Therefore, compared with the conventional Path-Delay method, the number of times of measurement can be greatly reduced, so that the measurement cost can be suppressed.

  Next, a detailed configuration of the CLB in which the delay comparator is incorporated will be described.

  FIG. 10 is a circuit diagram showing a configuration of CLB3. The CLB 3 receives a signal from the paths A and B and outputs a signal to the paths QA and QB. The CLB 3 includes two clustered LUTs 31a and 31b, an SR latch 32, two DFFs 33a and 33b, and two selectors 34a and 34b. The LUTs 31a and 31b are connected to paths A and B, respectively. Signals from the LUTs 31a and 31b are output to the SR latch 32 and also to the selectors 34a and 34b, respectively. One of the signals from the SR latch is output to the selector 34a via the DFF 33a, and the other of the signals from the SR latch is output to the selector 34b via the DFF 33b. The signal from the selector 34a is output to the path QA and also to the LUT 31a or the LUT 31b. Similarly, the signal from the selector 34b is output to the path QB and also to the LUTs 31a and 31b.

  In each measurement in FIG. 9, when CLB3 becomes the signal transmission starting point (SRC), as shown in FIG. 11A, the LUTs 31a and 31b are configured by inverters. The selectors 34a and 34b select signals from the DFFs 33a and 33b, respectively. The signals from the selectors 34a and 34b are output to the paths QA and QB, respectively, and also output to the LUT 31a or LUT 31b that is an inverter. In FIG. 11A, the SR latch 32 is omitted, but when the SR latch 32 applies a clock to the DFFs 33a and 33b once, signals are simultaneously output from the CLB 3 to the paths QA and QB.

  Further, when CLB3 becomes the signal transmission end point (delay comparator mode), as shown in FIG. 11B, the LUTs 31a and 31b are configured by NANDs. The selectors 34a and 34b select signals from the LUTs 31a and 31b, respectively. The signals from the selectors 34a and 34b are output to the paths QA and QB, respectively, and also output to the LUTs 31b and 31a. Also in FIG. 11B, the SR latch 32 is omitted.

  The operation when CLB 3 is the signal transmission end point will be described with reference to FIG. The delay comparator mode CLB3 shown in FIG. 11B is equivalent to the flip-flop shown in FIG.

  In the initial state, as shown in FIG. 12A, since the input from the paths A and B is 0: 0, the output to the paths QA and QB is 1: 1. Subsequently, as shown in FIG. 12B, if the input from the path A is 1 first, the output to the paths QA and QB is 0: 1. Further, as shown in FIG. 12C, even if the input from the path B becomes 1, the output to the paths QA and QB remains 0: 1. On the contrary, if the input from the path B is 1 first, the output to the path QA / QB is 1: 0, and even if the input from the path A is 1 later, the output to the path QA / QB Remains unchanged at 1: 0. In this manner, the delay comparator mode CLB 3 can determine which path A or B the signal has arrived first.

  Therefore, even if the path length between the signal transmission start point and the signal transmission end point is different, a plurality of paths can be measured simultaneously. When the SR latch 32 is not provided, it functions as a delay comparator without circuit overhead, but it is difficult to determine a delay of 30 ps or less. On the other hand, by providing the SR latch 32, a delay of 1 ps or less can be discriminated, and the comparison performance can be remarkably improved as compared with the conventional Path-Delay method.

  Although the delay between the LUTs 31a and 31b and the DFFs 33a and 33b is increased by the SR latch 32, since the ratio of the delay in the SR latch 32 to the total delay is small, the influence is small. For example, when the paths shown in FIG. 28 are compared, CLB3 in the middle uses only the LUT and does not use the FF. As described above, since the SR latch 32 is incorporated immediately before the FF, the signal does not pass through the SR latch 32. Therefore, the delay increases only in the CLB3 at the signal transmission end point.

  Next, critical path estimation by statistical MAX calculation will be described.

  Since the path delay varies in a certain distribution due to process variations, it is necessary to reconfigure all paths that can become critical paths, not just the maximum delay path obtained by static delay analysis.

FIG. 13 is a graph showing a critical path estimation method. The average of the circuit delay distribution and _{d Circuit,} delay value is a critical path candidates possible paths over the _{d Circuit.} Also, let d _i and σ _{i be} the average delay and standard deviation of path i, d _longest and σ _{longest be} the average delay and standard deviation of the longest path, and pass i satisfying d _i + 3σ _i > d _longest −3σ _longest Let it be a path candidate. d _circuit is a sub-path of Clerk's method (see C. E. Clark. The greatest of a set of random variables. Operations Research, 9 (2): 145-162, 1961.). Obtained by statistical MAX calculation of distribution. A path i satisfying d _i + 3σ _i > d _circuit is a critical path candidate. Critical path reconstruction is performed on critical path candidates obtained by this method.

  VPR (V. Betz and J. Rose. VPR: A new packing, placement and routing tool for FPGA research. In proc. Of Prop at Int. , 1997.), and LGSynth93 benchmark circuits multit16b and dio are arranged and wired. The speed and yield improvement effect was evaluated by Monte Carlo simulation.

  In this experiment, the flow of schematic wiring change in step S8 shown in FIG. 7 is not implemented, and the number of times of reconfiguration is only once. In addition, a greater performance improvement effect can be expected by repeating the reconfiguration.

The FPGA architecture assumed here is an island-style architecture, and the CLB includes one 4-input LUT. The wiring segments are connected by a switch block of the bufp architecture shown in FIG. The benchmark circuit was arranged in a minimum size array, and the channel width of the wiring was 1.2 times the minimum channel width. In the experiment, it was assumed that the resistance and capacitance of the switch and connection block switches varied. The speed and yield improvement effect was obtained by 10,000 Monte Carlo simulations. In the critical path reconstruction method, critical paths that violate a certain timing constraint are rewired. In this experiment, the timing constraint is μ _circuit + iσ _circuit (i = 1, 2, 3), and critical path reconfiguration is performed for a circuit whose delay value is larger than this value. μ _circuit and σ _circuit are the average value and standard deviation of the circuit delay distribution, respectively.

  FIG. 14A is a histogram of circuit delays due to the initial configuration of the multit 16b, and FIG. 14B is a histogram showing circuit delay distributions when a critical path reconfiguration is performed once by track replacement. From the histogram shown in FIG. 14B, it was confirmed that the chip that violated the timing constraint was reconfigured. For example, if the delay constraint is defined as a speed that achieves a yield of 50%, half of the devices that do not satisfy the delay constraint satisfy the delay constraint by replacing paths that do not satisfy the delay constraint using the degree of freedom of wiring. Can be reconfigured. In addition, as the variation becomes larger, the effect of improving the speed becomes higher, and the effect is further increased by miniaturization of devices in the future.

Table 2 shows the speed / yield improvement when μ / σ = 10% and d _spec = μ _circuit + σ _circuit , and it can be seen that the performance is improved in the multit 16b and the dio.

  Here, by implementing the rewiring function by changing the topology, further optimization is possible if rewiring is repeated twice or more. Thus, further performance improvement can be expected by performing more reconfigurations.

Further, Table 3 shows the process variation width μ / σ of the multit 16b and daio, and the speed and yield improvement with respect to the required speed d _spec . The yield is compared by the yield in the required specifications, and the speed improvement is compared by the delay value at which the yield is 99.87%. From Table 3, it can be seen that the yield is improved by a maximum of 26.62% and the speed is improved by a maximum of 5.81%.

FIG. 15 is a graph showing the yield improvement with respect to d _spec = μ + σ, μ + 2σ, and μ + 3σ in the range of process variation μ / σ = 2%, 4%, and 10% of Table 16 in Table 3. In either case, it can be seen that a yield of nearly 100% is achieved at the required speed.

  FIGS. 16A and 16B are graphs showing the speed improvement with respect to the variation width of the circuit. FIG. 16A shows the case of the multi 16b process, and FIG. As the variation width increases, faster elements exist. Therefore, it can be seen that, in the critical path reconfiguration method using variation, the improvement in circuit performance after reconfiguration increases as the process variation increases.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be suitably applied to a semiconductor device that includes a plurality of arithmetic circuits arranged in a matrix and is configured such that the wiring path between the arithmetic circuits can be changed.

It is a block diagram which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is the schematic which shows the connection relation of the switch block with which the semiconductor device shown in FIG. 1 is provided. It is the schematic which shows the connection relation after the rewiring from the initial wiring of Fig.31 (a) in the case of using the switch block shown in FIG. (A) is the schematic which shows the initial wiring at the time of using the switch block shown in FIG. 2, (b) is the schematic which shows the connection relation after rewiring. (A) is a conceptual diagram showing a configuration of a switch block with Fs = 3, (b) is a conceptual diagram showing a configuration of a switch block with Fs = 6, and (c) is a diagram showing Fs = 6 and 9 It is a conceptual diagram which shows the structure of this switch block. (A) is a circuit diagram showing a configuration of a switch block with Fs = 3, and (b) is a circuit diagram showing a configuration of a switch block with Fs = 6. It is a flowchart which shows the critical path reconstruction by the track replacement based on this invention. It is explanatory drawing which shows replacement | exchange between two adjacent tracks. It is explanatory drawing of the critical path search method which concerns on embodiment of this invention, (a) has shown the 1st measurement, (b) has shown the 2nd measurement. It is a circuit diagram which shows the structure of CLB with which the semiconductor device shown in FIG. 1 is provided. 2A and 2B are circuit diagrams illustrating a configuration of a CLB included in the semiconductor device illustrated in FIG. 1, in which FIG. 1A illustrates a signal start mode and FIG. 1B illustrates a delay comparator mode. It is an equivalent circuit diagram showing an operation when the CLB is in the delay comparator mode. 3 is a graph showing a critical path estimation method according to the present invention. (A) is a histogram of the circuit delay due to the initial configuration of the multit 16b, and (b) is a histogram showing the circuit delay distribution when the critical path reconfiguration is performed once by track replacement. It is a graph which shows the yield improvement with respect to d _spec = μ + σ, μ + 2σ, μ + 3σ in each of the variation width μ / σ = 2%, 4% and 10% of the process of the multit 16b. It is a graph which shows the speed improvement with respect to the variation width of a circuit, (a) shows the case of a multi 16b process, (b) has shown the case of a dario process. It is a graph which shows the performance of a chip | tip, and distribution of a chip | tip number. (A) is the schematic which shows the whole structure of trial manufacture FPGA, (b) is a photograph of the chip | tip provided with the said FPGA. It is the schematic which shows the structure of FPGA shown in FIG. (A) is a circuit diagram which shows the structure of CLB provided in said FPGA, (b) is a circuit diagram which shows the structure of DFF provided in the said CLB. (A) is a circuit diagram which shows the structural example of a ring oscillator, (b) is a conceptual diagram which shows the method of discriminating the performance of a logic block using a ring oscillator. It is the schematic which shows the dispersion | variation measurement result of the said prototype FPGA. It is a histogram which shows the dispersion | variation measurement result of the said prototype FPGA. It shows a prior art and is a conceptual diagram of multiple configurations. It shows a prior art and is a conceptual diagram of critical path reconstruction. It is a block diagram which shows the structure of the conventional semiconductor device. FIG. 27 is a schematic diagram illustrating a structure of a switch block included in the semiconductor device illustrated in FIG. 26. It is a conceptual diagram which shows the track replacement of a critical path in the conventional semiconductor device. It is explanatory drawing which shows the critical path search method. It is explanatory drawing which shows the critical path search method by Path-Delay method. (A) is the schematic which shows the connection relation in the initial wiring in a switch block, (b) is the schematic which shows the connection relation after rewiring in the case of using the switch block shown in FIG. It is the schematic which shows the connection relation of the rewiring in the switch block shown in FIG. 27, (a) has shown the initial wiring, (b) has shown the wiring after a route change.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3, 3a-3o Variable logic block (arithmetic circuit)
4, 4a to 4h, 14 switch block 5 tracks (wiring track)
6 Wiring path changing unit (wiring path changing means)
31a, 31b LUT
32 SR latch

Claims (4)

A plurality of arithmetic circuits arranged in a matrix;
A plurality of wiring tracks arranged so as to pass between two adjacent ones of four arithmetic circuits adjacent to each other among the plurality of arithmetic circuits;
Provided at a position surrounded by the four arithmetic circuits and between one of the plurality of wiring tracks between the two adjacent arithmetic circuits and between the other two arithmetic circuits adjacent to each other. A switch block for connecting one of the plurality of wiring tracks;
In order to transmit a signal from one of the plurality of arithmetic circuits to the other one, the delays of the first wiring path and the second wiring path respectively constituted by the wiring track and the switch block are compared. A first delay comparator provided in another one of the arithmetic circuits,
In order to transmit a signal from the other one of the plurality of arithmetic circuits to the other one, a third wiring path and a fourth wiring path formed by the wiring track and the switch block, respectively. A semiconductor device, comprising: a second delay comparator provided in still another one of the arithmetic circuits for comparing delays. The first delay comparator and the second delay comparator semiconductor device of claim 1, wherein is constituted by SR latch. 3. The semiconductor device according to claim 2 , wherein the other one of the arithmetic circuits and the other one have a clustered LUT provided in a preceding stage of the SR latch. Each arithmetic circuit, a semiconductor device according to claim 1, characterized in that is constituted by a variable logic block.