JP4785396B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device formed using a droplet discharge method typified by an ink jet method and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, a so-called active matrix driving display panel or a semiconductor integrated circuit including a semiconductor element typified by a thin film transistor (hereinafter also referred to as “TFT”) on a glass substrate has been subjected to a light exposure process using a photomask ( Hereinafter, it is manufactured by patterning various thin films by a photolithography process.

  In the photolithography process, a resist is applied and formed on the entire surface of the substrate, pre-baked, and then irradiated with ultraviolet rays or the like through a photomask, and a resist pattern is formed by development. Thereafter, the thin film (film formed of a semiconductor material, an insulator material, or a conductor material) existing in a portion to be a film pattern with the resist pattern as a mask pattern is removed by etching to pattern the thin film, A pattern is formed to form a semiconductor element.

On the other hand, a bottom gate TFT is used as a driving element for a pixel of a liquid crystal display. In the bottom gate TFT, inclined portions (tapered portions) are provided at both ends of the gate electrode in the gate insulating layer overlapping the gate electrode in order to prevent electric field concentration in the vicinity of both ends of the gate electrode. Further, in order to improve the step coverage of the gate insulating layer provided on the gate electrode, the gate electrode is similarly provided with a tapered portion (see Patent Document 1).
JP-A-10-170960

  However, in order to form a gate electrode having a tapered portion, a photolithography process is required, and it is necessary to repeat etching, cleaning, and drying processes a plurality of times. For this reason, in the process of forming the semiconductor device, most of the material for the gate electrode and the resist are wasted, and the number of processes for forming the resist mask pattern and the number of processes for forming the gate electrode are increased. There are many problems that the throughput decreases.

  In addition, it is difficult for an exposure apparatus used in the photolithography process to perform exposure processing on a large area substrate at a time. For this reason, in a method for manufacturing a semiconductor device using a large-area substrate, a plurality of exposure times are required, and there is a problem in that yield is reduced due to mismatch between adjacent patterns.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a method for manufacturing a semiconductor device by a method with a small number of steps and an improved material utilization efficiency.

  In addition, a method for manufacturing a semiconductor device with high breakdown voltage and high step coverage of a gate insulating layer, and a liquid crystal television and an EL television including the semiconductor device are provided.

  The gist of the present invention is to form a plurality of conductive layers on a substrate and to form an insulating layer filling between the conductive layers.

  According to the present invention, a plurality of conductive layers are formed on a substrate, a first insulating layer filling the space between the conductive layers is formed, and the plurality of conductive layers and the insulating layer filling the conductive layer are formed on the first insulating layer. The gist is to form two insulating layers.

  According to the present invention, a plurality of conductive layers are formed on a substrate, a first insulating layer filling the space between the conductive layers is formed, and a part of the plurality of conductive layers and an insulating layer adjacent to the conductive layer are formed. The gist is to form the second insulating layer on a part of the substrate.

  Further, according to the present invention, after forming a plurality of first conductive layers on a substrate, the first insulating layer is formed so as to fill a space between the first conductive layers. A second insulating layer is formed over the first conductive layer, and a semiconductor region and a second conductive layer are formed over the second insulating layer.

  In the present invention, a plurality of first conductive layers are formed on a substrate, a first insulating layer is formed to cover a side portion of the plurality of first conductive layers, and the first insulating layer and the plurality of first conductive layers are formed. A second insulating layer is formed over one conductive layer, and a semiconductor region and a second conductive layer are formed over the second insulating layer.

  According to the present invention, a plurality of first conductive layers are formed on a substrate, an insulating material is discharged between the plurality of first conductive layers by a droplet discharge method, and the first insulating layer is formed. A second insulating layer is formed over the first insulating layer and the plurality of first conductive layers, and a semiconductor region and a second conductive layer are formed over the second insulating layer.

  Note that the first conductive layer functions as a gate electrode, the second insulating layer functions as a gate insulating layer, and the second conductive layer forms a so-called bottom gate TFT that functions as a source electrode and a drain electrode. At this time, a source region and a drain region may be formed between the semiconductor region and the second conductive layer.

  In addition, the first conductive layer functions as a source electrode and a drain electrode, the second insulating layer functions as a gate insulating layer, and the second conductive layer functions as a gate electrode, which constitutes a so-called top gate TFT. At this time, a source region and a drain region may be formed between the second conductive layer and the semiconductor region.

  According to the present invention, a plurality of first conductive layers are formed on a substrate, an insulating material is discharged between the plurality of first conductive layers by a droplet discharge method, and the first insulating layer is formed. Forming a second insulating layer over a part of the first insulating layer and a part of the plurality of first conductive layers, and forming a semiconductor region over the second insulating layer and the first conductive layer; Features.

  Note that the first conductive layer functions as a gate electrode, a source electrode, and a drain electrode, and the second insulating layer functions as a gate insulating layer, which constitutes a so-called bottom gate TFT coplanar TFT. At this time, a source region and a drain region may be formed between the semiconductor region and the source electrode and the drain electrode, respectively.

  The present invention also provides a plurality of first conductive layers formed on an insulating surface, a first insulating layer formed between the plurality of first conductive layers, a plurality of first conductive layers, A second insulating layer formed in contact with the surface of the first insulating layer; a semiconductor region formed on the second insulating layer; and a second conductive layer provided on the semiconductor region. The semiconductor region has a first region that overlaps the first conductive layer, the first insulating layer, and the second insulating layer, and a first region that overlaps the first conductive layer and the second insulating layer. And 2 regions.

  Note that when the thickness of the first conductive layer is larger than the thickness of the first insulating layer, the ratio b / a (b <b) of the thickness b of the first insulating layer and the thickness a of the first conductive layer a) is 0.7 or more and 1 or less.

In addition, when the thickness of the first conductive layer is smaller than the thickness of the first insulating layer, the thickness of the first insulating layer (the first insulating layer and the first conductive layer is larger than the thickness of the first conductive layer). Thickness difference) b−a is thinner than the thickness c of the second insulating layer. That is, the relationship 0 <b−a <c (b> a) is satisfied.

  The first insulating layer may be raised along the side surface of the first conductive layer. That is, the first insulating layer is concave with respect to the insulating surface.

  On the other hand, the region of the first insulating layer in contact with the first conductive layer may be recessed with respect to the side surface of the first conductive layer. That is, the first insulating layer is convex with respect to the insulating surface.

  The contact angle of the first conductive layer with respect to the insulating surface is 70 degrees or more and 135 degrees or less.

  In the present invention, examples of the semiconductor device include an integrated circuit including a semiconductor element, a display device, a wireless tag, and an IC tag. As a display device, typically, a liquid crystal display device, a light emitting display device, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display) And display devices such as electrophoretic display devices (electronic paper). Note that the TFT is a forward stagger type TFT, an inverted stagger type TFT (channel etch type TFT or channel protection type TFT), and a coplanar type TFT of a bottom gate TFT.

In the present invention, the display device refers to a device using a display element, that is, an image display device. In addition, a connector such as a flexible printed circuit (FPC), a TAB (Tape Automated Bonding) tape, or a TCP (Tape Carrier) is provided on the display panel.
A module in which a package is attached, a module in which a printed wiring board is provided at the end of a TAB tape or TCP, or a module in which an IC (integrated circuit) or CPU is directly mounted on a display element by a COG (Chip On Glass) method All are included in the display device.

  Furthermore, the present invention is a liquid crystal television or an EL television constituted by the semiconductor device.

  By filling the space between the plurality of conductive layers with the insulating layer as in the present invention, the unevenness of the gate insulating layer formed thereon is reduced, and the step coverage is improved. Therefore, disconnection on both ends of the conductive can be prevented, and the yield of the semiconductor device having the conductive layer and the gate insulating layer can be improved.

  In addition, since the semiconductor device of the present invention can increase the uniformity of the thickness of the gate insulating layer, the breakdown voltage of the gate insulating layer can be increased, and the reliability of the semiconductor device can be improved. .

  Further, a gate insulating layer having high step coverage and high withstand voltage can be formed without forming a gate electrode having a tapered portion, and thus can be applied to various processes.

  Further, by forming an insulating layer that fills a space between the plurality of conductive layers by using a droplet discharge method, a nozzle that is a discharge port of a droplet containing the material of those layers and a substrate relative to each other are formed. A droplet can be discharged to a predetermined place by changing the position. Further, the thickness and thickness of the pattern to be formed can be adjusted by the relative relationship of the nozzle diameter, the droplet discharge amount, and the moving speed between the nozzle and the substrate on which the discharge is formed. For this reason, even on a large-area substrate having a side exceeding 1 to 2 m, the insulating layer can be accurately discharged and formed at a desired location. Further, since an insulating layer can be formed at a predetermined place without using a photolithography process, the number of processes, an increase in throughput, and a cost can be reduced.

  Further, a liquid crystal television and an EL television having the semiconductor device formed by the above manufacturing process can be manufactured at low cost and with high throughput and yield.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a semiconductor device in which a height of an insulating layer filling a plurality of conductive layers is lower than a height of a conductive layer and a manufacturing process thereof are illustrated in FIGS. A description will be given with reference to FIG. In this embodiment mode, description is made using a channel-etched TFT as a bottom gate TFT as a semiconductor device.

  As shown in FIG. 1A, a plurality of first conductive layers 102 and 103 are formed over a substrate 101, and first insulating layers 104 to 106 are formed so as to fill between the first conductive layers. To do.

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, a silicon wafer, a metal plate, or the like can be used. In this case, diffusion of impurities and the like from the substrate side, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), is prevented. It is desirable to form an insulating layer for this purpose. In addition, a substrate in which an insulating layer such as silicon oxide or silicon nitride is formed on the surface of a metal such as stainless steel or a semiconductor substrate can also be used. When the substrate 101 is a glass substrate, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm should be used. Can do. Here, a glass substrate is used as the substrate 101.

  When a plastic substrate is used as the substrate 101, a substrate having a relatively high glass transition point such as PC (polycarbonate), PES (polyethersulfone), PET (polyethylene terephthalate), or PEN (polyethylene naphthalate) is used.

As the first conductive layers 102 and 103, a conductive material is used, and a droplet discharge method, a printing method, an electroplating method, a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), a vapor deposition method, and the like. It is formed by the manufacturing method. The PVD method (Physical Vapor
In the case of using Deposition), CVD (Chemical Vapor Deposition), vapor deposition, or the like, the film is formed by the above film formation method and then etched into a desired shape. Note that, here, a method of forming a pattern with a predetermined shape by discharging a droplet of the adjusted composition from a fine hole is referred to as a droplet discharge method.

  Examples of conductive materials include metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, and Ba. Or indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide, or organic indium used as a transparent conductive layer Organic tin, titanium nitride (TiN), etc. are used as appropriate. Alternatively, the first conductive layers 102 and 103 may be formed by stacking conductive layers formed using these materials.

  In the case where the first conductive layer is formed by a droplet discharge method, a composition in which a conductor is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. As the conductor, a metal of the above conductive material, silver halide fine particles, or the like, or dispersible nanoparticles can be used.

  In addition, it is preferable to use what dissolved or disperse | distributed the material of either gold | metal | money, silver, and copper in the solvent considering the specific resistance value as the composition discharged from a discharge outlet. More preferably, low resistance and inexpensive silver or copper may be used. However, when copper is used, a barrier layer may be provided as a countermeasure against impurities. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone may be used.

  Here, an insulating or conductive substance containing nitrogen such as silicon nitride, silicon oxynitride, aluminum nitride, titanium nitride, or tantalum nitride is preferably used as a barrier layer in the case of using copper as a wiring. It may be formed by a discharge method.

  The viscosity of the composition used for the droplet discharge method is preferably 5 to 20 mPa · s, which is to prevent the drying from occurring and to smoothly discharge the composition from the discharge port. . The surface tension is preferably 40 mN / m or less. Note that the viscosity of the composition may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, ZnO, IZO, GZO, indium tin oxide containing silicon oxide, organic indium, organic tin, or the like is dissolved or dispersed in a solvent is 5 to 20 mPa · s, or silver is dissolved in the solvent. The viscosity of the dispersed composition is 5 to 50 mPa · s, and the viscosity of the composition in which gold is dissolved or dispersed in a solvent is 10 to 20 mPa · s.

  Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.5 to 10 μm. However, when formed in a gas evaporation method, the nanomolecules protected by the dispersant are as fine as about 7 nm, and the nanoparticles are aggregated in the solvent when the surface of each particle is covered with a coating agent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

  The step of discharging the composition may be performed under reduced pressure. This is because the solvent of the composition volatilizes before the composition is discharged and landed on the object to be processed, and the subsequent drying and firing steps can be omitted or shortened. After discharging the solution, one or both of drying and baking steps are performed by laser light irradiation, rapid thermal annealing, a heating furnace, or the like under normal pressure or reduced pressure depending on the material of the solution. The drying and firing steps are both heat treatment steps. For example, the drying is performed at 100 degrees for 3 minutes, and the firing is performed at 200 to 350 degrees for 15 minutes to 120 minutes. Time is different. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is 100 to 800 degrees (preferably 200 to 350 degrees). And By this step, the solvent in the solution is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and shrunk to accelerate fusion and fusion. The atmosphere is an oxygen atmosphere, a nitrogen atmosphere or air. However, although it is preferable to perform in an oxygen atmosphere in which the solvent in which the metal element is dissolved or dispersed is easily removed, a binder formed of an organic substance remains in the conductive layer depending on the heating temperature, atmosphere, and time. .

  In this embodiment mode, the first conductive layers 102 and 103 selectively discharge silver sol (hereinafter referred to as “Ag paste”) in which silver particles of several nanometers are dispersed, dry and baked, and thereby mainly contain silver. A conductive layer as a component is formed. Note that the first conductive layer is formed by irregularly overlapping fine particles, which are conductors, three-dimensionally. That is, it is composed of three-dimensional aggregate particles. For this reason, the surface has fine unevenness. Further, the fine particles are melted into an aggregate of fine particles depending on the temperature of the Ag paste and the heating time. Since the size of the aggregate at this time increases depending on the temperature of the Ag paste and the heating time thereof, it becomes a layer having a large surface height difference. The region where the fine particles are melted may have a polycrystalline structure.

  The first insulating layers 104 to 106 are filled with an insulating material between the plurality of first conductive layers 102 and 103 by a droplet discharge method, an inkjet method, a spin coat method, a roll coat method, a slot coat method, or the like. Form. In the case of using a droplet discharge method, an inkjet method, or the like as a formation method, the material of the first insulating layer is discharged to a predetermined place. When using a spin coat method, a roll coat method, a slot coat method or the like, a part (upper part) of the first conductive layer is exposed by appropriately adjusting the viscosity, surface tension, etc. of the first material. To form.

Typical examples of the material of the first insulating layers 104 to 106 include polyimide, acrylic, novolac resin, melamine resin, phenol resin, epoxy resin, silicon resin, furan resin, and diallyl phthalate resin. Moreover, it is represented by a solution in which fine particles of inorganic oxide are dispersed, PSG (phosphorus glass), BPSG (phosphorus boron glass), silicate-based SOG (Spin on Glass), alkoxysilicate-based SOG, polysilazane-based SOG, and polymethylsiloxane. It is also possible to use SiO ₂ having a Si—CH ₃ bond.

  Here, the shape of the first insulating layers 104 to 106 will be described with reference to FIGS. 4 and 7A. As shown in FIG. 7A, the thickness b of the first insulating layers 104 and 105 in this embodiment is smaller than the thickness a of the first conductive layer 102. Typically, the ratio b / a (b <a) between the thickness b of the first insulating layers 104 and 105 and the thickness a of the first conductive layer 102 is 0.7 or more and 1 or less. Is preferred. When the ratio of the thickness b of the first insulating layers 104 and 105 to the thickness a of the conductive layer 102 is in the above range, the unevenness of the second insulating layer to be formed later is small, and the film thickness is uniform. While improving, step coverage property increases. Therefore, a semiconductor device with high breakdown voltage and low leakage current can be manufactured with high yield.

  Next, the shape of the first insulating layers 104 and 105 in contact with the first conductive layer 102 will be described with reference to FIGS. The first insulating layers 104 and 105 in FIG. 1 are denoted by 401 and 402 in FIG. 4A and denoted by 411 and 412 in FIG. 4B, respectively.

  As illustrated in FIG. 4A, the first insulating layers 401 and 402 may rise along the side surface of the first conductive layer 102. That is, the first region 403 of the first insulating layer that is in contact with the first conductive layer 102 is raised more than the second region 404 of the first insulating layer that is not in contact with the first conductive layer 102. Yes. That is, the first insulating layers 401 and 402 are concave with respect to the surface of the substrate 101. The first insulating layers 401 and 402 having such a shape can be formed using an insulating material having a relatively low viscosity.

  On the other hand, as illustrated in FIG. 4B, the regions of the first insulating layers 411 and 412 that are in contact with the first conductive layer 102 may be recessed with respect to the side surface of the first conductive layer 102. That is, the first region 413 of the first insulating layer that is in contact with the first conductive layer 102 is depressed more than the second region 414 of the first insulating layer that is not in contact with the first conductive layer 102. Yes. That is, the first insulating layers 411 and 412 are convex with respect to the substrate 101 side. The first insulating layers 411 and 412 having such shapes can be formed using an insulating material having a relatively high viscosity.

  Next, as illustrated in FIG. 1B, a second insulating layer 121 functioning as a gate insulating layer over the first conductive layers 102 and 103 and the first insulating layers 104 to 106, a first semiconductor layer 122, a conductive second semiconductor layer 123 is formed.

  The second insulating layer 121 is formed by a single layer or a stacked structure of insulating layers containing silicon nitride, silicon oxide, or other silicon by a thin film formation method such as a plasma CVD method or a sputtering method. The second insulating layer preferably has a stacked structure of a silicon nitride layer (silicon nitride oxide layer), a silicon oxide layer, and a silicon nitride layer (silicon nitride oxide layer) from the side in contact with the gate electrode. In this structure, since the gate electrode is in contact with the silicon nitride layer, deterioration due to oxidation can be prevented.

The second insulating layer 121 can be formed using an insulating solution by a droplet discharge method, a coating method, a sol-gel method, or the like. Representative examples of the insulating solution include a solution in which fine particles of inorganic oxide are dispersed, polyimide, polyamide, polyester, acrylic, PSG (phosphorus silicate glass), BPSG (phosphorus boron silicate glass), silicate-based SOG (Spin on Glass), alkoxysilicate SOG, polysilazane SOG, and SiO ₂ having a Si—CH ₃ bond represented by polymethylsiloxane can be used as appropriate.

  The first semiconductor layer 122 includes an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and crystal grains of 0.5 nm to 20 nm in the amorphous semiconductor. A layer having any state selected from a microcrystalline semiconductor and a crystalline semiconductor that can be observed is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc). In any case, a semiconductor layer having a thickness of 10 to 60 nm mainly composed of silicon, silicon germanium (SiGe), or the like can be used.

The SAS is a semiconductor having an intermediate structure between an amorphous structure and a crystal structure (including single crystal and polycrystal) and having a third state that is stable in terms of free energy. It also contains a crystalline region with short-range order and lattice distortion. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. ing. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. Further, as a neutralizing agent for dangling bonds, SAS contains 1 atomic% or more of hydrogen or halogen.

SAS can be obtained by glow discharge decomposition of a silicide gas. A typical silicide gas is SiH ₄ , and in addition, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4 and the} like can be used. By forming a silicide gas diluted with hydrogen or fluorine, or hydrogen or fluorine and one or more kinds of rare gas elements selected from helium, argon, krypton, and neon, the formation of SAS is facilitated. be able to. At this time, it is preferable to dilute the silicide gas so that the dilution rate is in the range of 10 to 1000 times. Further, the SAS can be formed by using Si ₂ H ₆ and GeF ₄ and diluting with helium gas. The reaction generation of the coating by glow discharge decomposition is preferably performed under reduced pressure, and the pressure may be in the range of about 0.1 Pa to 133 Pa. The power for forming the glow discharge may be high frequency power of 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or less, and a substrate heating temperature of 100 to 250 ° C. is recommended.

The crystalline semiconductor layer can be formed by crystallizing an amorphous semiconductor layer or SAS by heating or laser irradiation. Alternatively, a crystalline semiconductor layer may be formed directly. In this case, a crystalline semiconductor layer is directly formed using heat or plasma using a fluorine-based gas such as GeF ₄ or F ₂ and a silane-based gas such as SiH ₄ or Si ₂ H _6. Can do.

  The second semiconductor layer 123 has conductivity. In the case of forming an n-channel TFT, a Group 15 element, typically phosphorus or arsenic is added. In the case of forming a p-channel TFT, an element belonging to Group 13, typically boron, is added. The second semiconductor layer is formed by a plasma CVD method in which a gas containing a group 13 or group 15 element such as boron, phosphorus, or arsenic is added to a silicide gas. In addition, after forming the semiconductor layer, a solution containing an element belonging to Group 13 or 15 can be applied to the semiconductor layer and irradiated with a laser beam to form a conductive second semiconductor layer. As the laser beam, a laser beam emitted from a known pulsed laser or continuous wave laser is appropriately used.

  Next, as illustrated in FIG. 1C, first mask patterns 131 to 134 are formed over the second semiconductor layer 123. The first mask pattern is preferably formed by using a heat-resistant polymer material, and a polymer having an aromatic ring and a heterocyclic ring as a main chain and a small amount of an aliphatic portion and a highly polar hetero atom group is dropped. It is preferable to form by discharging by a discharging method. Typical examples of such a polymer substance include polyimide and polybenzimidazole. In the case of using polyimide, a solution containing polyimide can be discharged from the discharge port onto the second semiconductor layer 123 and baked at 200 ° C. for 30 minutes.

  The first mask pattern can be formed by forming a mask pattern having a liquid repellent surface in advance and applying or discharging a polymer material to a region not covered with the liquid repellent surface.

  Next, the second semiconductor layer 123 is etched using the first mask patterns 131 to 134 to form first semiconductor regions (also referred to as a source region, a drain region, and a contact layer) 135 to 138. Thereafter, the first mask pattern is removed.

The second semiconductor _{layer, Cl 2, BCl 3, SiCl} 4 or a chlorine-based gas typified by _{CCl 4, CF 4, SF 6} , NF 3, fluorine-based gas CHF ₃ and the like as a representative or O _2, Can be used for etching.

  Next, as shown in FIG. 1D, second mask patterns 141 and 142 are formed on the substrate. The second mask pattern can be formed using the same material as the first mask pattern.

  Next, using the second mask patterns 141 and 142 as a mask, the first semiconductor layer 122 is etched to form second semiconductor regions (channel formation regions) 143 and 144. The etching conditions for the second semiconductor layer can be applied to the etching conditions for the first semiconductor layer. Thereafter, the second mask pattern is removed by a process using a stripping solution or an ashing process using oxygen.

  FIG. 39A is an enlarged view of the vicinity of the second semiconductor region 143 and the first conductive layer 102 at this time.

  FIG. 39A shows a region where the first conductive layer 102 and the first insulating layers 104 and 105, the second insulating layer 121, and the second semiconductor region 143 filling the outside are formed. The second semiconductor region 143 includes a region 161 that overlaps the first conductive layer 102 and the second insulating layer 121, the first conductive layer 102, the first insulating layers 104 and 105, and the second insulating layer. And a region 162 on which 121 is superimposed.

  That is, the gate insulating layer of the TFT of the present invention has a region formed of one insulating layer and a region formed of two insulating layers.

  Note that as illustrated in FIG. 1D, the second semiconductor regions 143 and 144 can be formed using an organic semiconductor material by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. The organic semiconductor material used in the present invention is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Typically, a soluble polymer material such as polythiophene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

  In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a first semiconductor region by processing after forming a soluble precursor. Examples of the organic semiconductor material that passes through such a precursor include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

  When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2) -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

  In the case where an organic semiconductor is used for the second semiconductor regions 143 and 144, instead of the first semiconductor regions 135 to 138, polyacetylene, polyaniline, PEDOT (poly-ethylenedioxythiophene), PSS (poly-styrenesulphonate), or the like is used. A conductive layer formed of an organic conductive material can be formed. The conductive layer functions as a contact layer or a source region and a drain region.

  Further, a conductive layer formed of a metal element can be used instead of the first semiconductor regions 135 to 138. In this case, since a material that transports charges in many organic semiconductor materials is a p-type semiconductor that transports holes as carriers, it is desirable to use a metal having a high work function in order to make ohmic contact with the semiconductor layer.

  Specifically, metals or alloys such as gold, platinum, chromium, palladium, aluminum, indium, molybdenum, and nickel are desirable. It can be formed by a printing method, a roll coater method, or a droplet discharge method using a conductive paste using these metals or alloy materials.

  Furthermore, a second semiconductor region formed of an organic semiconductor material, a conductive layer formed of an organic conductive material, and a conductive layer formed of a metal element may be stacked.

  Note that in the case where the second semiconductor region is formed of SAS, in addition to the structure in which the source region and the drain region cover the gate electrode as in the present embodiment, the end portions of the source region and the drain region A so-called self-aligned structure in which the end portions of the gate electrodes coincide can be obtained. Furthermore, a structure in which the source region and the drain region are formed at a certain distance without covering the gate electrode can be employed. In this structure, off-state current can be reduced, so that contrast can be improved when the TFT is used as a switching element of a display device. Furthermore, a TFT having a so-called multi-gate structure in which the second semiconductor region covers a plurality of gate electrodes may be used. Also in this case, reduction of off-state current can be increased.

  Next, as illustrated in FIG. 1E, source and drain electrodes 151 to 154 are formed over the first semiconductor regions 135 to 138 using a conductive material. The source electrode and the drain electrode can be formed using a material and a formation method similar to those of the first conductive layer. Here, a solution Ag paste in which silver particles of several nm are dispersed is selectively discharged and dried to form the source and drain electrodes 151 to 154.

  Next, it is preferable to form a passivation layer over the source and drain electrodes 151 to 154. The passivation layer is formed by a thin film formation method such as a plasma CVD method or a sputtering method. Silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), carbon nitride ( CN) and other insulating materials.

  Through the above steps, a channel-etched TFT with high breakdown voltage and suppressed leakage current can be formed with high yield.

(Embodiment 2)
In this embodiment, a manufacturing process of a semiconductor device in which the thickness of the first insulating layer is larger than that of the first conductive layer in Embodiment 1 will be described with reference to FIGS. B). In this embodiment mode, description is made using a channel-etched TFT as a bottom gate TFT as a semiconductor device.

  As shown in FIG. 2A, first conductive layers 102 and 103 are formed over a substrate 101 as in Embodiment Mode 1. Next, first insulating layers 204 to 206 are formed. The thickness of the first insulating layers 204 to 206 is thicker than the thickness of the first conductive layers 102 and 103, and covers the first conductive layer side and part of the upper portion.

  The first insulating layers 204 to 206 can be formed using a material and a formation method similar to those of the first insulating layers 104 to 106 in Embodiment 1.

  Next, as illustrated in FIG. 2B, a second insulating layer 221, a first semiconductor layer 122, and a conductive second semiconductor layer 123 are sequentially formed as in Embodiment Mode 1. Note that the second insulating layer 221 can be formed using a material and a formation method similar to those of the second insulating layer 121 in Embodiment 1.

  Here, the thicknesses of the first insulating layers 204 to 206 and the second insulating layer 221 are described with reference to FIG. As shown in FIG. 7B, the thickness b of the first insulating layer is larger than the thickness a of the first conductive layer. For this reason, the 1st insulating layer has covered a part of side and upper part of the 1st conductive layer. The thickness of the first insulating layer that is thicker than the thickness of the first conductive layer, that is, the thickness difference b−a between the first insulating layer and the first conductive layer is greater than the thickness c of the second insulating layer. Is also preferably thin. That is, it is preferable to satisfy the relationship of 0 <thickness difference (ba) <c (b> a). When the thickness of the first insulating layers 204 to 206, the thickness of the first conductive layer, and the thickness of the second insulating layer are in the above ranges, the second insulating layer has less unevenness and the film thickness As a result, the step coverage is improved. Therefore, a semiconductor device with high breakdown voltage and low leakage current can be manufactured with high yield.

  After that, as shown in FIGS. 2C to 2E, first semiconductor regions 135 to 138 functioning as a source region and a drain region and a channel formation region are formed by the same process as in the first embodiment. The functioning second semiconductor regions 143 and 144 and the source and drain electrodes 151 to 154 can be formed.

  Here, an enlarged view of the vicinity of the second semiconductor region 143 and the first conductive layer 102 is illustrated in FIG.

  In FIG. 39B, the first conductive layer 102, the first insulating layers 204 and 205, the second insulating layer 221, and the second semiconductor region 143 filling the outside are formed. The second semiconductor region 143 includes a region 261 that overlaps the first conductive layer 102 and the second insulating layer 221, the first conductive layer 102, the first insulating layers 204 and 205, and a second insulating layer. The region 262 overlaps with the layer 221.

  That is, the gate insulating layer of the TFT of the present invention has a region formed of one insulating layer and a region formed of two insulating layers. In addition, the second semiconductor region (channel formation region) of the TFT of this embodiment is concave with respect to the substrate surface.

  Through the above steps, a channel-etched TFT with high breakdown voltage and suppressed leakage current can be formed with high yield.

(Embodiment 3)
Here, the shape of the first conductive layers 102 and 103 which can be applied to the present invention in Embodiment Mode 1 or Embodiment Mode 2 will be described with reference to FIGS. This embodiment will be described using Embodiment 2. Note that Embodiment 1 can be used as appropriate.

As shown in FIG. 3A, after the conductive layer 301 having an inclined portion (taper) whose contact angle θ ₁ with the substrate 101 is 70 to 90 degrees at the end, that is, the conductive layer 301 having a trapezoidal cross section, is formed. First insulating layers 204 and 205 are formed. Conventionally, when a film is formed on a film pattern having a contact angle θ ₁ of 70 degrees or more, there is a problem that the step coverage of the film decreases as the contact angle increases, and step breakage occurs. However, by forming the first insulating layers 204 and 205, it is possible to prevent disconnection of a film to be formed later, and to improve the uniformity of the film thickness. The conductive layer 301 having such a shape can be formed by etching a film by a dry etching method using a mask pattern formed by a known photolithography process.

As shown in FIG. 3B, a conductive layer 311 having a contact angle θ ₂ with the substrate 101 of 90 degrees at the lower end portion and an inclined portion or a curvature portion 312 at the upper end portion is formed. Next, first insulating layers 204 and 205 are formed. In FIG. 3B, a conductive layer having a curvature portion 312 is shown. Conventionally, when a film is formed on a film pattern with a contact angle θ of 90 degrees, there is a problem that the step coverage of the film is lowered and step breakage occurs. However, by forming the first insulating layers 204 and 205, it is possible to prevent disconnection of a film to be formed later, and to improve the uniformity of the film thickness. The conductive layer having such a shape can be formed by discharging droplets by a droplet discharge method, an ink jet method, or the like, and performing drying and baking.

As shown in FIG. 3 (C), a contact angle theta ₃ is 90 degrees to the substrate 101 at the lower end, and an angle theta ₄ also conductive layer is 90 degrees at the upper end, i.e. cross-section rectangular A conductive layer 321 is formed. Next, first insulating layers 204 and 205 are formed. Conventionally, when a film is formed on a rectangular film pattern, there is a problem that the step coverage of the film is deteriorated and disconnection occurs. However, by forming the first insulating layers 204 and 205, it is possible to prevent disconnection of a film to be formed later, and to improve the uniformity of the film thickness. The conductive layer 321 having such a shape can be formed by etching a film by a dry etching method using a mask pattern formed by a known photolithography process. Further, a printing method, an electroplating method, or the like can be used.

As shown in FIG. 3D, a conductive layer 331 having a contact angle θ ₅ with the substrate 101 of 90 ° or more and 135 ° or less at the end, that is, a reverse tapered portion is formed. Next, first insulating layers 204 and 205 are formed. Conventionally, when a film is formed on a film pattern having a contact angle θ of 90 degrees or more, the lower end is covered with the upper end, and it is difficult to form a film near the lower end. There was a problem that the coatability was lowered and breakage occurred. However, by forming the first insulating layers 204 and 205, it is possible to prevent disconnection of a film to be formed later, and to improve the uniformity of the film thickness.

  As shown in FIG. 3E, a conductive layer 341 which is depressed on the side surface of the conductive layer, that is, has a recess 342 is formed. Next, first insulating layers 204 and 205 are formed. Conventionally, when a film is formed on a film pattern having a depression, the film pattern has severe irregularities, the uniformity of the film thickness is low, and disconnection occurs. However, by forming the first insulating layers 204 and 205, it is possible to prevent disconnection of a film to be formed later, and to improve the uniformity of the film thickness. The conductive layer having such a shape can be formed by etching a film by a wet etching method using a mask pattern formed by a known photolithography process.

  In the present invention, TFTs using conductive layers with various shapes can be formed as described above, and the application range of a manufacturing method can be expanded.

(Embodiment 4)
In this embodiment mode, a manufacturing process of a channel protection type TFT in the bottom gate TFT of the present invention will be described with reference to FIGS. Note that the first insulating layer is formed using Embodiment 1, but the present invention is not limited to this, and Embodiment 2 can be used. As the first conductive layer, the first conductive layer described in Embodiment 3 can be used as appropriate.

  As shown in FIG. 5A, first conductive layers 102 and 103 are formed over a substrate 101 using Embodiment Mode 1, and a first insulating layer is filled so as to fill a space between the first conductive layers. 104-106 are formed.

  Next, as illustrated in FIG. 5B, a second insulating layer 121 functioning as a gate insulating layer over the first conductive layers 102 and 103 and the first insulating layers 104 to 106, a first semiconductor layer 122 is formed. Next, protective layers 501 and 502 are formed over the first semiconductor layer 122 and in regions overlapping with the first conductive layers 102 and 103. As a formation method and a material of the protective layers 501 and 502, the same methods as the first mask patterns 131 to 134 described in Embodiment Mode 1 can be used.

  Next, a second semiconductor layer (a semiconductor layer having conductivity) 523 is formed. Note that the second semiconductor layer 523 can be formed using a material and a manufacturing method similar to those of the second semiconductor layer 123 of Embodiment 1.

  Next, as shown in FIG. 5C, first mask patterns 531 and 532 are formed. The first mask patterns 531 and 532 are formed using the same material and formation method as the second mask patterns 141 and 142 of the first embodiment.

  Next, the first semiconductor layer and the second semiconductor layer are etched using the first mask pattern, so that first semiconductor regions 533 and 534 and second semiconductor regions 543 and 544 are formed. Thereafter, the first mask pattern is removed.

  Next, as illustrated in FIG. 5D, source and drain electrodes 551 to 554 are formed over the first semiconductor regions 533 and 534.

  Next, using the source and drain electrodes 551 to 554 as a mask, the exposed portions of the first semiconductor regions 533 and 534 are etched and divided to form source and drain regions 535 to 538. Through this step, the protective layers 501 and 502 are exposed.

  Note that the method for forming the source region and the drain region is not limited to this embodiment mode, and the manufacturing process of the first semiconductor region described in Embodiment Mode 1 may be used. Further, the formation process of the source region and the drain region of this embodiment may be applied to Embodiment 1.

  Through the above steps, a channel protection type TFT with high breakdown voltage and suppressed leakage current can be formed with high yield.

(Embodiment 5)
In this embodiment mode, a manufacturing process of a forward staggered TFT among the top gate TFTs of the present invention will be described with reference to FIGS. Note that the first insulating layer is formed using Embodiment 1, but the present invention is not limited to this, and Embodiment 2 can be used. As the first conductive layer, the first conductive layer described in Embodiment 3 can be used as appropriate.

  As shown in FIG. 6A, first conductive layers 601 and 602 that function as a source electrode and a drain electrode are formed over a substrate 101. As this material and a manufacturing method, a material similar to that of the first conductive layers 102 and 103 in Embodiment 1 can be used as appropriate. Next, a first semiconductor layer 603 having conductivity is formed over the first conductive layer. For the first semiconductor layer 603, a material and a manufacturing method similar to those of the second semiconductor layer 123 in Embodiment 1 are used as appropriate. Next, first mask patterns 604 and 605 are formed over the first semiconductor layer 603. Since the first mask pattern is used as a mask for forming the source region and the drain region, the same material and formation process as those of the first mask patterns 131 to 134 of Embodiment 1 are used as appropriate.

  Next, as shown in FIG. 6B, the first semiconductor layer is etched using the first mask pattern to form first semiconductor regions 611 and 612. The first semiconductor region functions as a source region and a drain region. Note that as the first semiconductor region, a material and a manufacturing method similar to those of the first semiconductor regions 135 to 138 of Embodiment 1 can be used as appropriate.

  Next, first insulating layers 613 to 615 are formed between the stacked first conductive layers 601 and 602 and the first semiconductor region. For the first insulating layers 613 to 615, a material and a manufacturing process similar to those of the first insulating layers 104 to 106 in Embodiment 1 are used as appropriate.

  Next, as illustrated in FIG. 6C, the second semiconductor layer 621 is formed over the first insulating layers 613 to 615, the first conductive layers 601 and 602, and the first semiconductor regions 611 and 612. To do. For the second semiconductor layer 621, a material and a manufacturing method similar to those of the first semiconductor layer 122 in Embodiment 1 are used as appropriate.

  Next, a second film pattern 622 is formed over the second semiconductor layer 621. The second film pattern is a mask for forming a channel formation region, and materials and manufacturing steps similar to those of the second mask patterns 141 and 142 of Embodiment 1 are used as appropriate.

  Next, as shown in FIG. 6D, the second semiconductor film 621 is etched using the second film pattern 622 to form a second semiconductor region 631. The second semiconductor region functions as a channel formation region.

  Next, a second insulating layer 632 and a second conductive layer 633 are formed. Since the second insulating layer 632 functions as a gate insulating layer, the second insulating layer 632 is formed using a material and a formation process similar to those of the second insulating layer 121 in Embodiment 1. In addition, since the second conductive layer 633 functions as a gate electrode, the second conductive layer 633 is formed using a material and a method similar to those of the first conductive layers 102 and 103 in Embodiment 1.

  Through the above steps, a forward staggered TFT with high breakdown voltage and suppressed leakage current can be formed with high yield.

(Embodiment 6)
In this embodiment mode, a method for forming a TFT contact hole is described with reference to FIGS.

  A staggered TFT as shown in FIG. 38A is formed in accordance with Embodiment Mode 5. Here, the first conductive layers 601 and 602, the first insulating layers 613 to 615, the conductive first semiconductor regions 611 and 612, the second semiconductor region 631, and the second insulating layer are formed over the substrate 101. A layer 632 and a second conductive layer 633 are included. Thereafter, a protective layer 715 is formed so as to cover the TFT. Note that the first semiconductor region functions as a source region and a drain region, and the second semiconductor region functions as a channel formation region.

  Next, as illustrated in FIG. 38B, the first conductive layers 601 and 602, the second insulating layer 632, the protective layer 715, the first semiconductor region, and the second semiconductor region overlap with each other. Then, the first mask pattern 751 is formed by discharging a solution that forms the liquid repellent surface.

  The region having a liquid repellent surface is a region having a high surface contact angle with respect to the liquid. On this surface the liquid is repelled and becomes hemispherical. On the other hand, the region having the lyophilic surface is a region having a low surface contact angle with respect to the liquid. On this surface, the liquid spreads and spreads.

  For this reason, when two regions having different contact angles are in contact with each other, a region having a relatively high contact angle is a region having a lyophobic surface, and a region having a lower contact angle is a region having a lyophilic surface. When the solution is applied or discharged to these two regions, the solution spreads on the surface of the region having the lyophilic surface and is repelled at the interface with the region having the liquid repellent surface to become a hemisphere.

  When the surface has irregularities, the contact angle is further increased in the region having the liquid repellent surface. That is, the liquid repellency is increased. On the other hand, the contact angle is further reduced in the region having the lyophilic surface. That is, lyophilicity is increased. For this reason, the layer which has the edge part of each area | region uniform can be formed by apply | coating or discharging the solution which has a composition on each uneven surface, and baking.

Here, a material having a liquid repellent surface is applied or discharged to form a region having the liquid repellent surface. As an example of the material of the solution that forms the liquid repellent surface, a silane coupling agent represented by a chemical formula of Rn—Si—X _(4-n) (n = 1, 2, 3) is used. Here, R is a substance containing a relatively inert group such as an alkyl group. X is a hydrolyzable group such as halogen, methoxy group, ethoxy group or acetoxy group, which can be bonded by condensation with a hydroxyl group on the substrate surface or adsorbed water.

Further, as a typical example of the silane coupling agent, by using a fluorine-based silane coupling agent (fluoroalkylsilane (FAS)) having a fluoroalkyl group in R, liquid repellency can be further improved. R of FAS has a structure represented by (CF ₃ ) (CF ₂ ) _x (CH ₂ ) _y (x: an integer of 0 or more and 10 or less, y: an integer of 0 or more and 4 or less), and a plurality of R Alternatively, when X is bonded to Si, R and X may all be the same or different. Typical FAS includes fluoroalkylsilanes such as heptadecafluorotetrahydrodecyltriethoxysilane, heptadecafluorotetrahydrodecyltrichlorosilane, tridecafluorotetrahydrooctyltrichlorosilane, and trifluoropropyltrimethoxysilane.

  Solvents for forming the water repellent surface include n-pentane, n-hexane, n-heptane, n-octane, n-decane, dicyclopentane, benzene, toluene, xylene, durene, indene, tetrahydronaphthalene, decahydro. Examples thereof include hydrocarbon solvents such as naphthalene and squalane, or tetrahydrofuran.

  In addition, as an example of the material of the solution that forms the liquid repellent surface, a material having a fluorocarbon chain (fluorine resin) can be used. Examples of the fluorine resin include polytetrafluoroethylene (PTFE; tetrafluoroethylene resin), perfluoroalkoxyalkane (PFA; tetrafluoroethylene perfluoroalkyl vinyl ether copolymer resin), and perfluoroethylene propylene copolymer (PFEP; four fluorine). Ethylene-hexafluoropropylene copolymer resin), ethylene-tetrafluoroethylene copolymer (ETFE; tetrafluoroethylene-ethylene copolymer resin), polyvinylidene fluoride (PVDF; vinylidene fluoride resin), polychlorotrifluoroethylene (PCTFE; trifluoroethylene chloride resin), ethylene-chlorotrifluoroethylene copolymer (ECTFE; trifluoroethylene chloride-ethylene copolymer resin), polytetrafluoroethylene-perfluorodiode Sole copolymer (TFE / PDD), polyvinyl fluoride (PVF; a vinyl fluoride resin), or the like can be used.

  Subsequently, when the surface to which the solution forming the liquid repellent surface is attached is washed with ethanol, an extremely thin liquid repellent surface can be formed.

Further, an organic material that does not form a liquid repellent surface (that is, forms a lyophilic surface) as a mask pattern may be used to form a liquid repellent surface by subsequent treatment with CF ₄ plasma or the like. For example, a material in which a water-soluble resin such as polyvinyl alcohol (PVA) is mixed with a solvent such as H ₂ O as an organic substance can be used. Moreover, you may use combining PVA and another water-soluble resin. Furthermore, even when the mask pattern has a liquid repellent surface, the liquid repellency can be further improved by performing the plasma treatment or the like.

Alternatively, plasma treatment can be performed by preparing an electrode provided with a dielectric and generating plasma so that the dielectric is exposed to plasma using air, oxygen, or nitrogen. In this case, the dielectric need not cover the entire electrode surface. As the dielectric, a fluorine-based resin can be used. In the case of using a fluorine-based resin, surface modification is performed by forming CF ₂ bonds on the surface to be formed, and liquid repellency is exhibited. Plasma treatment is also performed.

  Next, a second mask pattern 752 is formed by discharging a solution that forms the lyophilic surface. Typical examples of lyophilic solutions include acrylic resin, polyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), furan resin, diallyl phthalate An organic resin such as a resin, siloxane, or polysilazane can be used. Alternatively, a solution using a polar solvent such as water, alcohol, ether, dimethylformamide, dimethylacetamide, dimethylsulfoxide, N-methylpyrrolidone, hexamethylphosphamide, chloroform, methylene chloride or the like can be used. As a method for forming the second mask pattern, a droplet discharge method, an inkjet method, a spin coating method, a roll coating method, a slot coating method, or the like can be applied.

  Since the first mask pattern 751 has a liquid repellent surface, the second mask pattern 752 is formed in the outer edge of the first mask pattern, that is, in a region where the first mask pattern is not formed.

  Note that, instead of the above step, the second mask pattern may be formed by applying the second solution after drying the solvent of the first mask pattern. By these steps, an extremely thin liquid repellent surface can be formed.

  Next, as illustrated in FIG. 38C, the first mask pattern 751, the protective layer 715, and the second insulating layer 632 are etched using the second mask pattern 752 as a mask, so that the second semiconductor region 631 is etched. To expose a part of

  Next, as shown in FIG. 38D, after the second mask pattern 752 is removed, a third conductive layer 764 is formed. The third conductive layer 764 functions as a source wiring layer and a drain wiring layer.

  Note that as shown in FIG. 38E, the second conductive pattern 764 can be formed using the second mask pattern 752 as an interlayer insulating layer without being removed.

  Through the above steps, a contact hole can be formed without using a photomask.

(Embodiment 7)
In this embodiment mode, a droplet discharge apparatus that can be used for film pattern formation in the above embodiment mode will be described. In FIG. 8, a region where one panel 1930 is formed on the substrate 1900 is indicated by a broken line.

  FIG. 8 shows one mode of a droplet discharge device used for forming a pattern such as a wiring. The droplet discharge means 1905 has a head, and the head has a plurality of nozzles. In this embodiment, a case where three heads (1903a, 1903b, and 1903c) having ten nozzles are described will be described. However, the number of nozzles and the number of heads are set according to a processing area, a process, and the like. Can do.

  The head is connected to the control means 1907, and the control means controls the computer 1910 to draw a preset pattern. The drawing timing may be performed using, for example, the marker 1911 formed on the substrate 1900 fixed on the stage 1931 as a reference point. Further, the edge of the substrate 1900 may be used as a reference point. These reference points are detected by an imaging means 1904 such as a CCD, and converted into a digital signal by an image processing means 1909. The computer 1910 recognizes the digitally changed signal, generates a control signal, and sends it to the control means 1907. When drawing a pattern in this way, the distance between the pattern forming surface and the tip of the nozzle is 0.1 cm to 5 cm, preferably 0.1 cm to 2 cm, and more preferably about 0.1 cm. By shortening the interval in this way, droplet landing accuracy is improved.

  At this time, information on the pattern formed on the substrate 1900 is stored in the storage medium 1908. Based on this information, a control signal is sent to the control means 1907, and each head 1903a, 1903b, 1903c is individually controlled. be able to. That is, different compositions can be discharged from the nozzles of the heads 1903a, 1903b, and 1903c. For example, the nozzles of the heads 1903a and 1903b can discharge a composition having an insulating layer material, and the nozzles of the head 1903c can discharge a composition having a conductive layer material.

  Furthermore, each nozzle of the head can be individually controlled. Since the nozzles can be individually controlled, different compositions can be discharged from a specific nozzle. For example, the same head 1903a can be provided with a nozzle for discharging a composition having a conductive layer material and a nozzle for discharging a composition having an insulating layer material.

  The nozzle is connected to a tank filled with the composition.

  Further, in the case where a droplet discharge process is performed on a large area as in the step of forming an interlayer insulating layer, a composition including an interlayer insulating layer material is preferably discharged from all nozzles. Further, a composition having an interlayer insulating layer material may be discharged from all nozzles of a plurality of heads. As a result, throughput can be improved. Needless to say, in the interlayer insulating layer forming step, a droplet discharge treatment may be performed on a large area by discharging a composition having an interlayer insulating layer material from one nozzle and scanning a plurality of times.

  Then, the pattern can be formed on the large mother glass by zigzaging or reciprocating the head. At this time, the head and the substrate may be scanned relatively a plurality of times. When scanning the head with respect to the substrate, the head may be inclined obliquely with respect to the traveling direction.

  In the case where a plurality of panels are formed from a large mother glass, the width of the head is preferably about the same as the width of one panel. This is because a pattern can be formed in one scan with respect to a region where one panel 1930 is formed, and high throughput can be expected.

  Further, the width of the head may be smaller than the width of the panel. At this time, a plurality of small heads may be arranged in series so as to be approximately the same as the width of one panel. By arranging a plurality of small heads in series, it is possible to prevent the occurrence of head deflection, which is a concern as the head width increases. Of course, the pattern may be formed by scanning a narrow head a plurality of times.

  The step of discharging the composition droplets by such a droplet discharge method is preferably performed under reduced pressure. This is because the solvent of the composition evaporates and the steps of drying and firing the composition can be omitted before the composition is discharged and landed on the object to be processed. Further, it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductor. The step of dropping the solution may be performed in a nitrogen atmosphere or an organic gas atmosphere.

A piezo method can be used as a droplet discharge method. The piezo method is also used in inkjet printers because of its excellent droplet controllability and high degree of freedom in ink selection. The piezo method includes a vendor type (typically MLP (Multi Layer Piezo) type), a piston type (typically MLChip (Multi Layer Ceramic Hyper Integrated Segments) type), a sidewall type, and a roof. There is a wall type. Further, depending on the solvent of the solution, a droplet discharge method using a thermal method in which the heating element generates heat to generate bubbles to push out the solution may be used.

  Next, a method for manufacturing an active matrix substrate and a display panel having the active matrix substrate will be described with reference to FIGS. In this embodiment, a liquid crystal display panel is used as the display panel. 17 to 19 schematically show the longitudinal cross-sectional structures of the pixel portion and the connection terminal portion, and the planar structures corresponding to AB and CD are shown in FIGS. In this example, the first insulating layer is formed using the first embodiment, but the present invention is not limited to this, and the second embodiment can be used. As the gate wiring layer, the gate electrode layer, and the connection conductive layer, the first conductive layer described in Embodiment 3 can be used as appropriate.

  As shown in FIG. 17A, the surface of the substrate 800 is oxidized at 400 degrees to form an insulating layer 801 having a thickness of 100 nm. This insulating layer functions as an etching stopper for a conductive layer to be formed later. Next, a first conductive layer is formed over the insulating layer 801, and a first mask pattern is formed over the first conductive layer by a droplet discharge method. As the substrate, an AN100 glass substrate manufactured by Asahi Glass Co., Ltd. is used, and as the first conductive layer, a tungsten layer having a thickness of 100 nm is formed by a sputtering method using a tungsten target and an argon gas. For the first mask pattern, polyimide is discharged by a droplet discharge method, and is heated and baked at 200 degrees for 30 minutes. The first mask pattern is discharged onto a gate wiring layer, a gate electrode layer, and a connection conductive layer that are formed later.

  Next, part of the first conductive layer is etched using the first mask pattern, so that the gate wiring layer 803, the gate electrode layer 804, and the connection conductive layer 805 are formed. Here, the first conductive layer having a taper portion of 70 to 90 degrees is formed. Thereafter, the first mask pattern is peeled using a peeling solution. Note that FIG. 17A schematically shows a longitudinal cross-sectional structure, and FIG. 20 shows a planar structure corresponding to AB and CD after the first mask pattern is removed.

  Next, first insulating layers 806 to 809 are formed so as to fill a space between the gate wiring layer 803, the gate electrode layer 804, and the connection conductive layer 805. Here, the first insulating layer is formed by discharging polyimide by a droplet discharge method.

Next, as illustrated in FIG. 17B, a gate insulating layer 814 is formed by a plasma CVD method. As the gate insulating layer 814, a silicon oxynitride layer having a thickness of 110 nm is formed by a plasma CVD method using SiH ₄ and N ₂ O (flow rate ratio SiH ₄ : N ₂ O = 1: 200) in a chamber heated at 400 degrees. (H: 1.8%, N: 2.6%, O: 63.9%, Si: 31.7%).

  Through this step, a gate insulating layer with high film thickness uniformity and high step coverage can be formed.

  Next, a first semiconductor layer 815 and an n-type second semiconductor layer 816 are formed. As the first semiconductor layer 815, an amorphous silicon layer with a thickness of 150 nm is formed by a plasma CVD method. Next, after removing the oxide layer on the surface of the amorphous silicon layer, a semi-amorphous silicon layer having a thickness of 50 nm is formed as the second semiconductor layer 816 using silane gas and phosphine gas.

  Next, second mask patterns 817 and 818 are formed over the second semiconductor layer 816. The second mask pattern is formed by discharging polyimide onto the second semiconductor layer by a droplet discharge method and heating at 200 ° C. for 30 minutes. The second mask patterns 817 and 818 are discharged onto a region where a first semiconductor region is formed later.

Next, as shown in FIG. 17C, the second semiconductor layer 816 is etched using the second mask pattern to form first semiconductor regions (source and drain regions, contact layers) 821 and 822. Form. The second semiconductor layer is etched using a mixed gas having a flow rate ratio of CF ₄ : O ₂ = 10: 9. Thereafter, the second mask patterns 817 and 818 are peeled using a peeling solution.

Next, a third mask pattern 823 that covers the first semiconductor regions 821 and 822 and the first semiconductor layer 815 formed therebetween is formed. The third mask pattern is formed by the same material and method as the second mask pattern. The first semiconductor layer 815 is etched using the third mask pattern to form a second semiconductor region 831 as shown in FIG. 17D and the gate insulating layer 814 is exposed. The first semiconductor layer has a flow ratio of CF ₄
After etching using a mixed gas of: O ₂ = 10: 9, ashing using oxygen is performed. Thereafter, the third mask pattern 823 is peeled using a peeling solution. Note that a planar structure corresponding to the longitudinal sectional structures AB and CD in FIG. 17D is shown in FIG.

  Next, as shown in FIG. 17E, a fourth mask pattern 832 is formed. The fourth mask pattern discharges a solution that forms a liquid repellent surface in a region where the gate insulating layer 814 and the connection conductive layer 805 overlap with each other by a droplet discharge method. Here, a solution in which a fluorinated silane coupling agent is dissolved in an alcohol solvent is used as a solution for forming the liquid repellent surface. The fourth mask pattern 832 is a protective layer for forming a fifth mask pattern used for forming a contact hole in a region where the drain electrode and the connection conductive layer 813 are connected later.

  Next, a fifth mask pattern 833 is formed. The fifth mask pattern is a mask for forming the first contact hole, and is formed by discharging polyimide by a droplet discharge method and heating at 200 degrees for 30 minutes. At this time, since the fourth mask pattern 832 is lyophobic and the fifth mask pattern 833 is lyophilic, the fifth mask pattern 833 is not formed in the region where the fourth mask pattern is formed. Not formed.

Next, the fourth mask pattern 832 is removed by oxygen ashing to expose part of the gate insulating layer 814. Next, part of the exposed gate insulating layer is etched using the fifth mask pattern 833. The gate insulating layer is etched using CHF ₃ . Thereafter, the fifth mask pattern is stripped by oxygen ashing and etching using a stripping solution.

  Next, as shown in FIG. 18A, second conductive layers 841 and 842 are formed by a droplet discharge method. The second conductive layer becomes a later source wiring layer and drain wiring layer. Here, the second conductive layer 841 is formed so as to be connected to the first semiconductor region 821, and the second conductive layer 842 is formed so as to be connected to the first semiconductor region 822 and the connection conductive layer 805. . The second conductive layers 841 and 842 are discharged by discharging a solution in which Ag (silver) particles are dispersed, heated at 100 ° C. for 30 minutes, and then heated at 230 ° C. for 1 hour in an atmosphere having an oxygen concentration of 10%. Bake. Note that a planar structure corresponding to the longitudinal sectional structures AB and CD of FIG. 18A is shown in FIG.

Next, the protective layer 843 is formed. As the protective layer, a silicon nitride layer with a thickness of 100 nm is formed by a sputtering method using a silicon target and argon and nitrogen (flow ratio Ar: N ₂ = 1: 1) as a sputtering gas.

  Next, as illustrated in FIG. 18B, the region where the protective layer 843 and the connection conductive layer 805 overlap, the region where the gate wiring layer and the source wiring layer are connected to the connection terminal, and the protection layer 843 overlap. After the sixth mask patterns 851 and 852 are formed in the region, an interlayer insulating layer 853 is formed. The sixth mask pattern is a mask used for forming an interlayer insulating layer to be formed later. As a sixth mask pattern, a solution for forming a liquid repellent surface (a solution obtained by dissolving a fluorine-based silane coupling agent in a solvent) is discharged, and polyimide is discharged as an interlayer insulating layer 853 by a droplet discharge method. Both discharged are baked by heating at a temperature of 30 minutes and heating at 300 ° C. for 1 hour.

  Note that as a material of the interlayer insulating layer 853, in addition to a heat-resistant organic resin such as polyimide, acrylic, polyamide, and siloxane, an inorganic material, a low dielectric constant (low-k) material, silicon oxide, silicon nitride, silicon oxynitride, Silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina, or the like can be used.

Next, as shown in FIG. 18C, a mixed gas of CF ₄ , O ₂ , and He (flow rate ratio CF ₄ :
After etching the sixth mask patterns 851 and 852 using O ₂ : He = 8: 12: 7), part of the protective layer 843 and the gate insulating layer 814 is etched to form a second contact hole. To do. In this etching step, the protective layer 843 and the gate insulating layer 814 in a region where the gate wiring layer and the source wiring layer are connected to the connection terminal are also etched.

  Next, after the third conductive layer 861 is formed, a seventh mask pattern 862 is formed. As the third conductive layer, indium tin oxide (ITO) containing silicon oxide with a thickness of 110 nm is formed by a sputtering method, and polyimide that is an eighth mask pattern is dropped into a region where a pixel electrode is to be formed later by a droplet discharge method. And then heated at 200 degrees for 30 minutes.

  In this embodiment, in order to manufacture a transmissive liquid crystal display panel, the pixel electrode is formed of ITO containing silicon oxide. Instead, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide is used. A predetermined pattern may be formed using a solution containing (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide, and the like, and the pixel electrode may be formed by baking. Further, when a reflective liquid crystal display panel is manufactured, metal particles such as Ag (silver), Au (gold), Cu (copper)), W (tungsten), and Al (aluminum) are mainly used. A solution can be used.

  Next, as shown in FIG. 18D, the third pixel electrode 871 is formed by etching the third conductive layer 861 using the seventh mask pattern. In this etching step, the third conductive layer formed in the region where the gate wiring layer and the source wiring layer are connected to the connection terminal is also etched. Thereafter, the seventh mask pattern is stripped using a stripping solution. Note that FIG. 23 shows a plan view corresponding to AB and CD in FIG.

  The first pixel electrode 871 is connected to the connection conductive layer 805 in the second contact hole. Since the connection conductive layer 805 is connected to the second conductive layer 842, the first pixel electrode 871 and the second conductive layer 842 are electrically connected. In this embodiment, the second conductive layer 842 is made of silver (Ag), and the first pixel electrode 871 is made of ITO containing silicon oxide, but these are not directly connected. Silver is not oxidized, and the drain wiring layer and the pixel electrode can be electrically connected without increasing the contact resistance.

  As another method for forming the first pixel electrode 871, a pixel electrode can be formed without an etching step by selectively dropping a solution containing a conductive material by a droplet discharge method. Further, the pixel electrode can be formed by discharging a solution having conductivity after forming a solution for forming the liquid repellent surface in a region where the pixel electrode is not formed later, using the mask pattern. In this case, the mask pattern can be removed by ashing using oxygen. Further, the mask pattern may be left without being removed.

  Through the above steps, an active matrix substrate can be formed.

  Next, as illustrated in FIG. 19A, an insulating layer is formed by a printing method or a spin coating method so as to cover the first pixel electrode 871, and an alignment film 872 is formed by rubbing. Note that the alignment film 872 can also be formed by oblique evaporation.

  Next, a closed loop sealing material 873 is formed in a peripheral region where the pixels are formed by a droplet discharge method. A liquid crystal material is dropped inside the closed loop formed by the sealant 873 by a dispenser type (dropping type).

  Here, a step of dropping the liquid crystal material is shown with reference to FIG. FIG. 25A is a perspective view of a step of dropping a liquid crystal material by a dispenser 2701, and FIG. 25B is a cross-sectional view taken along a line AB in FIG.

  A liquid crystal material 2704 is dropped or discharged from the liquid crystal dispenser 2701 so as to cover the pixel portion 2703 surrounded by the sealant 2702. The liquid crystal dispenser 2701 may be moved, or a liquid crystal layer can be formed by fixing the liquid crystal dispenser 2701 and moving the substrate 2700. Alternatively, a plurality of liquid crystal dispensers 2701 may be provided and a liquid crystal material may be dropped on a plurality of pixel portions at the same time.

  As shown in FIG. 25B, the liquid crystal material 2704 can be selectively dropped or discharged only in a region surrounded by the sealant 2702.

  Although the liquid crystal material is dropped on the pixel portion here, the substrate having the pixel portion may be attached after the liquid crystal material is dropped on the counter substrate side.

  Next, as illustrated in FIG. 19B, the counter substrate 881 provided with the alignment film 883 and the second pixel electrode (counter electrode) 882 is bonded to the substrate 800 in a vacuum, and ultraviolet curing is performed. Thus, a liquid crystal layer 884 filled with a liquid crystal material is formed.

  The sealant 873 may be mixed with a filler, and the counter substrate 881 may be formed with a color filter, a shielding layer (black matrix), or the like. Further, as a method for forming the liquid crystal layer 884, a dip method (pumping method) in which a liquid crystal material is injected using a capillary phenomenon after the counter substrate is bonded can be used instead of the dispenser method (dropping method).

  Next, as shown in FIG. 19C, when an insulating layer is formed on each end of the gate wiring layer 803 and the source wiring layer (not shown), the insulating layer is removed and then anisotropically separated. Through the conductive conductive layer 885, connection terminals (connection terminals 886 connected to the gate wiring layer and connection terminals connected to the source wiring layer are not shown) are attached. Furthermore, it is preferable that the connection portion between each wiring layer and the connection terminal is sealed with a sealing resin. With this structure, it is possible to prevent moisture from the cross section from entering the pixel portion and deteriorating. Through the above process, a liquid crystal display panel can be formed.

  Through the above process, a liquid crystal display panel can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring (gate wiring) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain or source wiring layer of the diode.

  Note that any of Embodiment Modes 1 to 7 can be applied to this example.

  In this embodiment, a method for manufacturing a light-emitting display panel as a display panel will be described with reference to FIGS. 27 to 30 schematically show the longitudinal cross-sectional structures of the pixel portion and the connection terminal portion, and FIGS. 31 to 34 show planar structures corresponding to CD and EF, respectively. 27 to 30 represent connection terminal portions, and CD and EF in FIGS. 27 to 34 represent switching TFTs, driving TFTs, and light emitting elements in each pixel of the pixel portion. The area | region provided is shown. In this example, the first insulating layer is formed using the first embodiment, but the present invention is not limited to this, and the second embodiment can be used. As the first conductive layer, the first conductive layer described in Embodiment 3 can be used as appropriate.

  As shown in FIG. 27A, as in Example 1, the surface of the substrate 2001 is oxidized at 400 degrees to form an insulating layer 2002 having a thickness of 100 nm. Next, first conductive layers 2003 to 2006 are formed. In this embodiment, Ag paste is discharged by a droplet discharge method, dried and fired, and then first conductive layers 2003 to 2006 are formed. Note that the first conductive layer 2003 functions as a gate wiring layer, the first conductive layers 2004 and 2006 function as a gate electrode layer, and the first conductive layer 2005 functions as a capacitor electrode layer.

  Next, first insulating layers 2007 to 2012 are formed so as to fill a space between the gate wiring layer 2003, the gate electrode layers 2004 and 2006, and the capacitor electrode layer 2005. Here, the first insulating layer is formed by discharging polyimide by a droplet discharge method.

  Next, as illustrated in FIG. 28B, the gate insulating layer 2021, the first semiconductor layer 2022, and the second semiconductor layer 2023 exhibiting n-type are formed by plasma CVD as in Example 1. First mask patterns 2024 to 2027 are formed on the second semiconductor layer on a region where a first semiconductor region is to be formed later. The first mask pattern can be formed in the same manner as the second mask patterns 817 and 818 of the first embodiment.

  Through this step, the gate insulating layer 2021 having high uniformity in film thickness and high step coverage can be formed.

  Next, as in Example 1, the second semiconductor layer 2023 is etched using the first mask pattern to form first semiconductor regions 2031 to 2034 as shown in FIG. . Thereafter, the first mask pattern is peeled off using a peeling liquid.

  Next, second mask patterns 2035 and 2036 are formed to cover the first semiconductor regions 2031 to 2034 and the first semiconductor layer 2022 formed therebetween. Next, using the second mask pattern, the first semiconductor layer 2022 is etched to form second semiconductor regions 2041 and 2042 as shown in FIG. 28A and one of the gate insulating layers 2021. Part is exposed. Thereafter, the second mask patterns 2035 and 2036 are peeled off using a peeling solution. In addition, since the planar structure corresponding to the longitudinal cross-section structure CD and EF at this time is shown in FIG. 31, it refers simultaneously.

  Next, as in the first embodiment, third mask patterns 2043 and 2044 are formed. In the third mask pattern, a liquid repellent surface is formed by a droplet discharge method in a region where the gate insulating layer 2021 and the capacitor electrode layer 2005 overlap and a region where the gate insulating layer 2021 and the gate wiring layer 2003 overlap. Dispense the solution. Next, fourth mask patterns 2045 and 2046 are formed. The fourth mask pattern is a mask used for forming the first contact hole, and is formed by discharging polyimide by a droplet discharge method and heating at 200 degrees for 30 minutes. At this time, since the third mask patterns 2043 and 2044 are lyophobic and the fourth mask patterns 2045 and 2046 are lyophilic, the region where the third mask pattern is formed has a fourth Mask patterns 2045 and 2046 are not formed.

  Next, the third mask patterns 2043 and 2044 are removed by oxygen ashing to expose part of the gate insulating layer 2021. Next, the exposed gate insulating layer 2021 is etched using the fourth mask patterns 2045 and 2046 in the same manner as in the first embodiment. Thereafter, the fourth mask pattern is peeled off by oxygen ashing and etching using a peeling solution.

  Next, as shown in FIG. 28C, second conductive layers 2051 to 2054 are formed by a droplet discharge method. The second conductive layer becomes a later source wiring layer and drain wiring layer. Here, the second conductive layer 2051 is connected to the first semiconductor region 2031, the second conductive layer 2052 is connected to the first semiconductor region 2032 and the capacitor electrode layer 2005, and the second conductive layer 2053 is connected to the first semiconductor region 2031. The second conductive layer 2054 is connected to the first semiconductor region 2034 and is connected to the first semiconductor region 2033. Note that FIG. 32 is a plan view corresponding to CD and EF in FIG. Note that as shown in FIG. 32, the second conductive layer 2053 functions as a power supply line and a capacitor wiring.

  Through the above steps, the switching TFT 2060a, the driving TFT 2060c, the capacitor 2060b, and an active matrix substrate including them can be formed.

  Next, as shown in FIG. 29A, after the third conductive layer is formed, it is etched into a desired shape using the fifth mask pattern, so that the second conductive layer 2054 of the driving TFT 2060c is formed. A first pixel electrode 2055 to be connected is formed. As in the first embodiment, in the third conductive layer, indium tin oxide (ITO) containing silicon oxide with a thickness of 110 nm is formed and etched into a desired shape to form the first pixel electrode 2055. In this etching step, the third conductive layer formed in a region where the gate wiring layer and the source wiring layer are connected to the connection terminal may be etched.

  As another method for forming the pixel electrode, a pixel electrode can be formed without an etching step by selectively dropping a solution containing a conductive material by a droplet discharge method. Further, the pixel electrode can be formed by discharging a solution having conductivity after forming a solution for forming the liquid repellent surface in a region where the pixel electrode is not formed later, using the mask pattern. In this case, the mask pattern can be removed by ashing using oxygen. Further, the mask pattern may be left without being removed.

  Instead of this, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), and indium tin oxide containing silicon oxide are used as the material of the pixel electrode. May be.

  In this embodiment, the pixel electrode is formed of a light-transmitting conductive layer for a structure in which emitted light is emitted to the substrate 2001 side, that is, a transmissive light-emitting display panel. In the case of manufacturing a reflection type light emitting display panel that emits light on the opposite side, Ag (silver), Au (gold), Cu (copper)), W (tungsten), Al (aluminum), etc. A solution containing metal particles as a main component can be used.

  Thereafter, the fifth mask pattern is stripped using a stripping solution. Note that FIG. 33 shows a plan view corresponding to CD and EF in FIG.

  Next, a protective layer 2061 of silicon nitride or silicon nitride oxide and an insulator layer 2062 are formed over the entire surface. Next, the insulating layer 2062 is formed with an insulating layer over the entire surface by spin coating or dipping, and then openings are formed by etching, as shown in FIG. This etching is performed so that the first pixel electrode 2055 is exposed by etching the protective layer under the insulator layer. Further, if the insulator layer 2062 is formed by a droplet discharge method, etching is not necessarily required.

  The insulator layer 2062 is formed around a position where a pixel is formed corresponding to the first pixel electrode 2055. This insulator layer 2062 is made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, or acrylic acid, methacrylic acid and derivatives thereof, or polyimide, Inorganic siloxanes containing Si—O—Si bonds among silicon, oxygen and hydrogen compounds formed from aromatic polyamides, heat-resistant polymers such as polybenzimidazole, or siloxane-based materials as starting materials It can be formed of an organic siloxane insulating material in which hydrogen bonded to is substituted with an organic group such as methyl or phenyl. When an insulating layer is formed using a photosensitive or non-photosensitive material such as acrylic or polyimide, the side surface has a shape in which the radius of curvature continuously changes, and the upper thin film is preferably formed without being cut off. . The interlayer insulating layer can be formed using an insulating layer containing a color pigment, a resist, or the like. In this case, since the interlayer insulating layer functions as a light shielding layer, the contrast of a display device to be formed later is improved. Note that FIG. 34 shows a plan view corresponding to CD and EF in FIG.

  Next, as illustrated in FIG. 30A, a layer 2073 containing a light-emitting substance is formed by an evaporation method, a spin coating method, an inkjet method, or the like, and then a second pixel electrode 2074 is formed to form a light-emitting element 2075. Form. The light emitting element 2075 is connected to the driving TFT 2060c. Thereafter, a protective laminate (not shown) is formed to seal the light emitting element 2075. The protective laminate is composed of a laminate of a first inorganic insulating layer, a stress relaxation layer, and a second inorganic insulating layer.

  Note that before the layer 2073 containing a light-emitting substance is formed, heat treatment is performed at 200 ° C. under atmospheric pressure to remove moisture adsorbed in or on the insulator layer 2062. Further, heat treatment is performed at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and a layer 2073 containing a luminescent material is formed by vacuum deposition or droplet discharge under reduced pressure without being exposed to the air as it is. Is preferred.

  Further, the surface of the first pixel electrode 2055 may be exposed to oxygen plasma or may be irradiated with ultraviolet light for surface treatment.

  The layer 2073 containing a light-emitting substance is formed of a charge injecting and transporting substance containing an organic compound or an inorganic compound and a light-emitting material, and a medium molecular organic compound typified by a low molecular weight organic compound, a dendrimer, an oligomer, etc. One or a plurality of layers selected from high molecular organic compounds may be included and combined with an inorganic compound having electron injection / transport properties or hole injection / transport properties.

Among the charge injecting and transporting substances, particularly, a substance having a high electron transporting property includes, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline Examples thereof include metal complexes having a skeleton.

As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: Aromatic amine systems such as TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring— Compound having a nitrogen bond).

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transport property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, materials having a high hole injecting property include, for example, molybdenum oxide (MoO _x ), vanadium oxide (VO _x ), ruthenium oxide (RuO _x ), and tungsten oxide (WO _x ). And metal oxides such as manganese oxide (MnO _x ). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc) can be given.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, by providing a filter (colored layer) that transmits light in the emission wavelength band on the light emission side of the pixel, the color purity is improved and the pixel portion is mirrored (reflected). Prevention can be achieved. By providing the filter (colored layer), it is possible to omit a circularly polarized plate that has been considered necessary in the past, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various materials for the light emitting material forming the light emitting layer. As a low molecular weight organic light emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT) ), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] -4H-pyran, perifuranthene, 2,5- Dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq _3), 9,9'-bianthryl, 9,10-diphenyl anthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) anthracene Abbreviation: DNA), or the like can be used. Other substances may also be used.

  On the other hand, a high molecular organic light emitting material has a higher physical strength than a low molecular weight material, and can make the light emitting element highly durable. Further, since it can be formed by coating, the device can be manufactured relatively easily. The structure of a light emitting element using a high molecular weight organic light emitting material is basically the same as that of a low molecular weight organic light emitting material, and has a structure of a cathode, a layer containing a light emitting substance, and an anode. However, when forming a layer containing a light emitting material using a high molecular weight organic light emitting material, it is difficult to form a layered structure as in the case of using a low molecular weight organic light emitting material, and in many cases two layers are formed. It becomes a structure. Specifically, the structure is a cathode, a light emitting layer, a hole transport layer, and an anode.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Examples of the polyparaphenylene vinylene-based light emitting material include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2 '-Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. . Examples of the polyparaphenylene-based light emitting material include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4). -Phenylene) and the like. Polythiophene-based light-emitting materials include polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3 -Cyclohexyl-4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POP], poly [3- (4-octyl) Phenyl) -2,2bithiophene] [PTOPT] and the like. Examples of the polyfluorene-based luminescent material include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for example, Alq _3, Alq ₃ partially doped with Nile red that is a red light emitting pigment, p-EtTAZ, TPD (aromatic diamine) are sequentially stacked by a vapor deposition method Thus, white can be obtained. Moreover, when forming a light emitting layer by the apply | coating method using spin coating, after apply | coating, it is preferable to bake by vacuum heating. For example, a poly (ethylenedioxythiophene) and poly (styrenesulfonic acid) aqueous solution (PEDOT and PSS) that act as a hole injection layer are applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution is applied to the entire surface and baked to form a light emitting layer.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the layer containing the light-emitting substance listed above are examples, such as a hole injecting and transporting layer, a hole transporting layer, an electron injecting and transporting layer, an electron transporting layer, a light emitting layer, an electron blocking layer, and a hole blocking layer. A light-emitting element can be formed by appropriately stacking functional layers. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, it is possible to provide a modification with an electrode for this purpose or a dispersed light-emitting material. Can be permitted without departing from the spirit of the present invention.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved.

  Next, as illustrated in FIG. 30B, a sealant 2081 is formed and sealed with a sealing substrate 2082. After that, a connection terminal (a connection terminal 2084 connected to the gate wiring layer, a source wiring layer is connected to an end portion of each of the gate wiring layer 2003 and the source wiring layer (not shown) via an anisotropic conductive layer 2083. A connection terminal is not shown.) Furthermore, it is preferable to seal the connection portion between each wiring layer and the connection terminal with a sealing resin 2085. With this structure, moisture from the cross section can be prevented from entering and deteriorating the light emitting element.

  Through the above process, a light-emitting display panel can be manufactured. Note that a protective circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring layer (gate wiring layer) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above-described TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain wiring layer or the source wiring layer of the diode.

  Note that any of Embodiment Modes 2 to 10 can be applied to this example. Further, in the first and second embodiments, the liquid crystal display panel and the light-emitting display panel have been described as examples in the first and second embodiments, but the present invention is not limited to this, and DMD (Digital Micromirror Device) The present invention can be appropriately applied to an active display panel such as a plasma display panel (PDP), a field emission display (FED), and an electrophoretic display device (electronic paper).

  A mode of a light-emitting element applicable in the above embodiment will be described with reference to FIGS.

  FIG. 36A illustrates an example in which the first pixel electrode 11 is formed using a light-transmitting oxide conductive material. The first pixel electrode 11 is formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. Yes. A layer 16 containing a light emitting material in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked is provided thereon. The second pixel electrode 17 is formed of a first electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or MgAg and a second electrode layer 34 formed of a metal material such as aluminum. A pixel having this structure can emit light from the first pixel electrode 11 side as indicated by an arrow in the drawing.

  FIG. 36B shows an example in which light is emitted from the second pixel electrode 17, and the first pixel electrode 11 is made of a metal such as aluminum or titanium, or nitrogen at a concentration less than the stoichiometric composition ratio with the metal. And a second electrode layer 32 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. A layer 16 containing a light emitting material in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked is provided thereon. The second pixel electrode 17 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting the layer to a thickness of 100 nm or less and allowing light to pass therethrough, light can be emitted from the second electrode 17.

  Note that in the light-emitting element having the structure of FIG. 36A or FIG. 36B, when light is emitted from both directions, that is, the first electrode and the second electrode, A conductive layer having a light-transmitting property and a high work function is used, and a conductive layer having a light-transmitting property and a low work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, and the second pixel electrode 17 is formed of LiF having a thickness of 100 nm or less. Alternatively, the third electrode layer 33 containing an alkali metal or alkaline earth metal such as CaF or the like and the fourth electrode layer 34 formed of a metal material such as aluminum may be used.

  FIG. 36C shows an example in which light is emitted from the first pixel electrode 11, and a layer containing a light-emitting substance is an electron transport layer or an electron injection layer 43, a light emitting layer 42, a hole injection layer or a hole transport. A configuration in which the layers 41 are stacked in this order is shown. The second pixel electrode 17 includes a second electrode layer 32 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic% from the side of the layer 16 containing a light emitting substance, a metal such as aluminum or titanium, Alternatively, the first electrode layer 35 is formed using a metal material containing nitrogen at a concentration equal to or less than the stoichiometric composition ratio to the metal. The first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting the layer to a thickness of 100 nm or less and allowing light to pass therethrough, light can be emitted from the first pixel electrode 11.

  FIG. 36D shows an example in which light is emitted from the second pixel electrode 17, and the layer 16 containing a light-emitting substance is formed as an electron transport layer or an electron injection layer 43, a light emitting layer 42, a hole injection layer or a hole. The structure which laminated | stacked the order of the transport layer 41 is shown. The first pixel electrode 11 has a structure similar to that of the second pixel electrode 17 in FIG. 35A, and is formed to be thick enough to reflect light emitted from the layer containing a light-emitting substance. The second pixel electrode 17 is made of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In this structure, the hole injection layer 41 is made of an inorganic metal oxide (typically molybdenum oxide or vanadium oxide), so that oxygen introduced when the second electrode layer 17 is formed is supplied. Thus, the hole injection property is improved, and the driving voltage can be lowered.

  Note that in the light-emitting element having the structure of FIG. 36C or FIG. 36D, when light is emitted in both directions, that is, from the first pixel electrode and the second pixel electrode, the first pixel electrode 11 is used. In addition, a conductive layer having a light-transmitting property and a low work function is used, and a conductive layer having a light-transmitting property and a high work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF having a thickness of 100 nm or less and a metal material such as aluminum. And the second pixel electrode 17 may be formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%.

  A pixel circuit of the light-emitting display panel described in the above embodiment and an operation configuration thereof will be described with reference to FIGS. There are two types of operation configurations of the light-emitting display panel in which a video signal input to a pixel is defined by a voltage and a current is defined by a current in a display device in which a video signal is digital. There are two types of video signals defined by voltage, one having a constant voltage applied to the light emitting element (CVCV) and one having a constant current applied to the light emitting element (CVCC). In addition, a video signal is defined by current, there are a constant voltage applied to the light emitting element (CCCV) and a constant current applied to the light emitting element (CCCC). In this embodiment, a pixel performing a CVCV operation will be described with reference to FIGS. In addition, a pixel that performs the CVCC operation will be described with reference to FIGS.

  In the pixel shown in FIGS. 37A and 37B, a signal line 3710 and a power supply line 3711 are arranged in the column direction, and a scanning line 3714 is arranged in the row direction. In addition, the pixel includes a switching TFT 3701, a driving TFT 3703, a capacitor element 3702, and a light emitting element 3705.

  Note that the switching TFT 3701 and the driving TFT 3703 operate in a linear region when turned on. The driving TFT 3703 has a role of controlling whether or not a voltage is applied to the light emitting element 3705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. In this embodiment, the TFTs are formed as n-channel TFTs. The driving TFT 3703 may be a depletion type TFT as well as an enhancement type. The ratio (W / L) of the channel width W to the channel length L (W / L) of the driving TFT 3703 is preferably 1 to 1000 depending on the mobility of the TFT. The larger the W / L, the better the electrical characteristics of the TFT.

  In the pixel shown in FIGS. 37A and 37B, a TFT 3701 controls input of a video signal to the pixel. When the TFT 3701 is turned on, a video signal is input into the pixel. Then, the voltage of the video signal is held in the capacitor 3702.

  In FIG. 37A, when the power supply line 3711 is Vss and the counter electrode of the light emitting element 3705 is Vdd, that is, in FIGS. 36C and 36D, the counter electrode of the light emitting element is an anode, and the driving TFT 3703 The electrode connected to is a cathode. In this case, luminance unevenness due to characteristic variations of the driving TFT 3703 can be suppressed.

  In FIG. 37A, when the power supply line 3711 is Vdd and the counter electrode of the light emitting element 3705 is Vss, that is, in FIGS. 36A and 36B, the counter electrode of the light emitting element is a cathode, and the driving TFT 3703 The electrode connected to is the anode. In this case, when a video signal having a voltage higher than Vdd is input to the signal line 3710, the voltage of the video signal is held in the capacitor 3702, and the driving TFT 3703 operates in a linear region. It is possible to improve.

  The pixel illustrated in FIG. 37B has the same pixel structure as that illustrated in FIG. 37A except that a TFT 3706 and a scanning line 3715 are added.

  The TFT 3706 is controlled to be turned on or off by a newly arranged scanning line 3715. When the TFT 3706 is turned on, the charge held in the capacitor 3702 is discharged, and the TFT 3703 is turned off. That is, the arrangement of the TFT 3706 can forcibly create a state in which no current flows through the light emitting element 3705. Therefore, the TFT 3706 can be called an erasing TFT. Therefore, the structure in FIG. 37B can improve the light emission duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. Is possible.

  In the pixel having the above operation configuration, the current value of the light-emitting element 3705 can be determined by the driving TFT 3703 that operates in a linear region. With the above structure, variation in TFT characteristics can be suppressed, and luminance unevenness of a light-emitting element due to variation in TFT characteristics can be improved, so that a display device with improved image quality can be provided.

  Next, a pixel that performs the CVCC operation will be described with reference to FIGS. In the pixel illustrated in FIG. 37C, a power supply line 712 and a current control TFT 3704 are provided in the pixel configuration illustrated in FIG.

  The pixel shown in FIG. 37E is different from the pixel shown in FIG. 37C except that the gate electrode of the driving TFT 3703 is connected to the power supply line 3712 arranged in the row direction. It is a configuration. That is, both pixels shown in FIGS. 37C and 37E show the same equivalent circuit diagram. However, in the case where the power supply line 3712 is arranged in the column direction (FIG. 37C) and in the case where the power supply line 3712 is arranged in the row direction (FIG. 37E), each power supply line has a different layer. It is formed of a conductive layer. Here, attention is paid to the wiring to which the gate electrode of the driving TFT 3703 is connected, and FIGS. 37C and 37E are shown separately to show that the layers for producing these are different.

  Note that the switching TFT 3701 operates in a linear region, and the driving TFT 3703 operates in a saturation region. The driving TFT 3703 has a role of controlling a current value flowing through the light emitting element 3705, and the TFT 3704 has a role of operating in a saturation region and controlling supply of current to the light emitting element 3705.

  The pixels shown in FIGS. 37D and 37F are the same as those shown in FIGS. 37C and 37E, respectively, except that an erasing TFT 3706 and a scanning line 3715 are added. The pixel configuration is the same as that shown in E).

  Note that the CVCC operation can be performed also in the pixels shown in FIGS. 37A and 37B. In addition, in the pixel having the operation configuration shown in FIGS. 37C to 37F, Vdd and Vss are appropriately changed depending on the direction of current flow of the light-emitting element, as in FIGS. 37A and 37B. Is possible.

  In the pixel having the above structure, since the TFT 3704 operates in a linear region, a slight change in Vgs of the TFT 3704 does not affect the current value of the light emitting element 3705. That is, the current value of the light emitting element 3705 can be determined by the driving TFT 3703 operating in the saturation region. With the above structure, it is possible to provide a display device in which luminance unevenness of a light-emitting element due to variation in TFT characteristics is improved and image quality is improved.

  In particular, when a thin film transistor including an amorphous semiconductor or the like is formed, it is preferable to increase the area of the semiconductor layer of the driving TFT because variation in the TFT can be reduced. Thus, the pixel shown in FIGS. 37A and 37B can increase the aperture ratio because the number of TFTs is small.

  Note that although a structure including the capacitor 3702 is shown, the present invention is not limited to this, and the capacitor 3702 is not provided in the case where the capacity for holding a video signal can be covered by a gate capacitor or the like. May be.

  Further, since a threshold value of a thin film transistor formed using an amorphous semiconductor layer is easily shifted, a circuit for correcting the threshold value is preferably provided in or around the pixel.

  Such an active matrix light-emitting device is considered to be advantageous because it can be driven at a low voltage because a TFT is provided in each pixel when the pixel density is increased. On the other hand, a passive matrix light-emitting device in which a TFT is provided for each column can be formed. A passive matrix light-emitting device has a high aperture ratio because a TFT is not provided for each pixel.

  In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

  As described above, various pixel circuits can be employed.

  In this embodiment, mounting of a driver circuit (a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b) on the display panel described in the above embodiment will be described with reference to FIGS.

    As shown in FIG. 9A, a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b are mounted around the pixel portion 1401. In FIG. 9A, an IC chip 1405 is mounted on a substrate 1400 by a COG method as the signal line driver circuit 1402, the scan line driver circuits 1403a and 1403b, and the like. Then, an IC chip and an external circuit are connected via an FPC (flexible printed circuit) 1406.

  As shown in FIG. 9B, in the case where a TFT is formed using a SAS or a crystalline semiconductor, the pixel portion 1401 and the scan line driver circuits 1403a and 1403b are integrally formed over the substrate, and the signal line driver circuit 1402 and the like are formed. May be separately mounted as an IC chip. In FIG. 9B, an IC chip 1405 is mounted on a substrate 1400 as a signal line driver circuit 1402 by a COG method. Then, the IC chip and an external circuit are connected through the FPC 1406.

  Further, as shown in FIG. 9C, the signal line driver circuit 1402 and the like may be mounted by a TAB method instead of the COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. In FIG. 9C, the signal line driver circuit is mounted by the TAB method, but the scan line driver circuit may be mounted by the TAB method.

  When the IC chip is mounted by the TAB method, a pixel portion can be provided larger than the substrate, and a narrow frame can be achieved.

  The IC chip is formed using a silicon wafer, but an IC (hereinafter referred to as a driver IC) in which an IC is formed on a glass substrate may be provided instead of the IC chip. Since an IC chip is taken out from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, the driver IC has a mother substrate made of glass and has no restriction in shape, so that productivity can be improved. Therefore, the shape of the driver IC can be set freely. For example, when the length of the long side of the driver IC is 15 to 80 mm, the required number can be reduced as compared with the case where the IC chip is mounted. As a result, the number of connection terminals can be reduced, and the manufacturing yield can be improved.

  The driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiation with continuous wave laser light. A semiconductor layer obtained by irradiation with continuous wave laser light has few crystal defects and large crystal grains. As a result, a transistor having such a semiconductor layer has favorable mobility and response speed, can be driven at high speed, and is suitable for a driver IC.

  In this embodiment, a mounting method of the driver circuit (the signal line driver circuit 1402 and the scan line driver circuits 1403a and 1403b) on the display panel described in the above embodiment is described with reference to FIGS. As a mounting method, a connection method using an anisotropic conductive material, a wire bonding method, or the like may be employed, and an example thereof will be described with reference to FIG. Note that in this embodiment, an example in which a driver IC is used for the signal line driver circuit 1402 and the scanning line driver circuits 1403a and 1403b is shown. An IC chip can be appropriately used instead of the driver IC.

  FIG. 10A shows an example in which a driver IC 1703 is mounted on an active matrix substrate 1701 using an anisotropic conductive material. On the active matrix substrate 1701, wirings (not shown) such as source wirings and gate wirings and electrode pads 1702a and 1702b which are extraction electrodes of the wirings are formed.

  Connection terminals 1704a and 1704b are provided on the surface of the driver IC 1703, and a protective insulating layer 1705 is formed in the periphery thereof.

  A driver IC 1703 is fixed on the active matrix substrate 1701 with an anisotropic conductive adhesive 1706, and the connection terminals 1704a and 1704b and the electrode pads 1702a and 1702b are electrically conductive in the anisotropic conductive adhesive, respectively. They are electrically connected by a particle 1707. An anisotropic conductive adhesive is an adhesive resin in which conductive particles (having a particle size of about several to several hundred μm) are dispersed and contained, and examples thereof include an epoxy resin and a phenol resin. In addition, the conductive particles (having a particle size of about several to several hundreds of μm) are formed of one element selected from gold, silver, copper, palladium, or platinum, or alloy particles of a plurality of elements. Moreover, the particle | grains which have the multilayer structure of these elements may be sufficient. Furthermore, the particle | grains by which the resin particle was coated with one element selected from gold, silver, copper, palladium, or platinum, or an alloy of a plurality of elements may be used.

  Moreover, you may transfer and use the anisotropic conductive film formed in the film form on the base film instead of an anisotropic conductive adhesive. In the anisotropic conductive film, conductive particles similar to the anisotropic conductive adhesive are dispersed. By making the size and density of the conductive particles 1707 mixed in the anisotropic conductive adhesive 1706 suitable, the driver IC can be mounted on the active matrix substrate in such a form. This mounting method is suitable for the mounting method of the driver IC shown in FIGS. 9A and 9B.

  FIG. 10B shows an example of a mounting method using the shrinkage force of an organic resin. Buffer layers 1711a and 1711b are formed of Ta or Ti on the connection terminal surface of the driver IC, and an electroless plating method or the like is formed thereon. As a result, Au is formed to about 20 μm to form bumps 1712a and 1712b. A photo-curable insulating resin 1713 is interposed between the driver IC and the active matrix substrate, and the photo-cured insulating resin 1713 can be mounted by pressing between the electrodes. This mounting method is suitable for the mounting method of the driver IC shown in FIGS. 9A and 9B.

  Further, as shown in FIG. 10C, a driver IC 1703 is fixed to an active matrix substrate 1701 with an adhesive 1721, and connection terminals 1704a and 1704b of the CPU and electrode pads 1702a on the active matrix substrate are connected by wires 1722a and 1722b. 1702b may be connected. Then, it is sealed with an organic resin 1723. This mounting method is suitable for the mounting method of the driver IC shown in FIGS. 9A and 9B.

  10D, a driver IC 1703 may be provided through a wiring 1732 over an FPC (Flexible printed circuit) 1731 and an anisotropic conductive adhesive 1706 containing conductive particles 1707. This configuration is very effective when used for an electronic device with a limited housing size such as a portable terminal. This mounting method is suitable for the mounting method of the driver IC in FIG.

The method for mounting the driver IC is not particularly limited, and a known COG method, wire bonding method, TAB method, or reflow processing using solder bumps can be used. When performing reflow processing, the substrate used for the driver IC or active matrix substrate is a plastic with high heat resistance, typically a polyimide substrate, an HT substrate (manufactured by Nippon Steel Chemical Co., Ltd.), norbornene with a polar group. It is preferable to use ARTON made of resin (manufactured by JSR) or the like.

  In the light-emitting display panel shown in Example 6, the semiconductor layer is formed of SAS, so that the driver circuit on the scanning line side is formed over the substrate 1400 as shown in FIGS. 9B and 9C. The drive circuit in this case will be described.

FIG. 14 shows a block diagram of a scanning line side driving circuit constituted by an n-channel TFT using SAS that can obtain a field effect mobility of 1 to 15 cm ² / V · sec.

  In FIG. 14, a block denoted by 1500 corresponds to a pulse output circuit that outputs a sampling pulse for one stage, and the shift register is configured by n pulse output circuits. Pixels are connected to the ends of the buffer circuits 1501 and 1502.

  FIG. 15 shows a specific configuration of the pulse output circuit 1500, and the n-channel TFTs 3601 to 3613 constitute the circuit. At this time, the size of the TFT may be determined in consideration of the operating characteristics of the n-channel TFT using SAS. For example, if the channel length is 8 μm, the channel width can be set in the range of 10 to 80 μm.

  A specific structure of the buffer circuit 1501 is shown in FIG. Similarly, the buffer circuit includes n-channel TFTs 3621 to 3636. At this time, the size of the TFT may be determined in consideration of the operating characteristics of the n-channel TFT using SAS. For example, if the channel length is 10 μm, the channel width is set in the range of 10 to 1800 μm.

  In this embodiment, a display module will be described. Here, a liquid crystal module is shown as an example of a display module with reference to FIG.

  An active matrix substrate 1601 and a counter substrate 1602 are fixed to each other with a sealant 1600, and a pixel portion 1603 and a liquid crystal layer 1604 are provided therebetween to form a display region.

  The colored layer 1605 is necessary when performing color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizers 1606 and 1607 are disposed outside the active matrix substrate 1601 and the counter substrate 1602. In addition, a protective layer 1616 is formed on the surface of the polarizing plate 1606 so as to reduce external impact.

  A wiring board 1610 is connected to a connection terminal 1608 provided on the active matrix substrate 1601 through an FPC 1609. A pixel drive circuit (IC chip, driver IC, etc.) 1611 is provided in the FPC, and an external circuit 1612 such as a control circuit or a power supply circuit is incorporated in the wiring board 1610.

  The cold cathode tube 1613, the reflecting plate 1614, and the optical film 1615 are backlight units, which serve as light sources and project light onto the liquid crystal display panel. A liquid crystal panel, a light source, a wiring board, an FPC, and the like are held and protected by a bezel 1617.

  Note that any of Embodiment Modes 1 to 9 can be applied to this example.

  In this embodiment, a cross-sectional view of a light-emitting display module is shown as an example of a display module with reference to FIG.

  FIG. 35A illustrates a cross section of a light-emitting display module in which an active matrix substrate 1201 and a counter substrate 1202 are fixed to each other with a sealant 1200, and a display region in which a pixel portion 1203 is provided therebetween. Is forming.

  A space 1204 is formed between the counter substrate 1202 and the pixel portion 1203. The space can be filled with an inert gas such as nitrogen gas, or a light-transmitting resin having a highly water-absorbing material can be formed to further prevent moisture and oxygen from entering. Even when light from the light-emitting element is emitted to the counter substrate side with a light-transmitting resin, the light-transmitting resin can be formed without reducing transmittance.

  In order to increase the contrast, at least the pixel portion of the module may be provided with a polarizing plate or a circular polarizing plate (a polarizing plate, a 1 / 4λ plate and a 1 / 2λ plate). In the case where the display is recognized from the counter substrate 1202 side, a ¼λ plate, a ½λ plate 1205, and a polarizing plate 1206 are preferably provided in order from the counter substrate 1202. Further, an antireflection layer may be provided on the polarizing plate.

  In the case where the display is recognized from both the counter substrate 1202 and the active matrix substrate 1201, similarly, a 1 / 4λ plate, a 1 / 2λ plate, and a polarizing plate may be provided on the surface of the active matrix substrate.

  A wiring board 1210 is connected to a connection terminal 1208 provided on the active matrix substrate 1201 through an FPC 1209. A pixel driving circuit (IC chip, driver IC, etc.) 1211 is provided in the FPC or connection wiring, and an external circuit 1212 such as a control circuit or a power supply circuit is incorporated in the wiring substrate 1210.

  As shown in FIG. 35B, a colored layer 1207 can be provided between the pixel portion 1203 and the polarizing plate or between the pixel portion and the circularly polarizing plate. In this case, a full color display can be performed by providing a light emitting element capable of emitting white light in the pixel portion and separately providing a colored layer showing RGB. Further, full color display can be performed by providing a light emitting element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. In addition, each pixel portion, a light emitting element that emits red, green, and blue light can be formed, and a colored layer can be used. Such a display module has high color purity of each RBG and enables high-definition display.

  FIG. 35C shows a case where the active matrix substrate and the light-emitting element are sealed using a protective layer 1221 such as a film or a resin without using the counter substrate, unlike FIG. 35A. A protective layer 1221 is provided to cover the second pixel electrode of the pixel portion 1203. As the second protective layer, an organic material such as an epoxy resin, a urethane resin, or a silicone resin can be used. Further, the second protective layer may be formed by dropping a polymer material by a droplet discharge method. In this embodiment mode, the epoxy resin is discharged using a dispenser and dried. Further, a counter substrate may be provided over the protective layer. Other structures are similar to those in FIG.

  When sealing is performed without using the counter substrate in this manner, the weight, size, and thickness of the display device can be improved.

In the module of this embodiment, the wiring board 1210 is mounted using the FPC 1209, but the configuration is not necessarily limited thereto. The pixel drive circuit 1211 and the external circuit 1212 may be directly mounted on the substrate using a COG (Chip on Glass) method.

  Note that any of Embodiment Modes 1 to 9 can be applied to this example. Moreover, although the example of the liquid crystal display module and the light emission display module was shown as a display module, it is not restricted to this, DMD (Digital Micromirror Device; Digital micromirror device), PDP (Plasma Display Panel; Plasma display panel), The present invention can be appropriately applied to display modules such as FED (Field Emission Display) and electrophoretic display devices (electronic paper).

  In this embodiment, the desiccant for the display panel shown in the above embodiment will be described with reference to FIG.

  24A is a surface view of a display panel, FIG. 24B is a cross-sectional view taken along lines (A)-(B) in FIG. 24A, and FIG. 24C is FIG. Sectional drawing in (C)-(D) of is shown.

  As shown in FIG. 24A, the active matrix substrate 1800 and the counter substrate 1801 are sealed with a sealant 1802. A pixel region is provided between the active matrix substrate and the counter substrate. In the pixel region, a pixel 1807 is formed in a region where the source wiring 1805 and the gate wiring 1806 intersect. A desiccant 1804 is provided between the pixel region and the sealant 1802. In the pixel region, a desiccant 1814 is provided over the gate wiring or the source wiring. Although the desiccant 1814 is provided over the gate wiring here, it can be provided over the gate wiring and the source wiring.

As the desiccant 1804, it is preferable to use a substance that adsorbs water (H ₂ O) by chemical adsorption such as an alkaline earth metal oxide such as calcium oxide (CaO) or barium oxide (BaO). However, the present invention is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.

  Further, the desiccant can be fixed to the substrate in a state where the desiccant is contained as a granular substance in a highly moisture-permeable resin. Here, examples of the highly moisture-permeable resin include acrylic resins such as ester acrylate, ether acrylate, ester urethane acrylate, ether urethane acrylate, butadiene urethane acrylate, special urethane acrylate, epoxy acrylate, amino resin acrylate, and acrylic resin acrylate. Can be used. In addition, bisphenol A type liquid resin, bisphenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cyclic aliphatic epoxy resin, epibis type Epoxy resins such as epoxy resins, glycidyl ester resins, glycidyl amine resins, heterocyclic epoxy resins, and modified epoxy resins can be used. Further, other substances may be used. Further, for example, an inorganic material such as siloxane may be used.

  Furthermore, as the substance having water absorption, a material obtained by solidifying a solution in which molecules capable of adsorbing water by chemical adsorption are mixed in an organic solvent can be used.

  Note that as the above-described highly permeable resin or inorganic substance, it is preferable to select a substance having a higher moisture permeability than a substance used as a sealing material.

  In the light emitting device of the present invention as described above, water mixed into the light emitting device from the outside can be absorbed before the water reaches the region where the light emitting element is formed. As a result, deterioration of an element provided in the pixel due to water, typically a light emitting element, can be suppressed.

  As shown in FIG. 24B, the desiccant 1804 is provided between the sealant 1802 and the pixel region 1803 in the periphery of the display panel. Further, by providing a recess in the counter substrate or the active matrix substrate and providing a desiccant 1804 there, the display panel can be thinned.

  As shown in FIG. 24C, in the pixel 1807, a semiconductor region 1811, a gate wiring 1806, a source wiring 1805, and a pixel electrode 1812 which are part of a semiconductor element for driving the display element are formed. . In the pixel portion of the display panel, the desiccant 1804 is provided in a region overlapping with the gate wiring 1806 in the counter substrate. Since the width of the gate wiring is 2 to 4 times that of the source wiring, by providing the desiccant 1814 over the gate wiring 1806 which is a non-display region, the aperture ratio is not lowered and the display element can be formed. Intrusion of moisture and deterioration resulting therefrom can be suppressed. In addition, the display panel can be thinned by providing a recess in the counter substrate and providing a desiccant there.

  According to the present invention, a circuit that can reduce off-state current and has highly integrated semiconductor elements with high reliability, typically a signal line driver circuit, a controller, a CPU, a converter of a sound processing circuit, a power supply circuit, transmission / reception A semiconductor device such as a circuit, a memory, an amplifier of a sound processing circuit, or the like can be formed. In addition, a system-on-chip that is monolithically equipped with circuits that constitute a single system (functional circuit) such as an MPU (microcomputer), memory, and I / O interface, enabling high speed, high reliability, and low power consumption. Can be formed at low cost.

  Various electronic devices can be manufactured by incorporating the semiconductor device described in any of the above embodiments into a housing. Electronic devices include television devices, cameras such as video cameras and digital cameras, goggles type displays (head mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), notebook personal computers, game machines, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.) or recording medium (specifically, Digital Versatile Disc (DVD)) A device having a display capable of displaying). Here, as representative examples of these electronic devices, a television device and its block diagram are shown in FIGS. 11 and 12, respectively, and a digital camera is shown in FIG.

  FIG. 11 is a diagram illustrating a general configuration of a television apparatus that receives an analog television broadcast. In FIG. 11, radio waves for television broadcasting received by the antenna 1101 are input to the tuner 1102. The tuner 1102 generates and outputs an intermediate frequency (IF) signal by mixing the high-frequency television signal input from the antenna 1101 with a signal having a local oscillation frequency controlled according to the desired reception frequency.

  The IF signal extracted by the tuner 1102 is amplified to a necessary voltage by an intermediate frequency amplifier (IF amplifier) 1103, and then detected by the image detection circuit 1104 and detected by the audio detection circuit 1105. The video signal output from the video detection circuit 1104 is separated into a luminance signal and a color signal by the video processing circuit 1106 and further subjected to predetermined video signal processing to become a video signal, which is the semiconductor device of the present invention. Display devices, typically liquid crystal display devices, light-emitting display devices, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), electricity The image is output to an image output unit 1108 such as an electrophoretic display device (electronic paper). A display device using a liquid crystal display device is a liquid crystal television, and a display device using a light emitting display device is an EL television. The same applies when other display devices are used.

  The signal output from the sound detection circuit 1105 is subjected to processing such as FM demodulation by the sound system processing circuit 1107 to become a sound signal, is appropriately amplified, and is output to the sound system output unit 1109 such as a speaker.

  Note that the television apparatus using the present invention is not limited to a terrestrial broadcast such as a VHF band or a UHF band, a cable broadcast, or an analog broadcast such as a BS broadcast, but also a terrestrial digital broadcast, a cable digital broadcast, Or it may correspond to BS digital broadcasting.

  FIG. 12 is a perspective view of the television device as viewed from the front, and includes a housing 1151, a display portion 1152, a speaker portion 1153, an operation portion 1154, a video input terminal 1155, and the like. Moreover, it has a structure as shown in FIG.

  The display unit 1152 is an example of the video system output unit 1108 in FIG. 11, and displays video here.

  The speaker unit 1153 is an example of the audio system output unit in FIG. 11, and outputs audio here.

  The operation unit 1154 is provided with a power switch, a volume switch, a channel selection switch, a tuner switch, a selection switch, and the like. By pressing the button, the power of the television apparatus is turned on / off, video selection, audio adjustment, And selecting a tuner. Although not shown, the above selection can also be performed by a remote controller type operation unit.

  The video input terminal 1155 is a terminal for inputting a video signal from the outside such as a VTR, a DVD, or a game machine to the television apparatus.

  In the case where the television device shown in this embodiment is a wall-mounted television device, a wall-hanging portion is provided on the back of the main body.

  By using the display device which is an example of the semiconductor device of the present invention for the display portion of the television device, a high-definition television device with high contrast can be manufactured at low cost with high throughput and yield. In addition, by using the semiconductor device of the present invention for the CPU that controls the video detection circuit, the video processing circuit, the audio detection circuit, and the audio processing circuit of the television device, the television device is manufactured at low cost and with high throughput and yield. be able to. For this reason, it can be applied to various uses as a display medium having a particularly large area, such as a wall-mounted television device, an information display board in a railway station or airport, and an advertisement display board in a street.

  13A and 13B are diagrams illustrating an example of a digital camera. FIG. 13A is a perspective view seen from the front side of the digital camera, and FIG. 13B is a perspective view seen from the rear side. 13A, the digital camera is provided with a release button 1301, a main switch 1302, a finder window 1303, a flash 1304, a lens 1305, a lens barrel 1306, and a housing 1307.

  In FIG. 13B, a viewfinder eyepiece window 1311, a monitor 1312, and operation buttons 1313 are provided.

  When the release button 1301 is pressed down to a half position, the focus adjustment mechanism and the exposure adjustment mechanism are operated, and when the release button 1301 is pressed down to the lowest position, the shutter is opened.

  A main switch 1302 switches on / off the power of the digital camera when pressed or rotated.

  The viewfinder window 1303 is disposed on the front of the lens 1305 on the front surface of the digital camera, and is a device for confirming the shooting range and focus position from the viewfinder eyepiece window 1311 shown in FIG.

  The flash 1304 is arranged at the upper front of the digital camera, and emits auxiliary light simultaneously with the release button being pressed to open the shutter when the subject brightness is low.

The lens 1305 is disposed in front of the digital camera. The lens is composed of a focusing lens, a zoom lens, and the like, and constitutes a photographing optical system together with a shutter and a diaphragm (not shown). An imaging element such as a CCD (Charge Coupled Device) is provided behind the lens.

The lens barrel 1306 moves the lens position in order to focus the focusing lens, the zoom lens, and the like. During photographing, the lens 1305 is moved forward to move the lens 1305 forward. Further, when carrying, the lens 1305 is retracted to make it compact. In this embodiment, the structure is such that the subject can be zoomed by extending the lens barrel. However, the present invention is not limited to this structure. It is also possible to use a digital camera that can perform zoom shooting without extending the camera.

  The viewfinder eyepiece window 1311 is provided on the upper rear surface of the digital camera, and is a window provided for eye contact when confirming a shooting range and a focus position.

  The operation buttons 1313 are various function buttons provided on the rear surface of the digital camera, and include a setup button, a menu button, a display button, a function button, a selection button, and the like.

  By using a display device which is an embodiment of the semiconductor device of the present invention for a monitor, a high-definition digital camera with high contrast can be manufactured at low cost with high throughput and yield. In addition, a CPU that performs related processing in response to operation inputs of various function buttons, main switches, relays buttons, etc., a circuit that performs an autofocus operation and an autofocus adjustment operation, a strobe light emission drive control, and a CCD drive timing A control circuit, an image pickup circuit that generates an image signal from a signal photoelectrically converted by an image pickup device such as a CCD, an A / D conversion circuit that converts an image signal generated by the image pickup circuit into a digital signal, and writing image data into a memory In addition, by using the semiconductor device of the present invention for a CPU or the like that controls each circuit such as a memory interface that reads image data, a digital camera can be manufactured at low cost and with high throughput and yield.

8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 6 is a cross-sectional view illustrating a structure of a first conductive layer of a semiconductor device according to the present invention. FIG. 6 is a cross-sectional view illustrating a structure of a first insulating layer of a semiconductor device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. 2A and 2B illustrate a structure of a droplet discharge device that can be applied to the present invention. FIG. 6 is a top view illustrating a method for mounting a driver circuit of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a method for mounting a driver circuit of a display device according to the present invention. FIG. 9 is a block diagram illustrating a structure of an electronic device. 6A and 6B illustrate examples of electronic devices. 6A and 6B illustrate examples of electronic devices. FIG. 6 is a diagram showing a circuit configuration when a scanning line side driving circuit is formed of TFTs in the liquid crystal display panel according to the present invention. FIG. 6 is a diagram (shift register circuit) illustrating a circuit configuration in the case where a scanning line side driving circuit is formed using TFTs in a liquid crystal display panel according to the present invention. FIG. 4 is a diagram (buffer circuit) illustrating a circuit configuration when a scanning line side driving circuit is formed of TFTs in the liquid crystal display panel according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. Top view and cross-sectional view illustrating a structure of a light-emitting display panel of the present invention. 4A and 4B illustrate a liquid crystal dropping method that can be applied to the present invention. FIG. 6 illustrates a structure of a liquid crystal display module according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. FIG. 6 illustrates a structure of a light-emitting display module according to the present invention. 4A and 4B each illustrate a mode of a light-emitting element that can be applied to the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a pixel that can be used in the light-emitting display panel of the present invention. FIG. 10 is a front view illustrating a structure of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention.

Claims (9)

Forming a plurality of gate electrode layers on a base plate,
By adjusting the viscosity and surface tension of the insulating material to expose a top of the plurality of the gate electrode layer, and between so as to fill, said insulating material is applied to form a insulation layer,
Forming a gate insulating layer in contact with the upper portion of the front Kize' edge layer and a plurality of the gate electrode layer,
Forming a semiconductor region on the gate insulating layer so as to partially overlap the gate electrode ;
The method for manufacturing a semiconductor device characterized by forming the source electrode layer over the semiconductor area and the drain electrode layer. Forming a plurality of gate electrode layers on a base plate,
The insulating material selectively formed insulation layer out ejection between the gate electrode layer,
Forming a gate insulating layer to contact the front Kize' edge layer and a plurality of the gate electrode layer,
Forming a semiconductor region on the gate insulating layer so as to partially overlap the gate electrode ;
The method for manufacturing a semiconductor device characterized by forming the source electrode layer over the semiconductor area and the drain electrode layer. In claim 2,
The insulating layer, a method for manufacturing a semiconductor device according to claim Rukoto forming shape in Migihitsuji covering the sides of the gate electrode layer. Forming a source electrode layer and a drain electrode layer on a plate,
By adjusting the viscosity and surface tension of the insulating material to expose the upper portion of the source electrode layer and the drain electrode layer, so as to fill between and, the insulation layer is formed by coating the insulating material,
Forming a semiconductor region in contact with the upper portion of the front Kize' edge layer and the source electrode layer and the drain electrode layer,
Forming a gate insulating layer on the semiconductor area,
A method for manufacturing a semiconductor device , comprising forming a gate electrode layer over the gate insulating layer so as to partially overlap with the semiconductor region . Forming a source electrode layer and a drain electrode layer on the substrate;
An insulating material is selectively discharged between the source electrode layer and the drain electrode layer to form an insulating layer ;
Forming a semiconductor region in contact with the insulating layer, the source electrode layer, and the drain electrode layer;
Forming a gate insulating layer on the semiconductor region;
A method for manufacturing a semiconductor device, comprising forming a gate electrode layer over the gate insulating layer so as to partially overlap with the semiconductor region. In claim 5,
The method for manufacturing a semiconductor device, wherein the insulating layer is formed so as to cover side portions of the source electrode layer and the drain electrode layer. Forming a gate electrode layer, a gate wiring layer and a connection wiring layer on the substrate;
By adjusting the viscosity and surface tension of the insulating material, the insulating material is applied so that the upper portions of the gate electrode layer, the gate wiring layer, and the connection wiring layer are exposed and filled between them. Forming an insulating layer,
Forming a gate insulating layer on the insulating layer and in contact with the gate electrode layer, the gate wiring layer and the connection wiring layer;
Forming a semiconductor region on the gate insulating layer so as to partially overlap the gate electrode ;
A first mask pattern is formed on the gate insulating layer by discharging a solution that forms a liquid repellent surface in a region where the connection wiring layer and the gate insulating layer overlap.
A second mask pattern is formed on the gate insulating film except for the region of the first mask pattern,
Removing the first mask pattern to expose the gate insulating layer, and then etching the gate insulating layer using the second mask pattern to form a first contact hole;
Removing the second mask pattern;
Forming a source electrode layer and a drain electrode layer on the semiconductor region, on the gate insulating layer, and on the first contact hole;
Forming a protective layer on the gate insulating layer and on the source and drain electrode layers;
A third mask pattern is formed on the protective layer by discharging a solution that forms a liquid-repellent surface in a region where the connection wiring layer and the gate wiring layer and the gate insulating layer overlap.
An interlayer insulating film is formed on the protective layer except for the third mask pattern,
After removing the third mask pattern, using the interlayer insulating film as a mask, etching the protective layer and part of the gate insulating layer to expose the gate wiring layer and form a connection region, A method for manufacturing a semiconductor device, wherein the connection wiring is exposed to form a second contact hole. Forming a gate electrode layer, a gate wiring layer and a connection wiring layer on the substrate;
An insulating material is selectively discharged between the gate electrode layer, the gate wiring layer and the connection wiring layer to form an insulating layer;
Forming a gate insulating layer on the insulating layer and in contact with the gate electrode layer, the gate wiring layer and the connection wiring layer;
Forming a semiconductor region on the gate insulating layer so as to partially overlap the gate electrode ;
A first mask pattern is formed on the gate insulating layer by discharging a solution that forms a liquid repellent surface in a region where the connection wiring layer and the gate insulating layer overlap.
A second mask pattern is formed on the gate insulating film except for the region of the first mask pattern,
Removing the first mask pattern to expose the gate insulating layer, and then etching the gate insulating layer using the second mask pattern to form a first contact hole;
Removing the second mask pattern;
Forming a source electrode layer and a drain electrode layer on the semiconductor region, on the gate insulating layer, and on the first contact hole;
Forming a protective layer on the gate insulating layer and on the source and drain electrode layers;
A third mask pattern is formed on the protective layer by discharging a solution that forms a liquid-repellent surface in a region where the connection wiring layer and the gate wiring layer and the gate insulating layer overlap.
An interlayer insulating film is formed on the protective layer except for the third mask pattern,
After removing the third mask pattern, using the interlayer insulating film as a mask, etching the protective layer and part of the gate insulating layer to expose the gate wiring layer and form a connection region, A method for manufacturing a semiconductor device, wherein the connection wiring is exposed to form a second contact hole. In claim 8,
The method for manufacturing a semiconductor device, wherein the insulating layer is formed to cover side portions of the source electrode layer and the drain electrode layer.

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