JP4787045B2 - Power supply voltage selection circuit - Google Patents

Description

  The present invention relates to a power supply voltage selection circuit capable of switching a power supply voltage in accordance with a system operation state.

  An electronic circuit that uses a plurality of power supply voltages and selects one of the power supply voltages to operate is known. Such an electronic circuit includes switch means for switching a plurality of power supply voltages, and the power supply voltage can be switched by switching the switch means in accordance with the operating state of the system. The switch means generally uses a transistor or the like.

Since such an electronic circuit drives the gate of the transistor for switching the power supply voltage at the same potential as the power supply voltage of the transistor, it has only a voltage supply capability obtained by subtracting the threshold value of the transistor from the power supply voltage applied to the transistor. Therefore, there is a problem that the current supply capability is small with respect to the size of the transistor and that the power supply voltage fluctuates greatly due to fluctuations in the supply current.
There are a number of suggestions for how to solve such problems. (For example, refer to Patent Document 1.)

  In the prior art disclosed in Patent Document 1, the drive signal applied to the gate of the transistor for switching the power supply voltage is a signal boosted by a booster circuit, so that the transistor is driven at a voltage higher than the power supply voltage of the transistor. Thus, a large current supply capability can be exhibited with a transistor having a small area.

  The prior art disclosed in Patent Document 1 will be described with reference to FIG. FIG. 3 is a circuit diagram rewritten to the extent that it does not depart from the gist for easy explanation. In FIG. 3, 300 is a first power supply voltage input terminal, 301 is a second power supply voltage input terminal, 302 is a first switching signal input terminal, and 303 is a second switching signal that is an inverted signal of the first switching signal. A signal input terminal, 304 is a clock generator, 305 is a booster circuit, 306 is a first MOS transistor, 307 is a second MOS transistor, 308 is an output terminal, 309 is a clock signal generated from the clock generator 304, and 310 is a booster circuit A signal generated from 305, 311 is an internal circuit, and 312 is a capacitor.

  A first power supply voltage and a second power supply voltage are inputted from the first power supply voltage input terminal 300 and the second power supply voltage input terminal 301, respectively. The second power supply voltage is higher in potential than the first power supply voltage.

The clock generator 304 is activated when the voltage input to the second switching signal input terminal 303 changes from a voltage lower than the second power supply voltage to the same voltage as the second power supply voltage, generates a clock signal 309 and boosts the voltage. Supply to the circuit 305.
The booster circuit 305 is activated when the voltage input to the second switching signal input terminal 303 changes from a voltage lower than the second power supply voltage to the same voltage as the second power supply voltage, and a clock generated from the clock generator 304 The signal 309 is used to generate a signal 310 having a voltage higher than the second power supply voltage.

The signal 310 is input to the gate of the second MOS transistor 307 whose drain is connected to the second power supply voltage and whose source is connected to the output terminal 308. The gate of the first MOS transistor 306 whose drain is connected to the first power supply voltage and whose source is connected to the output terminal 308 is the first
The switching signal input terminal 302 is connected.

  Although the internal circuit 311 and the capacitor 312 in FIG. 3 are not shown in the prior art shown in Patent Document 1, it is widely used by connecting the internal circuit 311 to the first power supply voltage input terminal 300. In general, the capacitor 312 is also provided between the output terminal 308 and the ground power supply, and is generally used to stabilize the output voltage.

  By adopting such a configuration, the prior art disclosed in Patent Document 1 is based on the first MOS transistor 306 according to the signal of the first switching signal input terminal 302 and the signal of the second switching signal input terminal 303. And the second MOS transistor 307 are turned on, and the power supply voltage of either the first power supply voltage input terminal 300 or the second power supply voltage input terminal 301 is output to the output terminal 308.

Japanese Patent Laid-Open No. 63-117516 (page 3, FIG. 1)

  However, in the conventional technique shown in Patent Document 1, when the power supply voltage output to the output terminal 308 is switched from the second power supply voltage to the first power supply voltage, it is input to the first power supply voltage input terminal 300. There is a problem that the internal power supply 311 using the first power supply voltage as a power supply voltage malfunctions due to a large fluctuation in the first power supply voltage.

  This will be described with reference to FIG. When a first power supply voltage is input to the first switching signal input terminal 302 and a voltage higher than the second power supply voltage is input to the second switching signal input terminal 303, the first MOS transistor 306 is turned off, Since the second MOS transistor 307 is turned on, the second power supply voltage is output to the output terminal 308, and the parasitic capacitance of the other electronic circuit connected to the capacitor 312 and the output terminal 308 (not shown) (hereinafter referred to as the parasitic capacitance of the output terminal 308). A voltage equivalent to the second power supply voltage is charged.

  Next, when a voltage higher than the first power supply voltage is input to the first switching signal input terminal 302 and the second power supply voltage is input to the second switching signal input terminal 303 at the power supply voltage selection timing shown in FIG. Since the first MOS transistor 306 is turned on and the second MOS transistor is turned off, the first power supply voltage is output to the output terminal 308.

  That is, the first power input terminal 300 and the output terminal 308 are short-circuited. Then, the first power supply voltage and the second power supply voltage charged in the capacitor 312 or the parasitic capacitance of the output terminal 308 are attracted to each other, and the first power supply voltage is the power supply voltage shown in FIG. Just after the selection timing, it fluctuates greatly in the direction of the second power supply voltage, and then the power supply voltage charged in the parasitic capacitance of the capacitor 312 and the output terminal 308 is slowly discharged and returns to the second power supply voltage. . As a result, the internal circuit 311 operating with the first power supply voltage as the power supply voltage malfunctions.

  An object of the present invention is to solve the above-described problems and provide a power supply voltage selection circuit that suppresses fluctuations in the power supply voltage even when the power supply is switched.

  In order to achieve the above object, the present invention employs the following configuration.

A power supply voltage selection circuit for switching output voltages of a plurality of power supplies,
The power supply voltage selection circuit has a power supply selection unit and a power supply fluctuation suppression unit,
Power selecting unit inputs the first power supply voltage and a second power supply voltage and the control signal, and the voltage output by switching these two supply voltage based on the control signal,
The power supply fluctuation suppressing unit includes an analog switch circuit that operates between the voltage output and the reference potential so that the voltage output has the same potential as the first power supply voltage, and the first power supply voltage and the second power supply. It is characterized by suppressing power supply fluctuations that occur when switching to voltage.

The analog switch circuit includes a first analog switch that connects the reference potential and the voltage output with a predetermined on-resistance,
A drive voltage generator for driving the first analog switch and being connected in parallel with the first analog switch;
The drive voltage generator is configured to connect a constant current source and a second analog switch in series, and generate a drive voltage that determines an on-resistance of the first analog switch according to a voltage value appearing at these two connection points. And

The first analog switch and the second analog switch are transistor switches,
The second analog switch is characterized in that the on-resistance is determined according to the value of the first power supply voltage.

The power supply fluctuation suppressing unit has a disconnect switch provided in series with the drive voltage generating unit,
The disconnect switch is controlled to open and close based on a control signal.

  The power supply voltage selection circuit of the present invention includes a power supply selection unit and a power supply fluctuation suppression unit. The power source selection unit switches between two different power source voltages, but the power source fluctuation suppression unit suppresses fluctuations in the power source voltage that occur during the switching. Thereby, malfunction of the electronic circuit can be prevented.

Hereinafter, embodiments of the power supply voltage selection circuit of the present invention will be described in detail with reference to FIGS.
In FIG. 1, 101 is a power source selection unit, 104 is an internal circuit, 106 is a capacitor, 108 is a first control signal input terminal, 109 is a second control signal input terminal that is an inverted signal of the first control signal 108, 110 is a power supply fluctuation suppressing unit, 111 is a P-channel MOS transistor that is a first analog switch, 112 is a constant current source, 113 is an N-channel MOS transistor that is a second analog switch, and 114 is an N-channel MOS that is a disconnect switch Transistors 115 and 116 are switch means of the power source selection unit 101 and are N-channel MOS transistors. Reference numeral 120 denotes a drive voltage generator.

  The constant current source 112 and the N channel MOS transistor 113 constitute a drive voltage generator 120, and the drive voltage generator 120 and the P channel MOS transistor 111 constitute an analog switch circuit.

  The voltage of the reference power line 107 is a reference potential, for example, 0V. The voltage of the first power supply voltage line 102 is, for example, −0.8V. The voltage of the second power supply voltage line 103 is, for example, −1.2V. The voltage output line 105 is selected and output by the power supply selection unit 101 as to whether the voltage of the first power supply voltage line 102 or the voltage of the second power supply voltage line 103 is selected.

  The internal circuit 104 operates using the voltage of the first power supply voltage line 102 as a power supply voltage. The capacitor 106 is provided between the reference power supply line 107 in order to stabilize the voltage of the voltage output line 105, and for example, a capacitor can be used.

  The power supply selection unit 101 includes an N-channel MOS transistor 115 having a source connected to the first power supply voltage line 102, a drain connected to the voltage output line 105, a gate connected to the first control signal input terminal 108, and a source connected to the second power supply. The voltage line 103 includes a voltage output line 105 having a drain and an N-channel MOS transistor 116 having a gate connected to a second control signal input terminal 109.

The P-channel MOS transistor 111 constituting the analog switch circuit of the power supply fluctuation suppressing unit 110 has a source connected to the reference power supply line 107, a drain connected to the voltage output line 105, and a gate connected to the drive voltage generating unit 120. is doing.
The drive voltage generator 120 connects a constant current source 112 and an N-channel MOS transistor 113 in series. One terminal of the constant current source 112 is connected to the reference power supply line 107, and the other terminal is connected to the drain of the N-channel MOS transistor 113. A connection point between the constant current source 112 and the N channel MOS transistor 113 is connected to the gate of the P channel MOS transistor 111.

The source of the N channel MOS transistor 113 is connected to the drain of the N channel MOS transistor 114, and the source of the N channel MOS transistor 114 is connected to the voltage output line 105.
The gate of the N channel MOS transistor 113 is connected to the first power supply voltage line 102, and the gate of the N channel MOS transistor 114 is connected to the first control signal input terminal 108.

  That is, the N-channel MOS transistor 113 has its on-resistance determined according to the value of the first power supply. The N-channel MOS transistor 114 is controlled to open and close based on the first control signal input terminal 108.

Next, the operation of the power supply voltage selection circuit of the present invention will be described.
When the voltage input to the first control signal input terminal 108 is −1.2 V and the voltage input to the second control signal input terminal 109 is 0 V, the N-channel MOS transistor 115 is off and the N-channel MOS transistor 116 is The voltage -1.2 V of the second power supply voltage line 103 is output to the voltage output line 105, and the parasitic capacitance of the other electronic circuit connected to the capacitor 106 or the voltage output line 105 (not shown) (hereinafter referred to as the power supply line 105). Voltage of -1.2V is charged.

Further, the N channel MOS transistor 114 of the power supply fluctuation suppressing unit 110 is turned off because the first control signal input terminal 108 is −1.2V, and the P channel MOS transistor 111 is turned off when the N channel MOS transistor 114 is turned off. Therefore, the constant current source 112 outputs the voltage 0 V of the reference power supply line 107 to the junction between the constant current source 112 and the N-channel MOS transistor 113 and turns off.
That is, the power supply fluctuation suppressing unit 110 is in a non-operating state.

Next, when the voltage 0V is input to the first control signal input terminal 108 and the voltage −1.2V is input to the second control signal input terminal 109 at the power supply voltage selection timing shown in FIG. On, the N-channel MOS transistor 116 is turned off, and the first power supply voltage line 102 and the voltage output line 105 are short-circuited.
Then, the voltage −0.8 V of the first power supply voltage line 102 and the voltage −1.2 V charged in the parasitic capacitance of the capacitor 106 and the voltage output line 105 are attracted, and the voltage of the first power supply voltage line 102 is Begins to fluctuate in the direction of -1.2V.

However, since the N-channel MOS transistor 114 is turned on by the voltage 0V of the first control signal input terminal 108, the source of the N-channel MOS transistor 113 is charged to the capacitor 106 and the parasitic capacitance of the voltage output line 105. A voltage of -1.2 V is applied.
Further, since −0.8 V is applied to the gate voltage of the N-channel MOS transistor 113, the N-channel MOS transistor 113 is half-on (slightly on) due to the potential difference between the source voltage and the gate voltage. The drain of the channel MOS transistor 113 outputs −1.2 V and is input to the gate of the P channel MOS transistor 111.

  Note that the transistor size of the N channel MOS transistor 113 and the transistor size of the N channel MOS transistor 114 are determined by adding the on resistance of the N channel MOS transistor 113 and the on resistance of the N channel MOS transistor 114 to a constant current. The transistor size is lower than the impedance of the source 112.

Therefore, the P-channel MOS transistor 111 is turned on, and the voltage −1.2 V charged in the capacitor 106 and the parasitic capacitance of the voltage output line 105 is instantaneously discharged and fluctuates in the 0V direction.
Further, since the N-channel MOS transistor 114 is on, the source voltage of the N-channel MOS transistor 113 instantaneously changes from −1.2V to 0V, but the source voltage of the N-channel MOS transistor 113 is N-channel MOS. When the gate voltage of the transistor 113 becomes equal to −0.8V, the N-channel MOS transistor 113 is turned off. Further, 0V is output to the junction point between the constant current source 112 and the N-channel transistor 113 by the constant current source 112. As a result, the P-channel MOS transistor 111 is turned off.

  That is, as shown in FIG. 2, the voltage of the first power supply voltage line 102 immediately after the power supply voltage selection timing is short-circuited to the voltage output line 105, so that the voltage −0.8 V of the first power supply voltage line 102 and the capacitance 106 Although it starts to fluctuate in the direction of -1.2V due to an inquiry with the voltage -1.2V charged in the parasitic capacitance of the power line 105, the voltage of the voltage output line 105 instantaneously changes from -1.2V to -0.8V. Since it fluctuates, the voltage of the first power supply voltage line 102 instantaneously returns to −0.8V.

  Therefore, compared to a power supply voltage selection circuit that does not include the power supply fluctuation suppressing unit 110, fluctuations in the voltage of the first power supply voltage line 102 can be much suppressed, and malfunction of the internal circuit 104 can be prevented.

The power supply voltage selection circuit of the present invention can suppress fluctuations in the power supply voltage that occur when the power supply voltage is switched in accordance with the operating status of the system by providing a power supply fluctuation suppression unit, thereby preventing malfunction of the internal circuit. Can be prevented.
Therefore, it is suitable for a system in which malfunction of the electronic circuit is not allowed.

It is a circuit diagram explaining the power supply fluctuation suppression circuit of this invention. It is a timing chart explaining operation | movement of the power supply fluctuation suppression circuit of this invention. It is a figure explaining the prior art shown in patent document 1. FIG. 10 is a timing chart for explaining the operation of the prior art disclosed in Patent Document 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Power supply selection part 102 1st power supply line 103 2nd power supply line 104 Internal circuit 105 3rd power supply line 106 Capacitance 107 Reference | standard power supply line 108 1st control signal input terminal 109 2nd control signal input terminal 110 Power supply fluctuation | variation Suppressor 111 P-channel MOS transistor as first analog switch 112 Constant current source 113 N-channel MOS transistor as second analog switch 114 N-channel MOS transistor as disconnect switch 115 N as switch means of power supply selector 101 Channel MOS transistor 116 N-channel MOS transistor as switch means of power supply selection unit 101

Claims (4)

A power supply voltage selection circuit for switching output voltages of a plurality of power supplies,
The power supply voltage selection circuit includes a power supply selection unit and a power supply fluctuation suppression unit,
The power supply selecting unit inputs the first power supply voltage and a second power supply voltage and the control signal, and the voltage output by switching these two supply voltage based on the control signal,
The power supply fluctuation suppressing unit includes an analog switch circuit that operates between a voltage output and a reference potential so that the voltage output has the same potential as the first power supply voltage. A power supply voltage selection circuit that suppresses power supply fluctuations that occur when switching to the second power supply voltage.
The analog switch circuit includes a first analog switch that connects the reference potential and the voltage output with a predetermined ON resistance;
A drive voltage generator connected to the first analog switch in parallel and driving the first analog switch;
The drive voltage generator unit connects a constant current source and a second analog switch in series, and generates a drive voltage that determines an on-resistance of the first analog switch according to a voltage value appearing at these two connection points. The power supply voltage selection circuit according to claim 1. The first analog switch and the second analog switch are transistor switches,
3. The power supply voltage selection circuit according to claim 2, wherein an on-resistance of the second analog switch is determined according to a value of the first power supply voltage. The power supply fluctuation suppressing unit has a disconnect switch provided in series with the drive voltage generating unit,
The power supply voltage selection circuit according to claim 2, wherein the disconnection switch is controlled to open and close based on the control signal.

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