JP4787588B2 - CMOS image sensor - Google Patents

Description

  The present invention relates to a CMOS image sensor having a photogate electrode for reading an image, which is used in a scanner section of a fax machine, a scanner, or a composite printer.

  The principle of photoelectric conversion using a semiconductor is that an electron-hole pair generated in a depletion layer is accumulated and converted into a voltage. Therefore, the wavelength that can be used for the photoelectric conversion element is determined depending on the band gap energy specific to the material. Depending on the wavelength currently used, compound semiconductors such as GaAs (gallium arsenide), GaP (gallium phosphorus), and InP ( Devices have been put into practical use using various semiconductors such as indium phosphorus) or single element Si. In order to create a depletion layer for receiving light, a depletion layer of a PN junction is used to change incident light into an electron-hole pair, or a depletion layer is formed by applying a voltage to convert incident light into an electron-hole. There are things that change into pairs.

As a CMOS image sensor compatible with a CMOS process using Si, a structure in which a photogate electrode having a MOS FET structure is provided is known. Patent document 1 can be mentioned as an example. FIG. 5 shows a cross-sectional view of a pixel portion of such a CMOS image sensor. 5, the N-type Si substrate 13, P-type well formed on N-type Si substrate 14, SiO ₂ film 15 is a device isolation region, SiO ₂ film is a gate oxide film 16, 17 Images It is a polycrystalline Si electrode which is a gate electrode. In Patent Document 1, the polycrystalline Si photogate electrode 17 is formed only on a part of the photoelectric conversion region having a depletion layer. In Patent Document 1, a positive voltage is applied to the polycrystalline Si photogate electrode 17, a depletion layer is spread on the P-type well 14, and electron-hole pairs generated by light incident on the depletion layer are detected. It is used to perform photoelectric conversion.

  In the prior art, the polycrystalline Si photogate electrodes 17 are arranged in a ring shape, a rod shape, or a lattice shape, and are formed only in a part on the photoelectric conversion region.

  Next, the principle aspect of the means implemented for improving the sensitivity in a CMOS image sensor having a photodiode having a PN junction will be described.

When converting incident light into a signal in a CMOS image sensor having a photodiode having a PN junction, the following process is performed. Incident light creates electron-hole pairs in the depletion layer. Electrons are accumulated in the N-type region having a low resistance, which is a charge suction port, and holes flow and accumulate toward the P-type region having a low resistance. Due to the movement of the generated electrons and holes, the potential of the N-type region having a low resistance which is a suction port changes.
In order to take out the stored charge as a signal voltage, the following equation is used.

Signal voltage = Q (charge stored in the depletion layer) / C (depletion layer capacity)
Therefore, to increase the signal voltage,
(A) The amount of light incident on the photoelectric conversion region is increased.
(B) To increase the number of electron-hole pairs.
(C) Reduce the capacity of the depletion layer.
Take measures that can be used.
JP-A-9-51085

  In the prior art, a voltage is applied to a photogate electrode made of polycrystalline Si in a part of the photoelectric conversion region to widen the depletion layer, but in order to cover part of the photoelectric conversion region with polycrystalline Si, There is a detrimental effect that the incident light to the photoelectric conversion region is limited and the efficiency is lowered. In order to avoid this adverse effect, Patent Document 1 proposes to collect light in a region not covered with a photogate electrode using a microlens. However, since this method involves a microlens formation process, a manufacturing process is added, resulting in an increase in manufacturing cost.

  In a CMOS image sensor in which a photodiode having a PN junction made of a P-type semiconductor substrate and a N-type region having a low impurity concentration formed on a P-type semiconductor substrate is used as a photoelectric conversion region, the impurity concentration of the photodiode is A photogate electrode made of a transparent material having conductivity was disposed on the entire surface of the thin N-type region through an insulating film.

  In the present invention, by applying a voltage to the transparent photogate electrode, a depletion layer can be formed in the photoelectric conversion region without reducing incident light to the photoelectric conversion region. Further, in this method, since a microlens for condensing is not necessary, a CMOS image sensor advantageous in terms of manufacturing cost can be produced.

  The CMOS image sensor according to the present invention uses Si, which has high efficiency in the visible light region, and generates a depletion layer by a PN junction and a depletion layer provided on the entire surface of the photoelectric conversion region by applying a voltage to the photogate electrode. By using both, incident light can be converted into electron-hole pairs more efficiently.

  FIG. 1 is a structural sectional view showing the first embodiment.

  The component of Example 1 of this invention is demonstrated. Photo having a PN junction comprising an N-type well 2 having a low impurity concentration, a P-type well 3 surrounding the N-type well, and a low-resistance N-type region 4 serving as a signal extraction port, provided on the P-type semiconductor substrate 1 A signal extraction electrode 6 made of Al (aluminum) or the like provided on a diode and an N-type well 2 having a low impurity concentration through an oxide film 5, a passivation film 7 covering the electrode 6, and an N-type having a low impurity concentration It comprises a transparent photogate electrode 8 made of ITO (Indium Tin Oxide) or the like disposed so as to cover the entire surface of the well 2 region, a passivation film 7, and an electrode 9 for transmitting a potential to the transparent photogate electrode 8.

  Here, the passivation film 7 is left only in the vicinity of the signal extraction electrode 6 and the electrode 9, and the transparent photogate electrode 8 is disposed so as to be in contact with the N-type well 2 having a low impurity concentration through the oxide film 5.

  By applying a negative voltage to the transparent photogate electrode 8, a surface depletion layer region 10 is generated on the surface of the N-type well 2 having a low impurity concentration. In addition, a PN junction depletion layer region 11 exists between the P-type semiconductor substrate 1 and the N-type well 2 having a low impurity concentration provided near the surface thereof. A combination of the PN junction depletion layer region 11 and the surface depletion layer region 10 is a photoelectric conversion region. In this way, the entire surface region of the N-type well 2 having a low impurity concentration can be easily formed into a depletion layer.

Here, the N-type well 2 having a low impurity concentration is preferably as close to an intrinsic semiconductor as possible so that the depletion layer can easily spread at a lower voltage, and the carrier density is 10E12 to 10E14 [cm ^−3] at room temperature. ] Degree is preferable. In the case of an impurity density of 10E14 [cm ⁻³ ], a depletion layer of 4 to 6 μm spreads by applying a voltage to the transparent photogate electrode 8 of −3 to −5 V close to the IC operating voltage.

  In addition, ITO used for the transparent photogate electrode 8 has a relatively high sheet resistance for use as a wiring for passing a current of 10 to 30Ω / □ at a film thickness of 1000 to 5000 mm. Since the gate electrode 8 is used only to transmit a potential, the above resistance value is sufficient.

  FIG. 2 is a plan view illustrating the first embodiment.

  An N-type well 2 having a low impurity concentration, a P-type well 3 surrounding it, an N-type region 4 connected to a signal extraction electrode 6 in the N-type well 2 having a low impurity concentration, and an N-type well 2 having a low impurity concentration A transparent photogate electrode 8 arranged so as to cover the electrode, an electrode 9 for transmitting a potential to the transparent electrode, and a passivation film 7 covering the electrode 9 and the signal extraction electrode 6.

  In this figure, the example in which the arrangement of the electrical connection between the transparent photogate electrode 8 and the electrode 9 is arranged in parallel has been described. However, the electrode 9 is arranged in a ring shape so as to be electrically connected to the transparent photogate electrode 8. You can connect.

  FIG. 3 is a structural sectional view showing the second embodiment.

  Photo having a PN junction comprising an N-type well 2 having a low impurity concentration, a P-type well 3 surrounding the N-type well, and a low-resistance N-type region 4 serving as a signal extraction port, provided on the P-type semiconductor substrate 1 A signal extraction electrode 6 and an electrode 9 made of Al (aluminum) or the like provided on an N-type well 2 having a low impurity concentration and a diode are electrically connected to the electrode 6 and connected to the electrode 6. The transparent photogate electrode 8 made of ITO or the like is disposed so as to cover the entire surface of the region, and the passivation film 7 covers the entire surface. In this embodiment, since the transparent photogate electrode 8 and the electrode 9 are in direct contact, it is necessary to dispose the transparent photogate electrode 8 so as not to overlap the signal extraction electrode 6.

  FIG. 4 is a structural sectional view showing the third embodiment.

  Photo having a PN junction comprising an N-type well 2 having a low impurity concentration, a P-type well 3 surrounding the N-type well, and a low-resistance N-type region 4 serving as a signal extraction port, provided on the P-type semiconductor substrate 1 A signal extraction electrode 6 and an electrode 9 made of Al (aluminum) or the like provided on the diode and the N-type well 2 having a low impurity concentration through the field oxide film 12 and the oxide film 5 are electrically connected to the electrode 6. It consists of a transparent photogate electrode 8 made of ITO or the like disposed so as to cover the entire surface of the N-type well 2 and a passivation film 7 covering the entire surface. Basically, it is the same as that of the second embodiment, but can be similarly implemented even if the field oxide film 12 is provided.

It is sectional drawing which shows 1st Example of this invention. It is a top view of the 1st example of the present invention. It is sectional drawing of 2nd Example of this invention. It is sectional drawing of 3rd Example of this invention. It is sectional drawing which shows a prior art example.

Explanation of symbols

1: P-type Si substrate 2: N-type well with low impurity concentration 3: P-type well 4: N-type region 5: Oxide film 6: Signal extraction electrode 7: Passivation film 8: Transparent photogate electrode 9: Electrode 10: Surface Depletion layer 11: PN junction depletion layer 12: field oxide film 13: N-type Si substrate 14: P-type well 15: element isolation oxide film 16: gate oxide film 17: polycrystalline Si photogate

Claims (2)

A photodiode comprising a first conductivity type semiconductor substrate and a second conductivity type region having a lower impurity concentration than the first conductivity type semiconductor substrate disposed in the vicinity of the surface of the first conductivity type semiconductor substrate is defined as a pixel. A CMOS image sensor
A signal extraction electrode disposed above the second conductivity type region;
A photogate electrode made of a transparent material having conductivity disposed on the entire surface of the second conductivity type region excluding the signal extraction electrode via an insulating film;
The photogate electrode is not short-circuited with the first conductivity type semiconductor substrate, and can provide a different potential from the first conductivity type semiconductor substrate;
Formed on the upper surface of the second conductivity type region by the first depletion layer region and the photogate electrode formed in the region along the bottom and side surfaces of the second conductivity type region, which is the PN junction region of the photodiode. A CMOS image sensor in which the bottom surface, the side surface, and the top surface of the second conductivity type region are photoelectric conversion regions by a second depletion layer region.   The CMOS image sensor according to claim 1, wherein the photogate electrode is a film of indium tin oxide (ITO).

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