JP4787671B2 - Clock booster circuit - Google Patents

Description

  The present invention relates to a clock booster circuit, and more particularly to a clock booster circuit including a well bias voltage generator capable of generating a stable well bias voltage.

  In recent years, LSIs used in portable electronic devices such as MDs, video cameras, and mobile phones are required to be downsized first, and furthermore, lower power consumption and more complicated calculations for longer battery life. There is a need for higher speed and lower cost for processing. As such an application, a CMOS circuit is generally used that does not consume electricity when it is not switched, and therefore uses a small amount of electricity. Furthermore, even when a CMOS circuit is used, a reduction in voltage is required in order to further reduce power consumption or enable operation with a battery to be used. However, when the power supply voltage is lowered, there arises a problem that the speed of LSI is hindered due to a decrease in the drive capability of the MOS transistor in the MOS transistor or transfer gate, and a problem that the signal does not pass through the transfer gate. In order to solve these problems, a low voltage operation LSI often uses a clock voltage doubler that boosts and outputs a clock potential (see, for example, FIG. 7 and FIG. 11 of Patent Document 1). . Further, in such a clock voltage booster circuit, in relation to the structure of the boost side drive transistor in the output stage on the IC substrate, in order to prevent latch-up of the transistor, the well in which the transistor is arranged is arranged. A bias voltage is supplied (see, for example, Patent Document 1 and Non-Patent Document 1).

  Further, a simplified clock voltage doubling circuit has been proposed with reference to these documents (see, for example, Non-Patent Document 2).

  In Non-Patent Document 1 described above, the bias voltage is supplied from the same capacitor as that for supplying the drive voltage to the transistor that is driven on the side of the output stage where the voltage is boosted. On the other hand, in Non-Patent Document 2 described above, the bias voltage is supplied via different capacitors driven at different phases.

  FIG. 4 shows a clock voltage doubling circuit having a well bias voltage generator disclosed in Non-Patent Document 2. In the figure, a portion composed of capacitors C1 and C2 and NMOS transistor M2M3 (hereinafter simply referred to as M2 and M3) is a portion disclosed in Patent Document 1, and capacitor C3 and PMOS transistor M1 (hereinafter referred to as “M2”). The portion of the well bias voltage generator disclosed in Non-Patent Document 2 is simply referred to as M1. In Non-Patent Document 1, a PMOS transistor M1 in the figure is connected to a node having the opposite polarity of the circuit composed of NMOS transistors M2 and M3. Hereinafter, this operation will be described on the assumption that the circuit is configured on a P-type substrate having an N-well.

  In the circuit shown in FIG. 4, the clock booster circuit includes an inverter circuit 1 that generates a phase inverted clock signal CKN of the clock CK, capacitors C1 and 2, NMOS transistors M2, M3, and M5 (hereinafter simply referred to as M5), It is composed of a PMOS transistor M4. As described above, the capacitor C3 and the PMOS transistor M1 are mainly connected to the well in order to prevent the PMOS transistor M4 (hereinafter simply referred to as M4) from latching up (to be exact, including the PMOS transistor M1 itself). This is for generating a bias voltage. In the figure, the back gates of the PMOS transistors M1 and M4 are shown as terminals for supplying the bias voltage for the well.

  The operation timing chart of the clock booster circuit is shown in FIG. 5, and the operation will be described using this chart. However, it is assumed that the charging voltage of the capacitors C1 to C3 is 0 V at the start of the time chart of FIG. 5, that is, in the initial state before clock input. Further, the power supply voltage of the drain (upper part of the drawing) of the NMOS transistor is set to VDD, and the ground (ground) voltage is set to VSS.

  In the section (1) immediately after the start of input of the clock signal CK, the voltages of CK and CKN are VDD and VSS, the voltage of the node N7 is VDD, and the voltage of the node N8 is VSS. At this time, since the source of the NMOS transistor M2 is VSS and the gate thereof is VDD, the NMOS transistor M2 is turned on to charge the capacitor C1. By charging C1, the voltage level of the node N8 gradually rises from VSS, and this rise is set to V8. At this time, the gate of the NMOS transistor M3 is reverse-biased and is off.

  In the next section (2), the voltages of CK and CKN become VSS and VDD, respectively. At this time, the voltage of N8 becomes VDD + V8 together with the voltage change VDD of CKN and the charging voltage V8 of C2, and N8 is connected to the gate. M3 is turned on to charge the capacitor C2. Due to the charging of C2, the potential of the node N7 gradually rises from VSS, and this rise is set to V7. At this time, M2 is off because the gate is reverse-biased.

  In the next section (3), the voltage of CK is VDD and the voltage of N7 is VDD + V7 together with the charging voltage V7 of C2, and M2 is turned on to charge C1. Thereafter, the same operation is repeated every time CK is phase-inverted, and the voltage charged to C1 and C2 gradually rises to finally become VDD, and N7 and N8 are in reverse phase and in a voltage range of 2 × VDD to VDD Become a swinging clock.

  In order to obtain a signal that swings between VSS and 2 × VDD, an inverter circuit is configured by connecting PMOS and NMOS in series between the node N7 and VSS, and these gates are driven by CKN. A signal DCK swinging from VSS to 2 × VDD is obtained from the output of the inverter circuit (the midpoint between PMOS and NMOS). This signal DCK is a signal having the same phase as the signal CK. However, in order for M4 to pass a voltage of 2 × VDD, it is necessary to increase the N-well voltage of M4 to 2 × VDD. For this purpose, a PMOS transistor M1 and a capacitor C3 are added. M1 is turned off and on in the sections (1) and (2), respectively, and when it is turned on, the voltage of N8 is passed through VB, and is charged to C3 each time CK becomes VSS. That is, VB is boosted to 2 × VDD over time. Therefore, the N-well voltage of M4 becomes 2 × VDD, and the M4 can pass the potential of 2 × VDD without forming a related parasitic circuit and without causing latch-up. It becomes like this.

  As shown in FIG. 3, the clock booster circuit is often used including a first clock booster circuit that receives the clock CK1 as an input and a second clock booster circuit that uses CK2 that is a phase-inverted clock signal of CK1 as a clock input. . The boost clock DCK1 of the first clock booster circuit and the boost clock DCK2 of the second clock booster circuit are clocks that swing from VSS (low level) to 2 × VDD (high level) in reverse phase. Each clock booster circuit has an output stabilizing circuit, that is, the above-described well bias voltage generator (M1 and C3 in FIG. 4) in order to supply a stable boosted clock without latch-up.

Japanese Patent No. 3112039 Thomas B. CHO and Paul R, Gray: "A 10b 20MS / s 35mW Pipelined A / D converter", IEEE J, Solid-State circuits, 1995, SC-30, pp. 166-172 ELECTRONICS LETTERS 28th October 1999 Vol.35 No.22 P1901-1902 `` Simplified clock voltage doubler ''

  Within each clock booster circuit, at the rising edge of N7 and the falling edge of N8 in FIG. 4, due to the delay of the inverter circuit 1, the falling of N8 starts slightly later than the rising edge of N7. For this reason, there is a period in which N7 and N8 are at an intermediate potential. During this period, M1 is turned on for a short time, a minute current flows from VB to N7, which is the intermediate potential, and the voltage of VB as shown in section (4). A descent occurs. The period during which this voltage drop occurs is short, but during the subsequent period (4), since the potential of N8 is lowered, VB is not charged from M1, and VB is a reduced voltage. Will be maintained. During this voltage period that has been lowered, a higher voltage is supplied to the drain of the PMOS transistor M4. As a result, a voltage difference is generated between the source voltage, drain voltage and bulk (back gate) voltage of the PMOS transistor M4, so that the parasitic bipolar transistor of the PMOS transistor M4 in FIG. 4 is turned on. The level output drops from 2 × VDD, and the circuit that receives DCK 1 and 2 does not operate correctly, or the performance is degraded. In order to prevent such malfunction of the circuit and degradation of performance, it is necessary to eliminate the voltage drop of VB and stably output a voltage of 2 × VDD. Alternatively, a voltage not lower than the voltage supplied to the drain of the PMOS transistor M4 needs to be the VB voltage. That is, the capacitor C3 shown in FIG. 4 is used to reduce the voltage drop of VB and at the same time maintain the high voltage up to that time during the period when the drain of the PMOS transistor M4 is driven at a high voltage.

  Here, by increasing the capacitor C3, the amount of voltage drop of VB in the section (4) of FIG. 5 can be reduced. As a result, the area of the capacitor C3 on the substrate increases, and VB is reduced. The rise time until reaching 2 × VDD becomes longer. In addition, it is possible to provide a circuit that adjusts the phase of the clock so that a minute current does not flow from VB to N7 (both CK and CKN do not become high). It will require an extra area to provide the service.

  In view of the above, an object of the present invention is to provide a clock booster circuit that can supply a stable booster clock with a simple configuration, a small area, a short rise time of a well bias voltage, and a stable booster clock. It is in. Another object of the present invention is to provide a clock booster circuit including a well bias voltage generator for generating a stable bias voltage for a well associated with the clock booster circuit without requiring an extra circuit. There is to do.

  In order to solve the above-mentioned problem, a first aspect of the present invention is a clock booster circuit that outputs a boosted clock signal using a supplied basic clock signal as an input, and includes a well bias voltage generator. A clock booster circuit; and a second clock booster circuit having a configuration similar to that of the first clock booster circuit and outputting a boosted clock signal with a phase-inverted clock signal as an input to the basic clock signal; The output of the well bias voltage generator in the first clock booster circuit and the output of the well bias voltage generator in the second clock booster circuit are connected.

  According to a second aspect of the present invention, a first level shift signal obtained by inputting a supplied basic clock signal and a phase inverted clock signal of the basic clock signal and level-shifting the basic clock signal in the boost side direction is provided. A clock level shift circuit for outputting a second level shift clock signal obtained by level shifting the clock signal and the phase-inverted clock signal in the boost side direction; and the boost side potential of the first level shift clock signal. And a first boost clock output circuit that outputs a clock signal that swings in the range of the ground potential, and a second clock signal that swings in the range of the boost side potential of the second level shift clock signal and the ground potential. The boost clock output circuit and the two level shift clock signals are input, and the voltage of the boost side potential is input. The generating in the form of full wave rectifier and is characterized in that it comprises two MOS transistors comprise constituted well bias voltage generator.

  According to a third aspect of the present invention, there is provided a first level shift in which a basic clock signal to be supplied and a phase inverted clock signal of the basic clock signal are input, and the basic clock signal is level-shifted in the boost side direction. A clock level shift circuit that outputs a second level shift clock signal obtained by level shifting the clock signal and the phase-inverted clock signal in the boost side direction; and the boost side of the first level shift clock signal A first boost clock output circuit that outputs a clock signal that swings between a potential and a ground potential, and the two level shift clock signals are input, and the voltage of the boost side potential is generated in the form of full-wave rectification. And a well bias voltage generator including two MOS transistors.

  According to a fourth aspect of the present invention, there is provided the clock booster circuit according to any one of the first to third aspects, wherein the well bias voltage generator includes an output of the well bias voltage generator and a ground. A capacitor is provided between the two MOS transistors, and when the voltage of the boost side potential is no longer supplied from the two MOS transistors, the voltage supplied so far is substantially maintained.

  According to the present invention, it is possible to realize a clock boosting circuit that has a small circuit area on a substrate and supplies a stable boosting clock. That is, the bias voltage for the well of the MOS transistor that generates the boosting clock is generated over many time periods, thereby shortening the rise time of the bias voltage for the well and the bias voltage source for the well It is possible to stabilize the voltage itself and finally generate a stable boost clock.

  The clock booster circuit of the present invention will be described below with reference to the drawings.

  First, before describing the details of the present invention, the outline of the present invention will be described with reference to FIGS.

  FIG. 1 is a diagram showing a configuration of a two-phase clock booster circuit according to the first embodiment of the present invention. The first and second clock booster circuits in the figure are clock booster circuits having a well bias voltage generator as shown in FIG. The lines connecting them indicate that the voltages generated by the well bias voltage generators in the first and second clock booster circuits are connected. The well bias voltage generator in FIG. 4 generates a high voltage on the VB line and charges the capacitor C3 when the input clock signal CK is low. In other words, the half-wave rectification is performed on the phase-shifted shift signal of the input clock CK. However, in the case of the configuration of FIG. 1, the well bias voltage generators in the first and second clock booster circuits are half-wave rectified, but when combined, the input phases of the clock booster circuit are inverted from each other. Therefore, full-wave rectification will be performed. That is, the voltage of the well bias voltage line in FIG. 4 is generated only when the phase-inverted clock signal is high, and the voltage stored in the capacitor C3 is only maintained during the low period. The well bias voltage line in FIG. 1 basically generates a voltage over the entire period.

  Therefore, in the configuration of FIG. 1, the role of the capacitor C3 of FIG. 4 is not necessary in principle, but in reality, since there is a clock phase difference and rise / fall time, the voltage between them is maintained. Therefore, it is necessary when VB is always maintained at a higher voltage than the drain of M4. In the case of the configuration shown in FIG. 1, when CK1 and CK2 are completely phase-inverted signals, the VB voltage drop described with reference to FIG. 5 occurs, but the M4 voltage actually required as the VB voltage is generated. As the voltage when the drain voltage becomes a high voltage, the same voltage is generated in the VB line in the same phase, so the voltage drop voltage is not maintained as it is, and immediately after the voltage drop, the voltage drop It will return to the previous voltage, ie, a voltage approximately equal to the drain of M4. Simply put, when M4 needs it, the necessary VB will be supplied to its back gate (N well).

  Even if a capacitor having the role of reducing the value of the voltage drop occurrence itself shown in FIG. 5 is provided, the capacitance can be shared in order to obtain the same effect. For this reason, when capacitors having the same capacitance are used, the rise of the VB voltage shown in FIG. 5 can be halved because full-wave rectification is performed.

  FIG. 2 is a diagram showing the configuration of the two-phase clock booster circuit according to the second embodiment of the present invention. The same signal lines in the first and second clock booster circuits in the configuration of FIG. 1 are shared. FIG. 3 is a diagram illustrating a configuration in which the total number of elements is reduced. For example, the inverter circuit 1 in FIG. 4, the capacitors C1 and C2, and the NMOS transistors M2 and M3 can be shared as a clock level shift circuit. Only the PMOS transistors M1 and M4 and the NMOS transistor M5 cannot be shared. This portion corresponds to the first boost clock output circuit and the second boost clock output circuit in FIG. This configuration has the same functions (actions and effects) as the configuration shown in FIG. 1, but can reduce the number of elements.

  In this configuration, if the capacitance of the capacitor is the same as that in the configuration shown in FIG. 4, the rise time of the VB voltage is set to 1 although there is no change in the amount of voltage drop of VB described with reference to FIG. / 2. This will be further described later in an actual circuit example using FIG.

  In the configuration shown in FIG. 4 described above, the well bias voltage is generated only during the period when the output DCK is a low output. However, those skilled in the art will understand that the above-described idea of the present invention can be applied to FIG. 4 so that the well bias voltage is full-wave rectified. For example, a new PMOS transistor is provided, and the drain is connected to the source of M3, the gate is connected to N8, and the source is connected to VB. Of course, the back gate (N well) of this new PMOS transistor also needs to have the generated well bias voltage. Also in this case, even when the capacitance of C3 in FIG. 5 is the same, the voltage drop amount of VB itself cannot be reduced, but the rise time can be halved.

(Example of clock booster circuit of the first embodiment)
FIG. 6 is a diagram showing an example of the clock booster circuit according to the first embodiment of the present invention described above.

  The clock booster circuit according to the first embodiment has the same configuration as the first clock booster circuit, as shown in FIG. 6, and a first clock booster circuit that outputs a boosted clock signal DCK1 with the basic clock signal CK1 as an input. And a second clock booster circuit that outputs a clock output signal DCK2 boosted with the phase-inverted clock signal CK2 of CK1 as an input, and connects the output voltages of the respective well bias voltage generators of these two circuits, The capacitor of each well bias voltage generator is a common capacitor C3. The first clock booster circuit includes an inverter circuit 11 that generates a phase-inverted clock signal CK1N of the clock CK1, capacitors C11 to C12, NMOS transistors M12, M13, and M15, and PMOS transistors M11 and M14. The clock booster circuit includes an inverter circuit 21 that generates a phase inverted clock signal CK2N of the clock CK2, capacitors C21 to C22, NMOS transistors M22, M23, and M25, and PMOS transistors M21 and M24. Each of these two circuits is the same as the circuit of FIG. 4 except for the capacitor C3.

  An operation timing chart of the clock booster circuit is shown in FIG. 7, and the operation will be described using this chart. However, in the initial state before the clock input, the charging voltage of each capacitor is 0V.

  First, the operation of the first clock booster circuit will be described.

  In the section (1) immediately after the start of input of the clock signal CK1, the voltages of CK1 and CK1N are VDD and VSS, the voltage of the node N17 is VDD, and the voltage of the node N8 is VSS. At this time, since the source of the NMOS transistor M12 is VSS and the gate thereof is VDD, the NMOS transistor M12 is turned on to charge the capacitor C11. The voltage level of the node N18 gradually rises from VSS due to charging of C11, and this rise is set to V18. At this time, the gate of the NMOS transistor M13 is reverse-biased and is off.

  In the next section (2), the voltages of CK1 and CK1N become VSS and VDD, respectively. At this time, the voltage of N18 becomes VDD + V18 in combination with the voltage change VDD of CK1N and the charging voltage V18 of C12, and N18 is connected to the gate. M13 is turned on to charge the capacitor C12. Due to the charging of C12, the potential of the node N17 gradually rises from VSS, and this rise is set to V17. At this time, M12 is off.

  Further, in the next section (3), the voltage of N17 of the first clock booster circuit becomes VDD + V17 together with the charging voltage V17 of C12, and M12 is turned on to charge C11. Thereafter, the same operation is repeated every time CK is phase-inverted, and the voltage charged in the capacitor gradually increases to finally become VDD, and N17 and N18 swing in the voltage range of 2 × VDD to VDD in reverse phase. Become a clock.

  In order to swing the boost clock signal DCK1 between VSS and 2 × VDD, DCK1 and N17 are connected across the PMOS transistor M14, and the NMOS transistor M15 is turned off in the section (1). M14 is turned on in order to pass the voltage, and M15 is turned on in the section (2) to force VSS, and at this time, M14 is turned off to cut the current flowing from N17 to VSS. However, in order for M14 to pass a voltage of 2 × VDD, it is necessary to increase the N-well voltage of M14 to 2 × VDD. For this purpose, the PMOS transistor M11 is used. M11 is turned off and on in the sections (1) and (2), respectively, and when it is turned on, the voltage of N18 is passed through VB, and is charged to C13 every time CK1 becomes VSS. That is, VB is boosted to 2 × VDD with time, and the potential of 2 × VDD can be passed through M14.

  On the other hand, the second clock booster circuit operates in the same manner as the first clock booster circuit with the phase inverted clock signal CK2 of CK1 as an input.

  In the present embodiment, it is possible to connect the N-wells of the PMOS transistors M14 and M24 and use a common capacitor C3. Also, after VB reaches 2 × VDD, M11 and M21 are turned on alternately and operate so as to compensate for the voltage drop of VB, so there is little dependency on the voltage maintaining function of the capacitor, and VB is less likely to drop. At the same time, the impedance of the VB voltage line itself is lowered and is not affected by external noise or the like. Basically, when the boosted clock output is a high voltage output, a bias voltage is generated from the source potential of the PMOS transistor that supplies the high voltage, and therefore, between the bias voltage and the source potential of the PMOS transistor, The potential difference that should be a problem is basically eliminated.

  In addition, even when the capacitor C3 is added, the capacity can be reduced, and the area can be reduced as compared with the case where the capacitor is individually provided as the voltage maintaining function. Further, in this case, M11 and M21 are alternately turned on at the time of rising, and the capacitor C3 is charged, so that the time until VB becomes 2 × VDD is shorter than in the case where each capacitor is individually provided.

  As described above, in the first embodiment, the clock booster circuits having the same configuration are input with clocks whose phases are inverted, and the outputs of the well bias voltage generators in the respective clock booster circuits are connected. Therefore, there is no problematic voltage drop, a stable well bias can be obtained, and a capacitor can be basically eliminated. In order to further stabilize the capacitor, it is possible to reduce the size even when the capacitor is provided in the well bias voltage line. In addition, even when a capacitor having the same capacity is added for the same purpose as in the conventional case, the capacity for that purpose is sufficient, and the area is smaller, the rise time is shorter than the case of having individual capacitors, and the voltage A boost clock with a small drop can be output.

  Further, in this embodiment, when the phase is adjusted so that the high period of the CK1 signal and the low period of the CK2 signal overlap, a voltage drop is generated in one well bias generator. However, on the other hand, since the operation is performed to cancel the voltage drop, the VB voltage that does not substantially generate the voltage drop shown in (4) of FIG. 5 can be obtained. Even in this case, the capacitor added to the VB voltage line has the effect of reducing the high-frequency impedance of the line and reducing the influence of external noise.

(Example of clock booster circuit of the second embodiment)
An example of the clock booster circuit according to the second embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 8, the clock booster circuit according to the second embodiment is a clock that outputs level-shifted clock signals N7 and N8 that are level-shifted with the phase-inverted clock signal CK2 of the basic clock signals CK1 and CK1 as inputs. A level shift circuit, a first boost clock output circuit that outputs DCK1 that swings between VSS and 2 × VDD, and a second boost clock output circuit that outputs DCK2 that swings between VSS and 2 × VDD, The output voltages of the well bias voltage generators of these two circuits are connected, and the capacitor of each well bias voltage generator is a common capacitor C3. The clock level shift circuit includes capacitors C1 and C2 and NMOS transistors M2 and M3. The first boost clock output circuit includes NMOS transistor M5 and PMOS transistors M1 and M4. The 2-boost clock output circuit includes an NMOS transistor M8 and PMOS transistors M6 and M7.

  The operation timing chart of the clock booster circuit is shown in FIG. 9, and the operation will be described using this chart. However, in the initial state before the clock input, the charging voltage of each capacitor is 0V.

  In the section (1) immediately after the start of input of the clock signals CK1 and CK2, the voltages of CK1 and CK2 are VDD and VSS, the voltage of the node N7 is VDD, and the voltage of the node N8 is VSS. At this time, since the source of the NMOS transistor M2 is VSS and the gate thereof is VDD, the NMOS transistor M2 is turned on to charge the capacitor C1. The voltage level of the node N8 gradually rises from VSS due to charging of C11, and this rise is set to V8. At this time, the gate of the NMOS transistor M3 is reverse-biased and is off.

  In the next section (2), the voltages of CK1 and CK2 are VSS and VDD, respectively. At this time, the voltage of N8 is VDD + V8 in combination with the voltage change VDD of CK2 and the charging voltage V8 of C2, and N8 is connected to the gate. M3 is turned on to charge the capacitor C2. Due to the charging of C2, the potential of the node N7 gradually rises from VSS, and this rise is set to V7. At this time, M2 is off.

  Further, in the next section (3), the voltage of N7 of the first clock booster circuit becomes VDD + V7 together with the charging voltage V7 of C2, and M2 is turned on to charge C1. Thereafter, the same operation is repeated every time CK is phase-inverted, and the voltage charged in the capacitor gradually increases to finally become VDD, and N7 and N8 swing in the voltage range of 2 × VDD to VDD in reverse phase. Become a clock.

  In order to swing the boost clock signal DCK1 between VSS and 2 × VDD, DCK1 and N7 are connected across the PMOS transistor M4, and the NMOS transistor M5 is turned off in the section (1). At this time, DCK1 is supplied with 2 × VDD. M4 is turned on in order to pass the voltage, and M5 is turned on in the section (2) to force VSS, and at this time, M4 is turned off to cut the current flowing from N7 to VSS. However, in order for M4 to pass a voltage of 2 × VDD, it is necessary to increase the N-well voltage of M4 to 2 × VDD. For this purpose, the PMOS transistor M1 is used. M1 is turned off and on in the sections (1) and (2), respectively, and when it is turned on, the voltage of N8 is passed through VB and is charged to C3 every time CK1 becomes VSS. That is, VB is boosted to 2 × VDD as time passes, and the potential of 2 × VDD can be passed through M4.

  On the other hand, in order to swing the boost clock signal DCK2 between VSS and 2 × VDD, DCK2 and N8 are connected across the PMOS transistor M7, and M8 is turned on in the section (1) to force VSS. M7 is turned off to cut the current flowing from N8 to VSS, and the NMOS transistor M8 is turned off in section (2). At this time, M4 is turned on to pass a voltage of 2 × VDD to DCK1. However, in order for M7 to pass a voltage of 2 × VDD, it is necessary to increase the N-well voltage of M7 to 2 × VDD. For this purpose, a PMOS transistor M6 is used. M6 is turned off and on in the sections (1) and (2), respectively, and when it is turned on, the voltage of N7 is passed through VB, and thereafter C3 is charged every time CK2 becomes VSS. That is, VB is boosted to 2 × VDD over time. Therefore, the N-well voltage of M4 becomes 2 × VDD so that M7 can pass the potential of 2 × VDD without forming a related parasitic circuit and without causing latch-up. become.

  In the present embodiment, it is possible to connect the N-wells of the PMOS transistors M4 and M6 and use a common capacitor C3. Further, after VB becomes 2 × VDD, M4 and M6 are alternately turned on and operate so as to compensate for the voltage drop of VB. Therefore, the voltage drop of VB is smaller than that in the case of the same configuration as in FIG. Can be negligible.

  In addition, even when the capacitor C3 is added, the capacity can be reduced, and the area can be reduced as compared with the case where the capacitor is individually provided as the voltage maintaining function. Further, in this case, M4 and M6 are alternately turned on at the time of rising, and the capacitor C3 is charged, so that the time until VB becomes 2 × VDD is shorter than in the case where each capacitor is individually provided.

  In FIG. 8, M1 and M4 and M6 and M7 are combined in a manner similar to the configuration in FIG. 4, but conversely, even if M1 and M7 and M6 and M4 are combined, the final circuit configuration Is the same.

  In the case of the circuit example of FIG. 6 described above, the timing at which VB is reduced as described with reference to FIGS. 4 and 5 is also different from each other in the two circuits, and by finely adjusting the phases of CK1 and CK2. , Can cancel each other. For example, at the timing at which M11 operates to lower the voltage of VB, M21 can generate the VB voltage, and can be operated to generate the VB voltage over the entire period. In this case, since the ability to generate a voltage is greater than the current value that causes the voltage drop, the voltage drop can be reduced to a level that can be substantially ignored.

  In the case of the circuit example of FIG. 8, the timing for lowering VB described with reference to FIGS. 4 and 5 can also be eliminated by adjusting the phase so that CK1 and CK2 do not simultaneously become high. Even when the inverter output of CK1 is CK2, the voltage drop can be halved by doubling the capacitance of the capacitor. Even in this case, both waves are rectified. Therefore, it is not necessary to increase the rise of VB. Therefore, as long as the voltage drop of 1/2 does not adversely affect the VB voltage, the VB voltage is generated in most of the time. Therefore, it is possible to avoid the decrease in VB due to noise or the like.

  As described above, in the second embodiment, the circuit is omitted, but the well bias voltage is set in the form of full-wave rectification using level-shifted clock signals that are in phase relations reversed to each other. Since it is generated, that is, the VB voltage is generated from each source voltage of the PMOS transistor that generates boosted clocks having different phases, it is possible to prevent a voltage drop that causes a problem. In addition, even when a capacitor having the same capacity as the capacitor C3 in FIG. 4 is added to the VB line, the capacitor can have the same capacity. In this case, the area is smaller than the case where the capacitors are individually provided, A boost clock with a short rise time and a small voltage drop can be output.

(Other explanation)
In the above description, a circuit configured on a P-type substrate having an N-well has been described as an example. However, the same idea is applied to an N-type having a P-well. Those skilled in the art will understand that the present invention can also be applied to a circuit formed on a substrate.

  As described above, in each embodiment of the clock booster circuit, the case where a MOS transistor is used as the constituent element has been described. It may be realized.

It is a figure which shows the structure of the two-phase clock booster circuit in the 1st Embodiment of this invention. It is a figure which shows the structure of the two-phase clock booster circuit in the 2nd Embodiment of this invention. It is a figure which shows the structure of the conventional clock booster circuit in the case of using a two-phase clock. FIG. 10 is a diagram illustrating a conventional clock booster circuit, and is a circuit diagram illustrating a clock voltage doubling circuit including a well bias voltage generator disclosed in Non-Patent Document 2. 5 is a timing chart showing how the conventional clock booster circuit shown in FIG. 4 operates. 1 is a diagram illustrating a clock booster circuit according to a first embodiment of the present invention. 3 is a timing chart showing how the clock booster circuit according to the first embodiment of the present invention operates. It is a figure which shows the clock booster circuit by 2nd Embodiment of this invention. 6 is a timing chart showing how the clock booster circuit according to the second embodiment of the present invention operates.

Explanation of symbols

M2, M3, M5, M8, M12, M13, M15, M22, M23, M25 NMOS transistors M1, M4, M6, M11, M14, M21, M24 PMOS transistors C1, C2, C3, C11, C12, C21, C22 capacitors CK, CK1, CK2 Clock DCK, DCK1, DCK2 Boost clock VB Well bias voltage

Claims (4)

A first clock booster circuit that outputs a boosted clock signal using a supplied basic clock signal as an input and includes a well bias voltage generator;
A second clock booster circuit having a configuration similar to that of the first clock booster circuit and outputting a boosted clock signal with a phase-inverted clock signal as an input to the basic clock signal;
An output of a well bias voltage generator in the first clock booster circuit and an output of a well bias voltage generator in the second clock booster circuit are connected. The supplied basic clock signal and the phase-inverted clock signal of the basic clock signal are input, and the first level shift clock signal and the phase-inverted clock signal obtained by level-shifting the basic clock signal in the direction of the boost side A clock level shift circuit for outputting a second level shift clock signal level shifted in the direction;
A first boost clock output circuit that outputs a clock signal that swings in a range of the boost side potential and ground potential of the first level shift clock signal;
A second boost clock output circuit that outputs a clock signal that swings in a range of the boost side potential and the ground potential of the second level shift clock signal;
A well bias voltage generator configured to include two MOS transistors that receive the two level shift clock signals and generate the voltage of the boost side potential in the form of full-wave rectification. A clock booster circuit. The supplied basic clock signal and the phase inverted clock signal of the basic clock signal are input, and the first level shifted clock signal obtained by level-shifting the basic clock signal in the boosting direction and the phase inverted clock signal are A clock level shift circuit for outputting a second level shift clock signal level-shifted in the boost side direction;
A first boost clock output circuit that outputs a clock signal that swings in a range between the boost side potential and the ground potential of the first level shift clock signal;
A well bias voltage generator configured to include two MOS transistors that receive the two level shift clock signals and generate the voltage of the boost side potential in the form of full-wave rectification. A clock booster circuit. The well bias voltage generator includes a capacitor between the output of the well bias voltage generator and the ground, and when the voltage of the boost side potential is no longer supplied from the two MOS transistors, 4. The clock booster circuit according to claim 1, wherein the voltage supplied to is substantially maintained. 5.

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