JP4788941B2 - Screen flicker mitigation circuit, image processing apparatus, and screen flicker mitigation control method - Google Patents

Description

  The present invention relates to a screen flicker mitigation circuit, an image processing apparatus, and a screen flicker mitigation control method for mitigating display flicker for an interlaced CRT monitor device.

In a conventional display circuit that outputs graphic data such as characters and lines superimposed on a video signal to an interlaced CRT monitor device, simply read and output the odd line graphic data in an odd field. In the case of the even field, the graphic data of the even line is read and output (for example, see Patent Document 1).
FIG. 9 is a schematic diagram of a scanning line of each field showing an interlaced CRT monitor device.
FIG. 10 is a graphic schematic diagram of a character T composed of a horizontal line and a vertical line in a conventional interlaced CRT monitor device.
FIG. 11 is a schematic diagram in which the graphic of FIG. 10 of the prior art is enlarged to scan lines and pixels, and odd fields and even fields that are originally displayed alternately are superimposed.
FIG. 12 is a schematic diagram of graphic output data of the character T in the odd field of the graphic of FIG. 10 of the prior art.
FIG. 13 is a schematic diagram of graphic output data of the character T in the even field of the graphic of FIG. 10 of the prior art.
The display method for superimposing and outputting graphic data such as characters and lines on a video signal to an interlaced CRT monitor device of the prior art using FIGS. explain.
As shown in FIG. 9, the scanning lines of each field in the interlaced CRT monitor apparatus display scanning lines 1, 3, 5 to 525 in the odd field, and scanning lines 2, in the next even field. 4, 6 to 524 are displayed.
As described above, in the interlace method, the odd line graphic data and the even line graphic data are simply displayed alternately. For this reason, as shown in FIG. 10, the graphic display of the character T composed of a horizontal line and a vertical line is displayed as shown in FIG. 12 in the odd field and as shown in FIG. 13 in the even field as the output data. Is displayed. As a result, the vertical line of T is displayed in both odd and even fields, although the displayed data is halved, but flickering is not noticeable. On the other hand, the horizontal line of T is displayed only in the odd field. Therefore, there has been a problem that the flickering occurs remarkably. In addition, since the graphic data in both the odd field and the even field is an image that blinks at 30 Hz, if the contrast between adjacent odd lines and even lines is significant, the graphic blinks at 30 Hz. In particular, there was a problem that it was difficult to see graphics composed only of horizontal lines.

FIG. 14 is a schematic diagram of graphic data showing a conventional screen flicker mitigation method.
As a method of alleviating display flickering caused by alternately displaying graphic data of odd lines and even lines, as shown in FIG. 14, a technique of displaying odd lines and even lines of graphic data two by two as shown in FIG. It is known.
JP-A-6-149195 (page 2-3)

In this way, even if the odd and even graphic data are displayed in the same two lines, the display flicker is eliminated, but the vertical resolution is halved, so the amount of information to be displayed is halved. There was a problem of being reduced.
In addition, when the background image and the graphic brightness are close, there is a problem that the graphic is buried in the image and cannot be seen.
The present invention has been made in view of such problems, and can reduce the flickering of the graphic display without reducing the vertical resolution, and the graphic can be buried even when the luminance of the video and the graphic is close. An object of the present invention is to provide a screen flicker mitigation circuit, an image processing apparatus, and a screen flicker mitigation control method capable of obtaining a screen free from any problem.

  In order to solve the above problem, the present invention is configured as follows.

According to the first aspect of the present invention, there is provided an address generation circuit for generating an address for specifying a display position of a pixel displayed on a display screen in order from left to right of pixels horizontally arranged on the display screen, and a plurality of the pixels A graphic memory for storing image data comprising: a plurality of pixels in one pixel row arranged in a line horizontally on the screen from the left to the right; a forward appears, and a graphic memory plurality of the pixel rows are sequentially displayed from top to bottom, the palette for outputting display data for the video signal output D / a converter interlaced in the screen flickering relaxation circuit in the display circuit having a memory and, to adjacent to the upper of the one pixel by subtracting the address of one pixel in the image data Address minus operation circuit for generating an address of a pixel, the address switching circuit for alternately outputting the graphic memory by switching the address of the pixel adjacent to the upper side of the address and the one pixel of the one pixel, the one and a pixel delay circuit for outputting a reference pixel delayed by one pixel data to the palette memory output from the graphic memory in accordance with the address of the pixel adjacent to the upper side of the pixel, the palette memory is the one pixels and a pixel comparison function is compared with the reference pixel, and outputs the to one pixel by the color converting the one pixel to be displayed when the true the D / a converter, the one in the pixel is false, besides the If reference pixels is true to the color conversion dropped the luminance according to preset brightness parameter the brightness level of the reference pixel Output to serial D / A converter, the one pixel is false, besides also the reference pixels but when the false and outputting the color converting the one pixel to be displayed on the D / A converter It is characterized by being.

  According to a second aspect of the present invention, in the image processing apparatus having an interlaced CRT monitor output circuit, the screen flicker mitigating circuit according to the first aspect is provided for the CRT monitor output circuit. It is said.

  According to a third aspect of the present invention, there is provided an image processing apparatus comprising an interlace CRT monitor output circuit and a non-interlace personal computer monitor output circuit as the monitor output circuit. A display circuit having a screen flicker mitigation circuit according to claim 1 is used for a CRT monitor output circuit of the type, and the screen flicker mitigation is used for the monitor output circuit for a non-interlace personal computer. A monitor output switching circuit for switching to use a display circuit having no circuit is provided.

Further, the invention according to claim 4, with respect to a CRT monitor device interlaced, the screen flicker mitigation control method of a display circuit configured to superimpose the image data composed of a plurality of pixels in the video signal, a pixel When an address to read out a pixel adjacent to the upper side of the one pixel, and generating the order from left to right aligned horizontally pixel on the display screen, adjacent to the upper of the one pixel and the one pixel a step of reading the pixels alternately, the steps of delaying by one pixel a pixel adjacent to the upper side of the one pixel, said the one pixel, delayed by one pixel a pixel adjacent to the upper side of the one pixel is a reference pixel, and performing a comparison of the steps the one pixel is when true for displaying the one pixel, the one pixel is false, besides, when the reference pixel is true, the brightness of the reference pixels As a step of displaying a screen flicker relaxation data, said one pixel is false, besides, the reference pixels also when false, as characterized by comprising the steps of: displaying the one pixel Yes.

  According to the first aspect of the present invention, the flickering of the graphic display can be alleviated without reducing the vertical resolution, and the lower right pixel is displayed as a shadow even when the brightness of the image and the graphic is close. Thus, it is possible to realize a screen flicker mitigation circuit that can be displayed on an interlaced CRT monitor without burying graphics.

  Further, according to the invention described in claim 2, the flickering of the graphic display can be alleviated without reducing the vertical resolution, and even when the video and the graphic are close in brightness, the lower right pixel is like a shadow. By displaying the image processing apparatus, it is possible to realize an image processing apparatus that can display on an interlaced CRT monitor without burying graphics.

  In addition, according to the third aspect of the present invention, it is possible to alleviate the flickering of the graphic display without reducing the vertical resolution, and the lower right pixel appears as a shadow even when the luminance of the video and the graphic is close. The display can be displayed on an interlaced CRT monitor without burying graphics, and a display circuit that does not have the screen flicker mitigation circuit is used for a non-interlaced personal computer monitor. By switching in such a manner, an image processing apparatus that can normally display graphics can be realized.

  According to the invention described in claim 4, it is possible to reduce the flickering of the graphic display without reducing the resolution in the vertical direction, and even when the luminance of the video and the graphic is close, the lower right pixel is like a shadow. By being displayed, a screen flicker mitigation control method that can be displayed on an interlaced CRT monitor without burying graphics becomes possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a display circuit including a screen flicker mitigating circuit according to a first embodiment of the present invention.
In FIG. 1, 21 is a graphic data display address generating circuit, 22 is an address minus arithmetic circuit, 23 is an address switching circuit, 24 is a graphic memory, 25 is a latch, 26 is a pixel delay circuit, 27 is a palette memory, 28 is a D / D A converter.
The present invention is different from the conventional display circuit as follows.
That is, the present invention includes an address minus operation circuit 22, an address switching circuit 23 that switches the display position address and the address on one line and outputs them alternately to the graphic memory 24, and delays the data on one line by one pixel . A screen flicker mitigation circuit comprising a pixel delay circuit 26 and a palette memory 27 with a built-in pixel comparison circuit for comparing the data on the scanning line with the data on one line is provided.

Hereinafter, the configuration of the display circuit including the screen flicker mitigating circuit and the operation of the screen flicker mitigating circuit according to the present embodiment will be described with reference to FIG.
The graphic data display address generation circuit 21 is a circuit that generates the address of the pixel at the arbitrary position X, and the address minus arithmetic circuit 22 subtracts the address of the pixel at the display position X to subtract the address of the pixel at the display position X. An arithmetic circuit that generates an address of an adjacent pixel , and an address switching circuit 23 switches an address of a pixel at the display position X and an address of an adjacent pixel on the pixel at the display position X and outputs the same to the graphic memory 24. It is.
After each of the pixels output from the graphic memory 24 held by the latch 25, a pixel of the display position X is directly input to the palette memory 27, the pixel adjacent to the upper side of a pixel of a display position X pixel delay circuit 26 after being delayed by one pixel through, as reference pixels, it is input to the palette memory 27.
The palette memory 27 has a built-in pixel comparison circuit that compares the pixel at the display position X with the reference pixel. When the pixel at the display position X is true, the color of the pixel at the display position X is converted to a D / A converter. If the pixel at the display position X is false and the reference pixel is true, the luminance level of the reference pixel is reduced according to a preset luminance parameter, and color conversion is performed, and output to the D / A converter 28. When the pixel at the display position X is false and the reference pixel is true, the pixel at the display position X is color-converted and output to the D / A converter 28.

FIG. 2 is a flowchart of the screen flicker mitigation method according to the first embodiment of the present invention.
Hereinafter, the procedure of the screen flicker mitigation control method of this embodiment will be described with reference to FIG.
An arbitrary display position X and a pixel readout address on one line are generated (step ST1), display data of the display position X and pixels on the one line are alternately read (step ST2), and one line of the display position X is displayed. the display data of the upper pixel one pixel delayed (step ST3), comparing the pixel data and one-pixel delay pixel data of the display position (step ST4a, b), the comparison result by displaying dropped luminance (step ST6 ).

FIG. 3 is an explanatory diagram of a method of comparing the pixel data on the scanning line and the pixel data on one line according to the first embodiment of the present invention.
In FIG. 3, 33 is display line data (A) at an arbitrary display position X, 34 is display data on one line, (B) is display data on the upper left of one pixel of data (A), and 35 is display. Output data obtained by comparing the data (A) and (B), 36 is pixel data with reduced luminance, 37 is original pixel data of the display line, and 38 is pixel data delayed by one pixel.
FIG. 4 is a schematic diagram of the graphic display of the character T in the odd field according to the first embodiment of the present invention.
FIG. 5 is a schematic diagram of the graphic display of the character T in the even field showing the first embodiment of the present invention.
FIG. 6 is a schematic diagram of one frame of graphic output data in which an odd field and an even field which are originally displayed alternately are overlapped to show the first embodiment of the present invention. 3 to 6, the display data of the pixels indicated by diagonal lines indicates that the luminance is reduced according to the luminance parameter set in advance.
Hereinafter, details of comparison and display operations of the present embodiment will be described with reference to FIGS.
As shown in FIG. 3, display line data 33 (A) at an arbitrary display position X and display data (B) at the upper left of one pixel at display position X, that is, display data 34 at the display position X1 line are converted into one pixel. Compared with the delayed data 38 (steps ST4a, 4b), when (A) is true, the data 37 of (A) is displayed at the display position X (step ST5), (A) is false and (B) When is true, the data 36 with the reduced brightness of (B) is displayed at the display position X (step ST6), and when both (A) and (B) are false, the data 37 of (A) is displayed at the display position X. (step ST7). In this way, the graphic output data in the odd field shown in FIG. 4 and the graphic output data in the even field shown in FIG. 5 are obtained for the character T. When the odd-numbered field and the even-numbered field, which are originally displayed alternately, are overlapped and displayed as one frame of graphic output data, the result is as shown in FIG.

  As described above, the screen flicker mitigation circuit and the screen flicker mitigation control method according to the present embodiment compare pixel data at an arbitrary display position with pixel data adjacent to the upper left of the pixel, and display the pixel data at the display position. When is true, the original pixel data is displayed, and when the pixel data at the display position is false, and when the upper left pixel data is not false, the luminance of the upper left pixel data is reduced and this is used to reduce the screen flicker. As shown in FIG. 6, the low-brightness horizontal line is displayed as a shadow as shown in FIG. 6 even in the horizontal line of the letter T in which the screen flickers remarkably occur in the conventional technique. Thus, flickering is alleviated and the graphic is not buried in the background video even when the luminance of the graphic is close to that of the background video.

FIG. 7 is a block diagram of an image processing apparatus showing a second embodiment of the present invention.
In FIG. 7, 1 is an image processing apparatus, 2 is an interlaced CRT monitor output circuit, and 3 is a screen flicker mitigation circuit.
The image processing apparatus of the second embodiment shown in FIG. 7 is different from the prior art in that the image processing apparatus 1 of the present embodiment outputs the screen flicker mitigation circuit 3 described in the first embodiment to an interlaced CRT monitor output. It is a point provided for the circuit 2.

  Since the image processing apparatus 1 according to the present embodiment includes the screen flicker mitigating circuit 3 as described above, the flickering of the graphic display can be mitigated without lowering the vertical resolution, and the video and the graphic can be reduced. Even when the luminance is close, the lower right pixel is displayed as a shadow, so that the graphic can be displayed on the interlaced CRT monitor 2 without being buried.

FIG. 8 is a block diagram of an image processing apparatus showing a third embodiment of the present invention. Note that the description of the same constituent elements as those in FIG. 7 which is the second embodiment is omitted, and only different points will be described.
In FIG. 8, 4 is a non-interlace personal computer monitor output circuit, 5 is a monitor output switching circuit, and 10 is an image processing apparatus.
Hereinafter, the difference between the image processing apparatus of the present embodiment and the prior art will be described with reference to FIG.
That is, the image processing apparatus 10 of the present embodiment includes an interlaced CRT monitor output circuit 2 and a non-interlaced personal computer monitor output circuit 4. The display circuit having the screen flicker mitigation circuit 3) described in the first embodiment is used, and the display circuit having no screen flicker mitigation circuit 3 described in the first embodiment is used for the non-interlace monitor 4. The monitor output switching circuit 5 that performs switching operation to be used is provided.

  Since the image processing apparatus 10 according to the present embodiment has the above-described configuration, it is possible to alleviate the flickering of the graphic display without reducing the vertical resolution, and the lower right pixel even when the luminance of the video and the graphic is close to each other. Can be displayed on the interlaced CRT monitor 2 without being buried, and the screen flicker mitigating circuit 3 for the noninterlaced personal computer monitor 4 is displayed. A graphic can be normally displayed by switching to use a display circuit that does not have the.

  The screen flicker mitigation circuit, the image processing apparatus, and the screen flicker mitigation control method of the present invention can be widely applied to all products having an interlaced CRT monitor output circuit.

1 is a configuration diagram of a display circuit including a screen flicker mitigation circuit according to a first embodiment of the present invention. The flowchart of the screen flicker mitigation method showing the first embodiment of the present invention. Explanatory drawing of the comparison method of the pixel data of the scanning line and the pixel data on one line which show 1st Example of this invention Schematic diagram of graphic display of character T in odd field showing the first embodiment of the present invention Schematic diagram of graphic display of character T in even field showing first embodiment of the present invention Schematic diagram of graphic output data of one frame in which odd fields and even fields that are originally displayed alternately are overlapped, showing the first embodiment of the present invention. Configuration diagram of an image processing apparatus showing a second embodiment of the present invention. Configuration diagram of an image processing apparatus showing a third embodiment of the present invention. Schematic diagram of scanning lines in each field showing an interlaced CRT monitor device Graphic schematic diagram of a letter T composed of a horizontal line and a vertical line in a conventional interlaced CRT monitor device FIG. 10 is a schematic diagram in which the graphic of FIG. 10 of the prior art is enlarged to scan lines and pixels and an odd field and an even field which are originally displayed alternately are superimposed. Schematic diagram of display data of character T in odd field of graphic in FIG. 10 of the prior art Schematic diagram of display data of character T in even field of graphic of FIG. 10 of the prior art Schematic diagram of graphic data showing the conventional screen flicker mitigation method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 10 Image processing device 2 Interlace type CRT monitor output circuit 3 Screen flicker mitigation circuit 4 Non-interlace type personal computer monitor output circuit 5 Monitor output switching circuit 21 Graphic data display address generation circuit 22 Address minus arithmetic circuit 23 Address switching circuit 24 Graphic memory 25 Latch 26 Pixel delay circuit 27 Palette memory 28 D / A converter 33 Display data (A) at an arbitrary display position X
34 Display data on the upper left of one pixel (B)
35 Output data obtained by comparing display data (A) and (B) 36 Pixel data with reduced brightness 37 Original pixel data of display line 38 Pixel data delayed by one pixel

Claims (4)

An address generating circuit for generating an address for specifying a display position of the pixel to be displayed on the display screen, in order from left to right aligned horizontally pixel on the display screen,
A graphic memory for storing image data composed of a plurality of the pixels, wherein the plurality of pixels in one pixel row in which the image data is allocated to the address space of the graphic memory are arranged in a line horizontally on the screen. a forward displayed from left to right, and a graphic memory plurality of the pixel rows are sequentially displayed from top to bottom,
A pallet memory for outputting display data for the interlaced video signal output D / A converter, the screen flickering relaxation circuit in the display circuit having a
Address minus operation circuit for generating an address of a pixel adjacent to the upper side of the one pixel by subtracting the address of one pixel in the image data,
An address switching circuit for switching and outputting an address of a pixel adjacent to the upper side of the address and the one pixel of the one pixel alternately in the graphic memory,
And a pixel delay circuit for outputting a reference pixel delayed by one pixel data to the palette memory output from the graphic memory in accordance with the address of the pixel adjacent to the upper side of the one pixel,
The palette memory has a pixel comparison function for comparing the one pixel with the reference pixel, and when the one pixel is true, color-converts the one pixel to be displayed and performs the D / A conversion. output to vessel, the one pixel is false, besides the D / a conversion by the color conversion dropped the luminance according to preset brightness parameter the brightness level of the reference pixels when the reference pixels is true and outputs to the vessel, and characterized in that said one pixel is of false, still and the reference when the pixel is also false and outputting the color converting the one pixel to be displayed on the D / a converter Screen flicker mitigation circuit to do. The image processing apparatus provided with a CRT monitor output circuit interlaced,
An image processing apparatus comprising the screen flicker mitigating circuit according to claim 1 for the CRT monitor output circuit. As a monitor output circuit, and the CRT monitor output circuit interlaced,
An image processing apparatus including a personal computer monitor output circuit of non-interlaced, and,
Said for the CRT monitor output circuit interlaced, using the display circuit having a screen flickering relaxation circuit of claim 1, it is for the personal computer monitor output circuit of the non-interlaced, wherein An image processing apparatus comprising a monitor output switching circuit that switches to use a display circuit that does not have a screen flicker mitigation circuit. In a screen flicker mitigation control method for a display circuit that outputs image data composed of a plurality of pixels superimposed on a video signal for an interlaced CRT monitor device,
And one pixel, and generating a pixel adjacent to the upper side of the one pixel, the address for reading, in order from left to right aligned horizontally pixel on the display screen,
A step of reading a pixel adjacent to the upper side of the one pixel and the one pixel alternately,
A step of delaying by one pixel a pixel adjacent to the upper side of the one pixel,
And performing said the one pixel, the reference pixel delayed by one pixel a pixel adjacent to the upper side of the one pixel, a comparison of,
A step wherein one pixel when true for displaying the one pixel,
Wherein one pixel is false, besides, said when reference pixels is true, drop the brightness of the reference pixel, and displaying the screen flicker relaxation data,
When the one pixel is false and the reference pixel is also false, displaying the one pixel;
A screen flicker mitigation control method characterized by comprising: