JP4794809B2 - Patterning method for manufacturing integrated circuits - Google Patents

Description

BACKGROUND OF THE INVENTION
[0001]
The present invention relates to a patterning method for manufacturing integrated circuits. More particularly, the present invention relates to a patterning method capable of minimizing restrictions in the photolithography process and etching process.
[Prior art]
[0002]
As the dimensions of semiconductor devices become smaller, the demand for resolution has increased accordingly. Since the resolution of the photoengraving process depends on the wavelength of the light source used for photoelectric exposure, the mask patterns obtained by performing the photoengraving (or etching) process are separated from each other by a minimum distance. Furthermore, if the mask is used as an etching mask, reducing the gap or opening size in the etching mask will have some detrimental effect on the underlying layer to be etched.
[0003]
Currently, the photoengraving process for patterning the photoresist layer is set so that the gap or opening in the photoresist layer has a minimum aspect ratio of 3: 1. However, the photoresist layer must also have a sufficient thickness to withstand etching. Therefore, device minimization is difficult to achieve by directly reducing the photoresist layer thickness.
[0004]
In order to reduce the thickness of the photoresist layer, a hard mask layer manufactured using a material having a high etching resistance is often used as an etching mask. In other words, the method includes the steps of patterning a hard mask layer using a photoresist layer and then patterning a material layer beneath it using the hard mask layer as an etching mask. Since the etching is selectively performed between the hard mask layer and the lower layer material layer, a thinner hard mask layer can be used. As a result, the thickness condition of the photoresist layer is relaxed, and the restriction of the photolithography process is relaxed to some extent. Nevertheless, this method has major drawbacks. First, the material forming the hard mask layer must be uniquely selected based on the material properties of the material layer to be patterned. Thus, different hard mask layers must be used to pattern material layers made of different materials, thus increasing process design complexity. Second, since the hard mask layer and the photoresist layer are made of two different materials, the photoresist layer and the hard mask layer must be removed in at least two separate steps, thereby reducing manufacturing complexity. Increase and become more expensive.
[0005]
[Problems to be solved by the invention]
Accordingly, one object of the present invention is to provide a patterning method for manufacturing integrated circuits that can alleviate some of the limitations in the photolithography process.
[0006]
A second object of the present invention is to provide a patterning method for manufacturing an integrated circuit that overcomes some of the disadvantages caused by using a hard mask layer in a conventional manner.
[0007]
[Means for Solving the Problems]
In order to achieve these and other advantages, and based on the objectives of the present invention, the present invention provides a patterning method for manufacturing integrated circuits, as implemented and generally described herein. First, a material layer is formed on the substrate, and then a patterned photoresist layer is formed on the material layer. When the photoresist layer is patterned in a photoengraving process, the thickness of this photoresist layer is thin enough to relax the restriction. The dimension of the patterned photoresist is a critical dimension. Next, form (here x, y, m, n are integers) formula C _x F _y and CH _m F _n liner by plasma chemical vapor deposition using a reactive gas having on the surface of the photoresist layer However, the height of this liner is greater than its width. In other words, the thickness of the liner on the top surface of the photoresist layer exceeds the thickness of the liner on the sidewalls of the patterned photoresist layer. In the present invention, the liner is made of a polymer compound formed by, for example, plasma enhanced chemical vapor deposition (PECVD). Thereafter, liners on the sidewalls of the photoresist layer is removed. An etching operation is performed to pattern the material layer by using the remaining liner as an etching mask. Finally, the liner and photoresist layer are removed together in a single step .
[0008]
The present invention provides another patterning method for manufacturing integrated circuits. First, a material layer is formed on the substrate, and then a photoresist layer is formed on the material layer. The photoresist layer has a thickness sufficient to alleviate the limitations of photolithography. Furthermore, the dimensions of the photoresist layer are smaller than the target critical dimension. Thus, the liner is formed on the photoresist layer, but the size of the liner on the photoresist layer matches the target critical dimension. In the present invention, the liner is a polymer compound and is formed, for example, by plasma enhanced chemical vapor deposition (PECVD). Thereafter, the liner on the sidewall of the photoresist layer is removed. By using the remaining liner as an etching mask, an etching operation is performed and the material layer is patterned. Finally, the liner and photoresist layer are removed together.
[0009]
In the present invention, a thinner photoresist layer is produced, which alleviates the limitations in photolithography for device miniaturization. Although the photoresist layer is too thin to withstand etching, the liner actually acts as an etching mask rather than the photoresist layer. This method therefore alleviates the limitations in the photolithography process and at the same time miniaturizes the device.
[0010]
Furthermore, the liner on the surface of the photoresist layer is made from a polymer compound similar to the organic polymer material used for the photoresist layer. Thus, unlike conventional methods where a hard mask layer must be uniquely selected for the selected material layer, the liner can be used extensively as an etching mask for multiple material layers.
[0011]
In addition, the liner and photoresist layers are made from similar types of organic polymer compounds. Unlike conventional methods where the photoresist layer and hard mask layer must be removed in separate steps, the photoresist layer and liner can be removed together after the material layer is patterned.
[0012]
The foregoing general description and the following detailed description are exemplary and further descriptions of the invention are intended to be disclosed in the claims.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.
[0014]
1A through 1D are schematic cross-sectional views illustrating a sequence of steps for performing an integrated circuit pattern according to one preferred embodiment of the present invention. As shown in FIG. 1A, the material layer 102 is formed on the substrate 100. The material layer 102 is a dielectric layer (for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer) or a conductor layer (for example, a metal layer or a polysilicon layer). A patterned photoresist layer 104 is formed on the material layer 102. The thickness of the photoresist layer 104 is thin enough to increase resolution in the photolithography process when this photoresist layer is patterned.
[0015]
A liner 106 is formed on the surface of the photoresist layer 104 as shown in FIG. 1B. The liner 106 has a height “a” greater than its width “b”. In other words, the thickness of the liner 106 on the surface of the photoresist layer 104 is considerably larger than the thickness of the liner 106 on the sidewall of the photoresist layer 104.
[0016]
In this embodiment, the liner 106 is made of, for example, a polymer material. The liner 106 is formed, for example, by performing plasma enhanced chemical vapor deposition (PECVD). In PECVD, chemical formula _C x _{F y} and _CH m _{F n} (here x, y, m, n is an integer) the reaction gas having to be used. In particular, PECVD is for example difluoro-methane (CH ₂ F ₂ ) or a mixture of difluoro-methane (CH ₂ F ₂ ) and octo-fluorobutane (C ₄ F ₈ ) or difluoro-methane (CH ₂ F ₂ ) and tri It is carried out using a reaction gas comprising a mixture with fluoro-methane. PECVD is performed at a pressure rating of 1-100 mTorr with a power rating set between 500-2000 W, and a bias voltage of 0-400 V is often applied during the deposition process. The rate of vapor deposition is, for example, 600 to 600 / min. Also certain argon (Ar), carbon monoxide (CO), oxygen (O ₂ ) and nitrogen (N ₂ ) may be added to the reaction gas during PECVD.
[0017]
As shown in FIG. 1C, the liner 106 is processed to remove the liner 106 from the sidewalls of the photoresist layer 104. The processing of liner 106 includes applying a plasma to etch a layer of material from liner 106. The original outline of the liner 106 before plasma treatment is indicated by a dashed outline 108. In plasma processing, a limited layer of liner material on top of the photoresist layer 104 is also removed from the liner material trimmed from the sidewalls of the photoresist layer 104. Since the liner “a” height “a” is significantly greater than the liner width “b” on the sidewalls of the photoresist layer 104, the remaining liner 106 above the photoresist layer 104 after plasma treatment can still withstand etching. The thickness is sufficient.
[0018]
Thereafter, using the trimmed liner 106 as an etching mask, an etching operation is performed to pattern the material layer 102a. Finally, liner 106 and photoresist layer 104 are removed to the structure shown in FIG. 1D. Because liner 106 and photoresist layer 104 are made of similar organic polymer materials, liner 106 and photoresist layer 104 can be removed in a single step.
[0019]
In this embodiment, the photoresist layer 104 is made thin for the purpose of relaxing the limitations in the photolithography process resulting from the patterning of the thick photoresist layer 104. Although the photoresist layer 104 is too thin for subsequent etching, in practice, the liner 106 rather than the photoresist layer 104 is used as an etch mask to pattern the material layer 102. Accordingly, the present invention relaxes the limitations in photolithography and etching to some extent and reduces the device dimensions associated therewith.
[0020]
2A to 2C are schematic cross-sectional views illustrating a sequence of steps for performing integrated circuit patterning according to another preferred embodiment of the present invention. As shown in FIG. 2A, a material layer 202 is formed on the substrate 200. The material layer 202 is a dielectric layer (for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer) or a conductor layer (for example, a metal layer or a polysilicon layer). A patterned photoresist layer 204 is formed on the material layer 202. The thickness of the photoresist layer 204 is thin enough to increase resolution in the photolithography process when the photoresist layer is patterned. Further, the width of the photoresist layer 204 is smaller than the critical dimension “c” of the device.
[0021]
A liner 206 is formed on the surface of the photoresist layer 204 as shown in FIG. 2B. The liner 206 is manufactured to a width that approximately matches the critical dimension “c” of the device. In other words, the width of the liner 206 preferably matches the critical dimension “c” of the device.
[0022]
In this embodiment, the liner 206 is, for example, a polymer material. The liner 206 is formed by, for example, plasma enhanced chemical vapor deposition (PECVD). In PECVD, chemical formula _C x _{F y} and _CH m _{F n} (here x, y, m, n is an integer) the reaction gas having to be used. Since a process using PECVD is used to form the liner used in the first embodiment, the detailed description will not be repeated here.
[0023]
Thus, using the trimmed liner 206 as an etch mask, etching is performed and the material layer 202 is patterned into the material layer 202a. Finally, the liner 206 and the photoresist layer 204 are removed to form a structure as shown in FIG. 2C . Since La Inert 206 and the photoresist layer 204 is made from the same induced polymeric material, the liner 206 and the photoresist layer 204 can be removed together in a single step.
[0024]
In the second embodiment described above, the photoresist layer 204 is made thin in order to alleviate the limitations in the photolithography process due to the patterning of the thick photoresist layer 204. Although the photoresist layer 204 is too thin to withstand the subsequent etching process, in practice, the liner 206 rather than the photoresist layer 204 is used as an etching mask to pattern the material layer 202. Accordingly, the present invention relaxes the limitations in photolithography and etching to some extent and reduces the device dimensions associated therewith. Further, the width of the liner 206 is also made to match the critical dimension “c” of the device. Since the critical dimensions of semiconductor devices are very important in semiconductor manufacturing, a number of methods for controlling the critical dimensions have been developed. In the present invention, the critical dimensions of the device are controlled by the growth of the liner 206. This method not only controls the critical dimension but is easy to implement.
[0025]
【The invention's effect】
In summary, the main advantages of the present invention are:
1. The thin photoresist layer is used to alleviate the limitations during the photoengraving process associated with device scaling. Although the thickness of the photoresist layer is not sufficient to withstand the subsequent etching process here, the liner has an etching resistance in the patterning process of the material layer. Therefore, the present invention can alleviate the restrictions of the photoengraving process and the etching process to some extent, and can reduce the device size.
2. The liner on the side of the photoresist layer is made from a polymer compound similar to the organic polymer material used for the photoresist layer. Thus, unlike conventional methods where the hard mask layer must be carefully selected to match the material layer, the liner can be used as an etch mask for more material layers.
3. Liners and photoresist layers are made of similar types of organic polymer compounds. Unlike conventional methods where the photoresist layer and hard mask layer must be removed in a separate step, the photoresist layer and liner can be removed together after the material layer has been patterned.
[0026]
It will be readily apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope or concept of the invention. As indicated above, the present invention is intended to include modifications and variations of the present invention which fall within the scope of the following claims and their equivalents.
The accompanying drawings provide a further understanding of the invention and are included to constitute and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
[Brief description of the drawings]
FIG. 1A is a schematic cross-sectional view illustrating a process of performing a pattern of an integrated circuit according to one preferred embodiment of the present invention.
FIG. 1B is a schematic cross-sectional view illustrating a process of performing an integrated circuit pattern according to one preferred embodiment of the present invention.
FIG. 1C is a schematic cross-sectional view illustrating a process of performing an integrated circuit pattern according to one preferred embodiment of the present invention.
FIG. 1D is a schematic cross-sectional view illustrating a process of performing an integrated circuit pattern according to one preferred embodiment of the present invention.
FIG. 2A is a schematic cross-sectional view illustrating a process of performing patterning of an integrated circuit according to another preferred embodiment of the present invention.
FIG. 2B is a schematic cross-sectional view illustrating a process of performing patterning of an integrated circuit according to another preferred embodiment of the present invention.
FIG. 2C is a schematic cross-sectional view illustrating a process of performing patterning of an integrated circuit according to another preferred embodiment of the present invention.
[Explanation of symbols]
100 Substrate 102 Material Layer 102a Material Layer 104 Patterned Photoresist Layer 106 Liner 108 Dashed Outline 200 Substrate 202 Material Layer 202a Material Layer 204 Patterned Photoresist Layer 206 Liner

Claims (1)

Preparing a substrate;
Forming a material layer on the substrate;
Forming a patterned photoresist layer on the material layer;
Chemical formula C _x F _y and CH _m F _n (here x, y, m, n are integers) photoresist layer height by plasma chemical vapor deposition using a reactive gas larger liner than its width with Forming on the surface of the substrate;
Removing the liners located on the side wall of the photoresist layer by processing the liner;
Performing an etching operation to pattern the material layer using a liner as an etching mask;
Removing the liner and the photoresist layer in a single step;
A patterning method for manufacturing an integrated circuit comprising:

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