JP4797644B2 - Clamp circuit - Google Patents

Description

  The present invention relates to a clamp circuit that limits the amplitude of an input signal voltage and outputs the same to an integrated circuit, and more particularly to a clamp circuit that suppresses current consumption with little signal delay.

  An integrated circuit such as a signal conditioner for taking in external data incorporates a multiplexer having an analog switch composed of a CMOS transistor or the like, a programmable gain amplifier, and the like. In this case, a protection circuit such as a clamp circuit is provided in the input unit in order to protect the integrated circuit even when an excessive input voltage from a measuring instrument or the like is supplied.

FIG. 5 is a block diagram showing an example of a conventional clamp circuit.
In the figure, a signal input terminal VIN to which external data is input is connected in series with two inverter circuits U1 and U2 via a clamp circuit 10 including a resistor R1 and a Zener diode D1, and an inverter circuit U2 in the subsequent stage. The binary signals “1” and “0” are output from the signal output terminal VOUT.

  In such a clamp circuit 10, when the signal voltage Vi of external data is smaller than the breakdown voltage Vz of the Zener diode D1, the signal voltage applied to the signal input terminal VIN is applied as it is as the input voltage V1 of the inverter circuit U1. . On the other hand, when the signal voltage at the signal input terminal VIN becomes larger than the breakdown voltage Vz, the Zener diode D1 breaks down to V1 = Vz, so that the input voltage V1 does not exceed the breakdown voltage Vz. Therefore, when there is a possibility that the signal voltage Vi of the external data applied to the signal input terminal VIN exceeds the voltage value allowed as the input voltage V1 to the integrated circuit, the clamp circuit 10 is connected to the inverter circuit U1, By providing it between U2 and the signal input terminal VIN, it is possible to protect the integrated circuit at the subsequent stage from an excessive input voltage.

As an example of a protection circuit for this type of integrated circuit, Patent Document 1 discloses an input voltage clamp circuit with a wide normal input range, a stable clamping operation, and low power consumption. This input voltage clamp circuit is an input voltage clamp circuit that clamps an input voltage to an integrated circuit so that it is equal to or lower than a positive first power supply voltage or a negative second power supply voltage of the integrated circuit. The first voltage control means for clamping the input voltage to a voltage not lower than the first predetermined voltage and not higher than the first power supply voltage to be input to the integrated circuit, and a second constant negative in the input voltage. In the case where the voltage is smaller than the voltage, the second voltage control means for clamping the input voltage to a voltage not lower than the second power supply voltage and not higher than the second constant voltage to input the integrated circuit is provided.
JP 2001-160719 A (paragraph numbers [0002]-[0024], FIGS. 1 and 4)

  However, in the conventional clamp circuit 10 shown in FIG. 5, when the signal voltage at the signal input terminal VIN is higher than the breakdown voltage Vz of the Zener diode D1, a current constantly flows through the resistor R1, which is useless. There was a problem that power consumption occurred. This current value can be reduced by increasing the resistance R1, but in this case, the time required to drive the input capacitance of the inverter circuit U1 increases, and the delay time of the input signal increases due to the provision of the clamp circuit 10. There was a risk.

  Further, in the input voltage clamp circuit described in Patent Document 1, the first voltage control means includes a first operational amplifier that outputs a first control voltage when the input voltage is greater than a first constant voltage, and a first control voltage. And a first output transistor that outputs a voltage not lower than the first constant voltage and not higher than the first power supply voltage, and the second voltage control means has a second control voltage when the input voltage is smaller than the second constant voltage. And a second output transistor for inputting a second control voltage and outputting a voltage not lower than the second power supply voltage and not higher than the second constant voltage. It has been difficult to reduce power consumption in the amplifier.

  The present invention has been made in view of these points, and an object of the present invention is to provide a clamp circuit with a short delay time and low current consumption.

In the present invention, in order to solve the above problem, in a clamp circuit that limits the amplitude of the input signal voltage and outputs a signal in a predetermined voltage range, the gate terminal is connected to the first reference power supply, and the drain terminal is the signal input. A three-terminal clamp element directly connected to a terminal; an even number of inverter circuits connected in series between a source terminal and a signal output terminal of the three-terminal clamp element; and the source terminal of the three-terminal clamp element And a resistor element having one end connected to a connection point of the inverter circuit and the other end connected to a second reference power supply.

  According to the present invention, even when external data from a measuring instrument or the like is supplied with an excessive input voltage, a delay in response time of an output signal can be shortened and a clamp circuit with low current consumption can be provided.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a clamp circuit according to the first embodiment.

  In FIG. 1, a clamp circuit 11 is provided as a protection circuit for a signal input terminal VIN to which external data is supplied, and an input voltage Vi of external data is clamped by the clamp circuit 11 to become an output voltage V1, which is connected in series 2 The output voltage Vo is output to the signal output terminal VOUT through a buffer including two inverter circuits U1 and U2.

  The clamp circuit 11 includes an N-channel MOSFET Qn1 whose substrate terminal is grounded and a resistor R1. MOSFET Qn1 has its drain terminal connected to signal input terminal VIN, and its source terminal connected to the input side of inverter circuit U1. The gate terminal of the MOSFET Qn1 is connected to the gate bias signal input terminal Vb and supplied with a gate bias signal. The resistor R1 has one end connected to a connection point between the MOSFET Qn1 and the inverter circuit U1, and the other end grounded.

  In the clamp circuit 11 configured as described above, when the input voltage Vi of the external data is sufficiently low, the MOSFET Qn1 is conductive (operates in the non-saturated region). Now, assuming that the on-resistance of the MOSFET Qn1 is negligible compared to the resistor R1, the output voltage V1 is equal to the input voltage Vi. On the other hand, when external data is supplied to the signal input terminal VIN as an input voltage Vi having a magnitude exceeding a specified value, the MOSFET Qn1 operates as a source follower having the output voltage V1 as a source potential. Now, assuming that the potential of the gate bias signal is Vg and the threshold voltage of the MOSFET Qn1 is Vth1, the potential output to the inverter circuit U1 does not exceed (Vg−Vth1). Therefore, by setting the potential Vg of the gate bias signal to an appropriate value, even when the input voltage Vi of the external data increases, a signal having a limited amplitude is output to the integrated circuit via the inverter circuits U1 and U2. it can.

  Note that, in the clamp circuit 11 described above, a current of V1 / R1 is constantly consumed, so it is preferable to set the resistance value of the resistor R1 as large as possible. In this case, even if a large value is used as the resistor R1 of the clamp circuit 11, in the region where the input signal to the inverter circuit U1 changes (not clamped), the inverter circuit U1 is connected through the MOSFET Qn1 having a low on-resistance. Since it is driven, it can respond to the external data supplied to the signal input terminal VIN with a small delay.

  As described above, the clamp circuit 11 according to the first embodiment is a clamp circuit that outputs a signal in a predetermined voltage range by limiting the voltage amplitude of external data supplied to an integrated circuit or the like, and the gate terminal is a gate bias signal input terminal. A gate bias signal connected to Vb and serving as a first reference power supply is supplied, a drain terminal connected to the signal input terminal VIN, and a source terminal connected to the signal output terminal VOUT via the two inverter circuits U1 and U2. The channel type MOSFET Qn1 and a resistor R1 having one end connected to a connection point between the source terminal of the MOSFET Qn1 and the signal output terminal VOUT and the other end grounded, are excessively large on the upper side of the voltage amplitude of the input voltage Vi. The input is limited to protect the integrated circuit at the subsequent stage. As described above, an increase in delay time due to the provision of the clamp circuit 11 can be reduced, and current consumption by the clamp circuit 11 itself can be reduced.

  The clamp circuit 11 according to the first embodiment has been described with respect to a configuration in which the input voltage Vi is clamped and converted into a limited amplitude signal when the voltage amplitude of the external data exceeds the high potential side. A P-channel MOSFET Qp1 is used instead of the N-channel MOSFET Qn1 constituting the circuit 11, and the other end of the resistor R1 is connected to a high-potential reference power supply (for example, a high-potential-side power supply of the integrated circuit or the gate bias signal input terminal described above). Vb, etc.), and the gate of the P-channel MOSFET Qp1 is connected to a low-potential reference power source such as a ground potential, thereby clamping the input voltage Vi below the lower limit of the voltage amplitude and limiting the underinput. Is also possible.

(Embodiment 2)
FIG. 2 is a block diagram showing a clamp circuit according to the second embodiment.
The clamp circuit 12 of FIG. 2 is configured in combination with the latch circuit 13 when the target external data is a binary signal of “1” and “0”. The clamp circuit 11 according to the first embodiment shown in FIG. 1 can be applied to analog signal clamping, but the clamp circuit 12 shown in FIG. 2 can be applied only to binary signals. Although the clamp circuit 12 is not applicable to analog signal clamping, it has the advantage of not consuming current in a steady state. The clamp circuit 12 includes an N-channel MOSFET Qn1 and a resistor R2. The gate terminal of the MOSFET Qn1 is connected to the gate bias signal input terminal Vb, the drain terminal is connected to the signal input terminal VIN, and the source terminal is the inverter circuit U1. Is connected to the input side. The resistor R2 is connected in parallel with the two-stage inverter circuits U1 and U2 connected in series between the source terminal of the MOSFET Qn1 and the signal output terminal VOUT. That is, the latch circuit 13 is configured by the inverter circuits U1 and U2 and the resistor R2 that connects the input terminal of the first stage and the output terminal of the final stage as a feedback resistor.

  In the clamp circuit 12 configured as described above, when the input voltage Vi of the external data is the ground potential, the output voltage V1 and the output voltage Vo of the signal output terminal VOUT are both equal to the ground potential, and the resistor R2 Current does not flow. On the other hand, when the external data becomes the input voltage Vi having a magnitude exceeding the specified value, the power supply voltage of the latch circuit 13 is output to the signal output terminal VOUT. In this case, by setting the potential Vg of the gate bias signal to an appropriate value, the MOSFET Qn1 is cut off (V1 = VOUT in this state), and the resistor R2 has a steady current as in the first embodiment. Since there is no flow, unnecessary power consumption is eliminated. Further, if the inverter circuits U1 and U2 are formed of CMOS, the inverter circuits U1 and U2 do not consume current.

Next, a specific embodiment of the above-described clamp circuit will be described.
FIG. 3 is a circuit diagram showing an example of the clamp circuit according to the second embodiment.
Here, the power supply voltage VDD is applied as a gate bias signal to the gate terminal of the MOSFET Qn1, and its substrate terminal is grounded. Further, as MOSFETs constituting the inverter circuits U1 and U2, a first CMOS circuit including an N-channel MOSFET Qn2 and a P-channel MOSFET Qp2 connected in series between the power supply voltage VDD and the ground, and an N-channel MOSFET Qn3 And a second CMOS circuit composed of a P-channel type MOSFET Qp3 are cascade-connected, and a resistor R2 is used as a feedback resistor.

  Each of these MOSFETs Qn1, Qn2, Qn3, Qp2 and Qp3 represents the device size (ratio of gate width to gate length, W μm / L μm) by the numbers shown in the figure.

  Here, since the gate potential of the MOSFET Qn1 is fixed to the power supply voltage VDD, a special circuit for generating a gate bias signal is not required. When the threshold voltage of the MOSFET Qn1 is Vth1, the threshold value of the latch circuit 13 needs to be sufficiently lower than (VDD−Vth1). The threshold voltage of the latch circuit 13 can be adjusted to some extent by changing the device sizes of the MOSFETs Qn2 and Qp2 constituting the first CMOS circuit. For example, if the gate width W of the MOSFET Qn2 is set large, the threshold value can be set low.

  FIG. 4 is a voltage waveform diagram showing simulation voltage values at various parts in the clamp circuit of FIG. In FIG. 4, the waveform indicated by symbol Δ is the input voltage Vi, the waveform indicated by symbol ■ is the output voltage Vo, and the waveform indicated by symbol x is the output voltage V1. The resistance value of the resistor R2 was 100 kΩ.

  Now, in the clamp circuit in which the clamp voltage is set by the power supply voltage VDD (= 5V), external data that changes in the range of 0V to 10V is supplied as the input voltage Vi to the signal input terminal VIN. When the input voltage Vi changes, the output voltage V1 of the clamp circuit 12 is also gradually regulated from 0V to the power supply voltage VDD and rises to 5V. At this time, in the first CMOS circuit of the latch circuit 13, the MOSFET Qp2 is turned off and the MOSFET Qn2 is turned on. In the second CMOS circuit, the MOSFET Qn3 is turned off and the MOSFET Qp3 is turned on to generate an output signal clamped at the power supply voltage VDD (= 5 V) with respect to the signal output terminal VOUT.

  Thus, when the input voltage Vi at the signal input terminal VIN changes beyond the power supply voltage VDD, the signal amplitude of the external data is clamped between the ground potential and the power supply voltage VDD at the signal output terminal VOUT. The output voltage Vo can be output with a short delay time. In the clamp circuit of FIG. 3, a P-channel type MOSFET Qp1 is used instead of the MOSFET Qn1, and the gate of the P-channel type MOSFET Qp1 is grounded to clamp the input voltage Vi below the lower limit (GND) of the voltage amplitude. It is also possible to limit the underinput.

  As described above, the clamp circuit 12 according to the second embodiment is a clamp circuit that limits the voltage amplitude of external data supplied to an integrated circuit or the like and outputs a signal in a predetermined voltage range, and the gate terminal is a gate bias signal input terminal. A gate bias signal that is connected to Vb and serves as the first reference power supply is supplied, a drain terminal is connected to the signal input terminal VIN, and a substrate terminal is connected to the ground serving as the second reference power supply. And the two-stage inverter circuits U1, U2 connected in series between the source terminal of the MOSFET Qn1 and the signal output terminal VOUT, and the first-stage input terminal and the final-stage output terminal of the inverter circuits U1, U2. And a latch circuit 13 composed of a resistor R2 to be connected to limit the excessive input above the voltage amplitude of the input voltage Vi, and It is obtained so as to protect the integrated circuit. Therefore, here, the provision of the clamp circuit 12 causes little increase in delay time until signal output and does not increase current consumption.

  As described above, the clamp circuit 12 of the second embodiment may use a P-channel MOSFET instead of the N-channel MOSFET Qn1 constituting the clamp circuit 12 as in the first embodiment. Is possible. In that case, needless to say, the potential of the substrate terminal and the potential of the gate bias signal are different from those in FIG.

3 is a block diagram illustrating a clamp circuit according to the first embodiment. FIG. 6 is a block diagram illustrating a clamp circuit according to a second embodiment. FIG. 6 is a circuit diagram showing an example of a clamp circuit according to Embodiment 2. FIG. FIG. 4 is a voltage waveform diagram showing simulation voltage values in each part of the clamp circuit of FIG. 3. It is a block diagram which shows an example of the conventional clamp circuit.

Explanation of symbols

11, 12 Clamp circuit 13 Latch circuit VIN Signal input terminal VOUT Signal output terminal U1, U2 Inverter circuit R1, R2 Resistor D1, Zener diode V1 Input voltage of inverter circuit U1 Qn1, Qn2, Qn3, Qp2, Qp3 MOSFET

Claims (6)

In the clamp circuit that limits the amplitude of the input signal voltage and outputs a signal in a predetermined voltage range,
A gate terminal is connected to a first reference power supply, and a three-pole terminal device drain pin is directly connected to the signal input terminal,
An even number of inverter circuits connected in series between a source terminal and a signal output terminal of the three-terminal clamp element;
A resistance element having one end connected to a connection point between the source terminal of the three-terminal clamp element and the inverter circuit, and the other end connected to a second reference power supply;
A clamp circuit comprising:   2. The clamp circuit according to claim 1, wherein the potential of the first reference power source is higher than the potential of the second reference power source, and the three-terminal clamp element is an N-channel type MOSFET.   2. The clamp circuit according to claim 1, wherein the potential of the first reference power source is lower than the potential of the second reference power source, and the three-terminal clamp element is a P-channel type MOSFET. In the clamp circuit that limits the amplitude of the input signal voltage and outputs a signal in a predetermined voltage range,
A three-terminal clamp element having a gate terminal connected to a first reference power supply and a drain terminal connected to a signal input terminal;
An even number of inverter circuits connected in series between the source terminal and the signal output terminal of the three-terminal clamp element, and a feedback resistor that connects the first-stage input terminal and the final-stage output terminal of the inverter circuit And a latch circuit
A clamp circuit comprising:   5. The clamp circuit according to claim 4, wherein the three-terminal clamp element is an N-channel type MOSFET.   5. The clamp circuit according to claim 4, wherein the three-terminal clamp element is a P-channel type MOSFET.

Images