JP4801917B2 - amplifier - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to an amplifier having a differential input stage.

  For high-accuracy analog signals and low-voltage and high-accuracy analog signal processing, etc., a single-stage or multi-stage differential amplifier circuit having a differential input stage is often used (for example, , See Patent Document 1).

In the amplifier described in Patent Document 1, the gain and the pole frequency are greatly influenced by the value of the output impedance. For example, if the output impedance value is decreased to maintain a predetermined gain and provide a phase margin, there is a problem that the current consumption of the amplifier increases. In addition, when the impedance is converted to a desired impedance, there is a problem that the shape and current value of the transistor are limited and the degree of freedom in circuit design is reduced.
JP 2004-128487 A (page 23, FIG. 10)

  An object of the present invention is to provide an amplifier capable of performing desired impedance conversion without increasing current consumption.

In order to achieve the above object, an amplifier according to one embodiment of the present invention is provided between a high-potential-side power supply and a low-potential-side power supply and includes one stage or a plurality of stages, and forms a differential pair at an input stage. A differential amplifier circuit including a first transistor and a second transistor , wherein an input signal is input to a control terminal of the first transistor and a feedback signal is input to a control terminal of the second transistor; A resistor provided between the high potential side power source and the low potential side power source, one end connected to the output node of the differential amplifier circuit, a control terminal connected to the other end of the resistor, and a diode connection A third transistor , one end of which is connected to the other end of the resistor and the control terminal of the third transistor, and the other end of which is connected to the low-potential-side power source . The transistor shape is A first voltage drop, which is a voltage difference between the potential side power supply voltage and the output node, and a voltage difference between the high potential side power supply voltage and the voltage on the low potential side power supply side of the third transistor. And an impedance conversion circuit adjusted so that the two voltage drops are the same, and performs a negative feedback differential amplification operation .

Furthermore, in order to achieve the above object, an amplifier according to another aspect of the present invention is provided between a high-potential side power supply and a low-potential side power supply, is configured by a plurality of stages, and forms a differential pair in an input stage. And a differential amplifier circuit that performs a negative feedback operation when an input signal is input to the control terminal of the first transistor and a feedback signal is input to the control terminal of the second transistor. A resistor provided between the high potential power source and the low potential power source, one end connected to the output node of the input stage, and a control terminal connected to the other end of the resistor and diode connected 3, a current source having one end connected to the other end of the resistor and the control terminal of the third transistor, and the other end connected to the low-potential side power source . The shape is the high potential side A first voltage drop that is a voltage difference between the voltage and the output node, and a second voltage that is a voltage difference between the high-potential-side power supply voltage and the voltage on the low-potential-side power supply side of the third transistor. And an impedance conversion circuit that is adjusted so that the drops are the same, and performs a negative feedback differential amplification operation .

  According to the present invention, it is possible to provide an amplifier capable of performing desired impedance conversion without increasing current consumption.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, an amplifier according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an amplifier. In the present embodiment, an impedance conversion circuit is provided on the output side of the single stage differential amplifier circuit.

  As shown in FIG. 1, the amplifier 1 includes a differential amplifier circuit 2 and an impedance conversion circuit 3. The differential amplifier circuit 2 is provided with a Pch MOS (Metal Oxide Semiconductor) transistor PT1, a Pch MOS transistor PT2, an Nch MOS transistor NT1, an Nch MOS transistor NT2, and a current source BC1. The MOS transistor is also referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The source of the Pch MOS transistor PT1 is connected to the high potential power supply Vdd, and the gate is connected to the drain and the gate of the Pch MOS transistor PT2. The Pch MOS transistor PT2 has a source connected to the high potential power supply Vdd and a drain connected to the drain of the Nch MOS transistor NT2. The Pch MOS transistor PT1 and the Pch MOS transistor PT2 constitute a current mirror circuit. In operation, the current Ia flows from the high potential power source Vdd to the low potential side power source Vss in the Pch MOS transistor PT1, and the Pch MOS transistor PT2 has the same magnitude as the current Ia and from the high potential power source Vdd to the low potential side. A current Ib flows in the direction of the power supply Vss.

  The Nch MOS transistor (first transistor) NT1 has a drain connected to the drain of the Pch MOS transistor PT1, and a first input signal is input from the input terminal IN1 to the gate. The Nch MOS transistor (second transistor) NT2 receives the second input signal from the input terminal IN2 at the gate. Nch MOS transistor NT1 and Nch MOS transistor NT2 form a differential pair.

  The current source BC1 has one end connected to the sources of the Nch MOS transistor NT1 and the Nch MOS transistor NT2, and the other end connected to the low potential side power source Vss. A “High” level bias potential (not shown) is applied to the current source BC1, and all the MOS transistors constituting the differential of the differential amplifier circuit 2 are connected to the input terminal IN1 and the input terminal IN2 in the pentode region. When an operable input voltage is applied, the differential amplifier circuit 2 is turned on, a current Ia + Ib flows from the high potential power supply Vdd to the low potential side power supply Vss through the current source BC1, and the drain of the Pch MOS transistor PT2 and the Nch MOS A differentially amplified output signal is output from the node N3 between the drains of the transistor NT2 to the output terminal OUT.

  The impedance conversion circuit 3 is provided with a Pch MOS transistor PT3, a resistor R1, and a current source BC2. The Pch MOS transistor PT3 is a diode-connected transistor having a source connected to the high potential power source Vdd, a gate connected to the drain, and a current Ic flowing from the high potential power source Vdd toward the low potential power source Vss. The resistor R1 has one end connected to a node N1 between the drain of the Pch MOS transistor PT2 and the drain of the Nch MOS transistor NT2, and the other end connected to a node N2 between the drain of the Pch MOS transistor PT3 and the current source BC2. Yes. The current source BC2 has one end connected to the drain of the Pch MOS transistor PT3 and the other end connected to the low potential side power source Vss. Here, the shape of the Pch MOS transistor PT3 is set such that the reciprocal of the conductance (gm) is smaller by one digit or more than the resistance R1.

  When a “High” level bias potential (not shown) is applied to the current source BC2, a current Ic flows from the high potential power source Vdd to the low potential side power source Vss in the current source BC2. For example, an Nch MOS transistor in which a bias potential is applied to the gate is used for the current source BC1 and the current source BC2.

  Here, the gate shape of the Pch MOS transistor PT3 is adjusted and the current of the current source BC2 is adjusted, and the voltage drop in the Pch MOS transistor PT2 and the voltage drop in the Pch MOS transistor PT3 are designed to be the same. . Therefore, the node N1 and the node N2 are always at the same potential, and no current flows through the resistor R1.

Next, the impedance conversion of the impedance conversion circuit 3 will be described in detail. Here, when the impedance of the Pch MOS transistor PT2 is rds1, the impedance of the Nch MOS transistor NT2 is rds2, and the conductance of the Pch MOS transistor PT3 is gm1, the high-potential-side power supply Vdd that is the output impedance of the amplifier 1 and the output terminal OUT AC impedance ro is
1 / ro ≒ (1 / rds1) + (1 / rds2) + [1 / {R1 + (1 / gm1)}] ... Equation (1)
It is expressed. The node N20 shown in FIG. 1 can be regarded as ground (also referred to as ground) in the AC equivalent circuit, and the impedance component of the current source BC1 can be excluded from the above equation (1). Further, since the conductance (reciprocal of the impedance) of the current source BC2 is sufficiently smaller than the conductance gm1 of the Pch MOS transistor, the impedance component of the current source BC2 can be excluded from the above equation (1).

As described above, since the shape of the Pch MOS transistor PT3 is set so that the reciprocal of the conductance gm1 of the Pch MOS transistor PT3 is one digit or more smaller than the resistance R1, the (1) in the above equation (1) is set. Excluding the term / gm1)
1 / ro ≒ (1 / rds1) + (1 / rds2) + (1 / R1) ··· Equation (2)
It is expressed.

  In the amplifier 1, in order to maintain a predetermined gain and achieve a low current consumption (for example, a gain of 20 or more and a current consumption of 5 μA or less), the impedance rds1 of the Pch MOS transistor PT2 and the Nch MOS transistor NT2 The impedance rds2 is set to 2 MΩ or more, for example.

Here, when the resistor R1 is set to a value one digit or more smaller than the impedance rds2 of the Pch MOS transistor PT2 and the impedance rds2 of the Nch MOS transistor NT2, for example, 100 kΩ, (1 / rdds1) and (1 Excluding the / rds2) term
1 / ro ≒ (1 / R1) ... Formula (3)
It is expressed.

  The resistance R1 is preferably in the range of 50 kΩ to 1 MΩ. If it is 50 KΩ or less, it is difficult to increase the gain to 20 dB or more. If it is 1 MΩ or more, the impedance rds1 of the Pch MOS transistor PT2 and the impedance rds2 of the Nch MOS transistor NT2 cannot be ignored, and the output impedance ro of the amplifier 1 is set to the resistor R1. It becomes difficult to convert.

  As described above, in the amplifier of this embodiment, the impedance conversion circuit 3 including the Pch MOS transistor PT3, the resistor R1, and the current source BC2 is provided on the output side of the differential amplifier circuit 2. The resistor R1 has one end connected to a node N1 between the drain of the Pch MOS transistor PT2 and the drain of the Nch MOS transistor NT2, and the other end connected to a node N2 between the drain of the Pch MOS transistor PT3 and the current source BC2. The shape of the Pch MOS transistor PT3 and the current of the current source BC2 are adjusted so that no current flows through the resistor R1. The impedance conversion circuit 3 converts the impedance between the high-potential-side power supply Vdd and the output terminal OUT, which is the output impedance of the differential amplifier circuit 2, into a resistor R1.

  For this reason, the value of the output impedance of the amplifier 1 can be arbitrarily adjusted by changing the value of the resistor R1. Accordingly, the pole frequency can be set to an optimum value while maintaining the gain and DC performance (low current consumption) of the amplifier 1, and the phase margin and the frequency band can be improved. In addition, complicated circuit design for setting the output impedance of the amplifier 1 is not required, and the degree of freedom in circuit design is improved.

In this embodiment, a current mirror circuit is used for the differential amplifier circuit 2, but a resistor load or a transistor load using a PchMOS transistor may be used. Further, although a silicon oxide film is used as the gate insulating film of the MOS transistor, a SiNxOy film obtained by thermally nitriding the silicon oxide film, a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film laminated film, or a high dielectric film A MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which (High-K gate insulating film) or the like becomes a gate insulating film may be used.

  Next, an amplifier according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram showing the amplifier. In this embodiment, an impedance conversion circuit is provided on the output side of the amplification stage which is the second stage of the negative feedback differential amplifier circuit having a three-stage configuration.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 2, the amplifier 1a includes a differential input stage 2a, an impedance conversion circuit 3a, an amplification stage 4, and an output stage 5.

  The differential input stage 2a is provided with a Pch MOS transistor PT1, a Pch MOS transistor PT2, an Nch MOS transistor NT1, an Nch MOS transistor NT2, and a current source BC1. The differential input stage 2a has the same arrangement of the transistors and the current source BC1 as the differential amplifier circuit 2 of FIG.

  N-channel MOS transistor NT1 receives an input signal from its input terminal at its gate. Nch MOS transistor NT2 receives the feedback signal output from output stage 5 at its gate. The Nch MOS transistor NT1 and the Nch MOS transistor NT2 form a differential pair, and a differentially amplified signal is output from the node N4 to the amplification stage 4.

  The amplification stage 4 is provided between the differential input stage 2a and the impedance conversion circuit 3a, and includes a Pch MOS transistor PT4 and a current source BC3.

  The Pch MOS transistor PT4 has a source connected to the high potential side power supply Vdd and a gate connected to a node N4 between the drain of the Pch MOS transistor PT2 and the drain of the Nch MOS transistor NT2 in the differential input stage 2a. A current Id flows from the potential power source Vdd toward the low potential side power source Vss, amplifies the signal output from the differential input stage 2a, and outputs the signal from the node N7 to the output stage 5.

  One end of the current source BC3 is connected to the drain of the Pch MOS transistor PT4, and the other end is connected to the low potential side power source Vss. When a “High” level bias potential (not shown) is applied to the current source BC2, the amplification stage 4 is turned on, and the current Id flows from the high potential power source Vdd to the low potential side power source Vss in the current source BC3.

  The impedance conversion circuit 3a is provided between the amplification stage 4 and the output stage 5, and includes a Pch MOS transistor PT3a, a resistor R1a, and a current source BC2a.

  The Pch MOS transistor PT3a is a diode-connected transistor having a source connected to the high potential side power supply Vdd, a gate connected to the drain, and a current Ie flowing from the high potential side power supply Vdd toward the low potential side power supply Vss. The resistor R1a has one end connected to the node N5 between the drain of the Pch MOS transistor PT4 in the amplification stage 4 and the current source BC3, and the other end connected to the node N6 between the drain of the Pch MOS transistor PT3a and the current source BC2a. ing. The current source BC2a has one end connected to the drain of the Pch MOS transistor PT3a and the other end connected to the low potential side power supply Vss. Here, the shape of the Pch MOS transistor PT3a is set such that the reciprocal of the conductance (gm) is a value smaller by one digit or more than the resistor R1a.

  When a “High” level bias potential (not shown) is applied to the current source BC2a, the current Ie flows from the high potential power source Vdd to the low potential side power source Vss in the current source BC2a.

  Here, the gate shape of the Pch MOS transistor PT3a and the current adjustment of the current source BC2a are adjusted, and the voltage drop at the Pch MOS transistor PT4 and the voltage drop at the Pch MOS transistor PT3a are designed to be the same. . For this reason, the node N5 and the node N6 are always at the same potential, and no current flows through the resistor R1a.

  The output stage 5 includes a Pch MOS transistor PT5, a resistor R2, and a resistor R3. The Pch MOS transistor PT5 has a source connected to the high potential side power supply Vdd, a gate connected to the node N7 between the drain of the Pch MOS transistor PT4 of the amplification stage 4 and the current source BC3, and a signal output from the amplification stage 4 Is output from the node N8 to the output terminal OUT.

  The resistors R2 and R3 are connected in cascade between the drain of the Pch MOS transistor PT5 and the low-potential-side power supply Vss, and a feedback signal having a resistance-divided potential is provided between the resistors R2 and R3 in the differential input stage 2a. Is input to the gate of the N-channel MOS transistor NT2.

Next, the impedance conversion of the impedance conversion circuit 3a will be described in detail. Here, assuming that the impedance of the Pch MOS transistor PT4 is rds4 and the conductance of the Pch MOS transistor PT3a is gm2, the AC impedance roa between the high potential side power supply Vdd and the node N7, which is the output impedance of the amplification stage 4, is
1 / roa ≒ (1 / rds4) + [1 / {R1a + (1 / gm2)}] ··· Equation (4)
It is expressed. Note that the conductance (reciprocal of the impedance) of the current source BC2a and the current source BC3 is sufficiently smaller than the conductance gm2 of the Pch MOS transistor PT3a. can do.

As described above, since the shape of the Pch MOS transistor PT3a is set so that the reciprocal of the conductance gm2 of the Pch MOS transistor PT3a is smaller by one digit or more than the resistance R1a, (1) in the above equation (4) / Gm2)
1 / roa ≒ (1 / rds4) + (1 / R1a) ··· Equation (5)
It is expressed.

  In the amplification stage 4 of the amplifier 1a, in order to maintain a predetermined gain and achieve low current consumption (for example, gain is 20 or more and current consumption is 3 μA or less), the impedance rds4 of the Pch MOS transistor PT4, for example, 3MΩ or more is set.

Here, if the resistor R1a is set to a value one digit or more lower than the impedance rds4 of the Pch MOS transistor PT4, for example, 200 kΩ, the term (1 / rds4) in the above equation (5) is excluded,
1 / roa ≒ (1 / R1a) ··· Equation (6)
It is expressed.

  That is, the value of the output impedance of the amplification stage 4 can be arbitrarily adjusted by changing the value of the resistor R1a. Therefore, the pole frequency can be set to an optimum value while maintaining the gain and DC performance (low current consumption) of the amplification stage 4, and the phase margin and the frequency band can be improved.

  As described above, in the amplifier of this embodiment, the impedance conversion circuit 3a including the Pch MOS transistor PT3a, the resistor R1a, and the current source BC2a is provided on the output side of the amplification stage 4. The resistor R1a has one end connected to the node N5 between the drain of the Pch MOS transistor PT4 and the current source BC3, and the other end connected to a node N6 between the drain of the Pch MOS transistor PT3a and the current source BC2a. The shape of the Pch MOS transistor PT3a and the current of the current source BC2a are adjusted so that no current flows. The impedance conversion circuit 3a converts the impedance between the high-potential-side power supply Vdd, which is the output impedance of the amplification stage 4, and the node N7 into the resistor R1a.

  For this reason, the value of the output impedance of the amplification stage 4 can be arbitrarily adjusted by changing the value of the resistor R1a. Therefore, the pole frequency can be set to an optimum value while maintaining the gain and DC performance (low current consumption) of the amplification stage 4, and the phase margin and the frequency band can be improved. In addition, complicated circuit design for setting the output impedance of the amplification stage 4 is not required, and the degree of freedom in circuit design is improved. Furthermore, it is possible to provide an impedance conversion circuit for each stage. In this case, the output impedance adjustment of each stage can be simplified, the circuit design of the amplifier 1a can be quickly performed, and an optimum output is provided for each stage. Even with an amplifier set to impedance and having a three-stage configuration or more, the phase margin can be increased.

  In the present embodiment, the impedance conversion circuit 3a is provided on the output side of the amplification stage 4 which is the second stage, but the impedance is provided to the differential input stage 2a which is the first stage and the output stage 4 which is the third stage. A conversion circuit may be provided.

  Next, an amplifier according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing the amplifier. In this embodiment, an impedance conversion circuit is provided on the output side of a differential amplifier circuit composed of a single-stage bipolar transistor.

  As shown in FIG. 3, the amplifier 1b includes a differential amplifier circuit 2b and an impedance conversion circuit 3b. The differential amplifier circuit 2b is provided with a PNP transistor PB1, a PNP transistor PB2, an NPN transistor NB1, an NPN transistor NB2, and a current source BC1a.

  The PNP transistor PB1 has an emitter connected to the high potential power supply Vdd and a base connected to the collector and the base of the PNP transistor PB2. The PNP transistor PB2 has an emitter connected to the high potential power supply Vdd and a drain connected to the collector of the NPN transistor NB2. The PNP transistor PB1 and the PNP transistor PB2 constitute a current mirror circuit. In operation, the current If flowing from the high potential power source Vdd to the low potential side power source Vss flows through the PNP transistor PB1, and the PNP transistor PB2 has the same magnitude as the current If from the high potential power source Vdd to the low potential side power source. A current Ig flowing in the Vss direction flows.

  The NPN transistor NB1 has a collector connected to the collector of the PNP transistor PB1, and receives a first input signal from the input terminal IN1 to the base. The NPN transistor NB2 receives the second input signal from the input terminal IN2 to the base. The NPN transistor NB1 and the NPN transistor NB2 form a differential pair.

  One end of the current source BC1a is connected to the emitters of the NPN transistor NB1 and the NPN transistor NB2, and the other end is connected to the low potential side power source Vss. When a “High” level bias potential (not shown) is applied to the current source BC1a, the differential amplifier circuit 2b is turned on, and if + Ig current flows from the high potential power supply Vdd to the low potential side power supply Vss in the current source BC1a. A differentially amplified output signal is output from the node N11 between the collector of the PNP transistor PB2 and the collector of the NPN transistor NB2 to the output terminal OUT.

  The impedance conversion circuit 3b is provided with a PNP transistor PB3, a resistor R1b, and a current source BC2b. The PNP transistor PB3 is a diode-connected transistor having an emitter connected to the high potential power source Vdd, a base connected to the collector, and a current Ih flowing from the high potential power source Vdd toward the low potential power source Vss. The resistor R1b has one end connected to a node N9 between the collector of the PNP transistor PB2 and the collector of the NPN transistor NB2, and the other end connected to a node N10 between the collector of the PNP transistor PB3 and the current source BC2b. The current source BC2b has one end connected to the collector of the PNP transistor PB3 and the other end connected to the low potential side power source Vss. Here, the shape of the PNP transistor PB3 is set such that the reciprocal of the conductance (gm) is a value smaller by one digit or more than the resistance R1b.

  When a “High” level bias potential (not shown) is applied to the current source BC2b, a current Ih flows from the high potential power source Vdd to the low potential side power source Vss in the current source BC2b.

  Here, the transistor shape of the PNP transistor PB3 and the current of the current source BC2b are adjusted, and the voltage drop at the PNP transistor PB2 and the voltage drop at the PNP transistor PB3 are designed to be the same. Therefore, the node N9 and the node N10 are always at the same potential, and no current flows through the resistor R1b.

Next, the impedance conversion of the impedance conversion circuit 3b will be described in detail. Here, the impedance of the PNP transistor PB2 is rc1, the impedance of the NPN transistor NB2 is rc2, and the conductance of the PNP transistor PB3 is gm3.
R1b >> 1 / gm3 ・ ・ ・ ・ ・ ・ Formula (7)
R1b << rce1, R1b << rce2 ... Formula (8)
If the value of the resistor R1b is set within the range, the AC impedance rob between the high potential side power supply Vdd and the output terminal OUT, which is the output impedance of the amplifier 1b, is the same as in the first embodiment.
1 / rob ≒ (1 / R1b) ... Formula (9)
It is expressed.

  That is, the value of the output impedance of the amplifier 1b can be arbitrarily adjusted by changing the value of the resistor R1b.

  As described above, in the amplifier according to this embodiment, the impedance conversion circuit 3b including the PNP transistor PB3, the resistor R1b, and the current source BC2b is provided on the output side of the differential amplifier circuit 2b. The resistor R1b has one end connected to a node N9 between the collector of the PNP transistor PB2 and the collector of the NPN transistor NB2, and the other end connected to a node N10 between the collector of the PNP transistor PB3 and the current source BC2a. No current flows. The impedance conversion circuit 3b converts the impedance between the high-potential-side power supply Vdd and the output terminal OUT, which is the output impedance of the differential amplifier circuit 2b, into a resistor R1b.

  Therefore, the value of the output impedance of the amplifier 1b can be arbitrarily adjusted by changing the value of the resistor R1b. Therefore, the pole frequency can be set to an optimum value while maintaining the gain and DC performance (low current consumption) of the amplifier 1b, and the phase margin and the frequency band can be improved. In addition, complicated circuit design for setting the output impedance of the amplifier 1b is not required, and the degree of freedom in circuit design is improved.

  Next, an amplifier according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing the amplifier. In this embodiment, an impedance conversion circuit is provided on the output side of the cascode-type differential input stage of the two-stage negative feedback differential amplifier circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 4, the amplifier 1c includes a differential input stage 2c, an impedance conversion circuit 3c, and an output stage 5a. The differential input stage 2c is provided with Pch MOS transistors PT11 to PT14, Nch MOS transistor NT1, Nch MOS transistor NT2, Nch MOS transistor NT11, Nch MOS transistor NT12, and current source BC1b.

  The Pch MOS transistor PT11 has a source connected to the high potential power supply Vdd, a gate supplied with a bias potential from the bias terminal Vb1, and a drain connected to the source of the Pch MOS transistor PT13. The Pch MOS transistor PT12 has a source connected to the high potential power supply Vdd, a gate supplied with a bias potential from the bias terminal Vb1, and a drain connected to the source of the Pch MOS transistor PT14. In the Pch MOS transistor PT13, a bias potential is supplied to the gate from the bias terminal Vb2, and the drain is connected to the drain of the Nch MOS transistor NT11. The Pch MOS transistor PT14 has a gate supplied with a bias potential from a bias terminal Vb2, and a drain connected to the drain of the Nch MOS transistor NT12.

  The Nch MOS transistor NT11 has a gate supplied with a bias potential from a bias terminal Vb3, and a source connected to the drain of the Nch MOS transistor NT1. The Nch MOS transistor NT12 has a gate supplied with a bias potential from a bias terminal Vb3, and a source connected to the drain of the Nch MOS transistor NT2. The Nch MOS transistor NT1 has an input signal input from the input terminal IN to the gate, and the Nch MOS transistor NT2 receives the feedback signal output from the output stage 5a. Nch MOS transistor NT1 and Nch MOS transistor NT2 form a differential pair.

  In operation, the Pch MOS transistor PT11, Pch MOS transistor PT13, Nch MOS transistor NT11, and Nch MOS transistor NT1 flow a current Im from the high potential side power supply Vdd to the low potential side power supply Vss, respectively, and the Pch MOS transistor PT12, Pch The MOS transistor PT14, the Nch MOS transistor NT12, and the Nch MOS transistor NT2 flow a current In having the same magnitude as the current Im from the high potential side power supply Vdd toward the low potential side power supply Vss during operation.

  One end of the current source BC1b is connected to the sources of the Nch MOS transistor NT1 and the Nch MOS transistor NT2, and the other end is connected to the low potential side power source Vss. When a “High” level bias potential (not shown) is applied to the current source BC1b, the differential input stage 2c is turned on, and a current Im + In flows from the high potential power supply Vdd to the low potential side power supply Vss in the current source BC1b. A differentially amplified output signal is output from the node N14 between the drain of the Pch MOS transistor PT13 and the drain of the Nch MOS transistor NT11 to the output stage 5a.

  The impedance conversion circuit 3c is provided between the differential input stage 2c and the output stage 5a, and includes a Pch MOS transistor PT3b, a Pch MOS transistor PT15, a resistor R1c, and a current source BC2c.

  The Pch MOS transistor PT15 has a source connected to the high potential side power supply Vdd, a gate supplied with a bias potential from the bias terminal Vb4, and a drain connected to the source of the Pch MOS transistor PT3b. The Pch MOS transistor PT3b is a diode-connected transistor whose gate is connected to the drain. The Pch MOS transistor PT15 and the Pch MOS transistor PT3b cause a current Ip to flow from the high potential side power supply Vdd to the low potential side power supply Vss during operation.

  The resistor R1c has one end connected to a node N12 between the drain of the Pch MOS transistor PT13 and the drain of the Nch MOS transistor NT11, and the other end connected to a node N13 between the drain of the Pch MOS transistor PT3b and the current source BC2c. Yes. The current source BC2c has one end connected to the drain of the Pch MOS transistor PT3b and the other end connected to the low potential side power source Vss. Here, the shape of the Pch MOS transistor PT3b is set such that the reciprocal of the conductance (gm) is smaller by one digit or more than the resistance R1.

  When a “High” level bias potential (not shown) is applied to the current source BC2c, the current Ip flows in the current source BC2c from the high potential power supply Vdd toward the low potential power supply Vss.

  Here, adjustment of the gate shape of the Pch MOS transistor PT3b, adjustment of the gate shape of the Pch MOS transistor PT15, and current adjustment of the current source BC2c are performed, and the sum of the voltage drops in the Pch MOS transistor PT11 and the Pch MOS transistor PT13 and Pch are adjusted. The sum of voltage drops in the MOS transistor PT15 and the Pch MOS transistor PT3b is designed to be the same. Therefore, the node N12 and the node N13 are always at the same potential, and no current flows through the resistor R1c.

  The Pch MOS transistor PT15 may be omitted and only the Pch MOS transistor PT3b may be provided. In this case, it is necessary to optimize the transistor shape of the Pch MOS transistor PT13 so that the sum of the voltage drops in the Pch MOS transistor PT11 and the Pch MOS transistor PT13 and the voltage drop in the Pch MOS transistor PT3b have the same value. is there.

  The output stage 5a includes a Pch MOS transistor PT5a, a resistor R2a, and a resistor R3a. The Pch MOS transistor PT5a has a source connected to the high potential side power supply Vdd, and a gate connected to a node N14 between the drain of the Pch MOS transistor PT13 and the drain of the Nch MOS transistor NT11 in the differential input stage 2c. The signal output from the stage 2c is amplified, and the signal is output from the node N15 to the output terminal OUT.

  The resistor R2a and the resistor R3a are connected in cascade between the drain of the Pch MOS transistor PT5a and the low-potential-side power supply Vss, and a feedback signal having a resistance-divided potential is provided between the resistor R2a and the resistor R3a in the differential input stage 2c. Is input to the gate of the N-channel MOS transistor NT2.

Next, the impedance conversion of the impedance conversion circuit 3c will be described in detail. Here, the impedance of Pch MOS transistor PT11 is rds6, the impedance of Pch MOS transistor PT13 is rds7, the impedance of Nch MOS transistor NT11 is rds8, the impedance of Nch MOS transistor NT1 is rds9, the impedance of Pch MOS transistor PT15 is rds10, Pch MOS transistor The conductance of the transistor PT3b is gm4,
R1c >> 1 / gm4 ... Formula (10)
R1c << rce6, rce7, rce8, rce9, rce10 ... Formula (11)
If the value of the resistor R1c is set in the range of ω, the AC impedance loc between the high-potential-side power supply Vdd and the node N14 that is the output impedance of the differential input stage 2c is the same as in the first embodiment.
1 / roc ≒ (1 / R1c) ··· Equation (12)
It is expressed.

  That is, the value of the output impedance of the differential input stage 2c can be arbitrarily adjusted by changing the value of the resistor R1c.

  As described above, in the amplifier of this embodiment, the impedance conversion circuit 3c including the Pch MOS transistor PT15, the Pch MOS transistor PT3b, the resistor R1c, and the current source BC2c is provided on the output side of the differential input stage 2c. Yes. The resistor R1c has one end connected to a node N12 between the drain of the Pch MOS transistor PT13 and the drain of the Nch MOS transistor NT11, and the other end connected to a node N13 between the drain of the Pch MOS transistor PT3b and the current source BC2c. No current flows through the resistor R1c. The impedance conversion circuit 3c converts the impedance between the high-potential-side power supply Vdd and the node N14, which is the output impedance of the differential input stage 2c, into a resistor R1c.

  For this reason, the value of the output impedance of the differential input stage 2c can be arbitrarily adjusted by changing the value of the resistor R1c. Therefore, the pole frequency can be set to an optimum value while maintaining the gain and DC performance (low current consumption) of the differential input stage 2c, and the phase margin and the frequency band can be improved. In addition, complicated circuit design for setting the output impedance of the differential input stage 2c is not required, and the degree of freedom in circuit design is improved. Further, since the cascode differential amplifier circuit is used for the differential input stage 2c, the number of poles is small compared to the differential amplifier circuit using the current mirror circuit of the first and second embodiments. It operates stably over a wide band.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the first embodiment, the second embodiment, and the third embodiment, the amplifier has a CMOS configuration. In the third embodiment, the amplifier has a bipolar transistor, but the amplifier may have a BiCMOS configuration. Further, the amplifier of this embodiment can be used for an operational amplifier, an error amplifier, a regulator, and the like using a negative feedback system.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) A first Nch MOS transistor and a second Nch MOS transistor which are configured in a plurality of stages and form a differential pair in the input stage are provided, and an input signal is input to the gate of the first Nch MOS, A diode-connected Pch MOS provided between a negative feedback differential amplifier circuit in which a feedback signal is inputted to the gate of the second Nch MOS and a high potential side power source and a low potential side power source and having a gate connected to a drain A transistor, one end of the current source provided between the drain of the Pch MOS transistor and the low-potential power supply, one end connected to the output side of the input stage, and the other end of the drain of the Pch MOS transistor and the A resistor connected between the current sources, adjusting means for adjusting both ends of the resistor to the same potential, and a variable for converting the output impedance of the input stage. And means, an amplifier comprising an impedance conversion circuit provided on the output side of the input stage.

(Supplementary Note 2) A first Nch MOS transistor and a second Nch MOS transistor which are configured in a plurality of stages and form a differential pair in the input stage are provided, and an input signal is input to the gate of the first Nch MOS, A diode-connected Pch MOS provided between a negative feedback differential amplifier circuit in which a feedback signal is inputted to the gate of the second Nch MOS and a high potential side power source and a low potential side power source and having a gate connected to a drain One end of the transistor is connected to the current source provided between the drain of the Pch MOS transistor and the low-potential-side power source, one end is connected to the output side of the second amplification stage, and the other end is connected to the Pch MOS transistor A resistor connected between the low-potential-side power supply side and the current source, adjusting means for adjusting both ends of the resistor to the same potential, and an output input of the input stage And an impedance conversion circuit provided on the output side of the amplification stage.

(Supplementary Note 3) A first NPN transistor and a second NPN transistor which are configured in a plurality of stages and form a differential pair are provided in an input stage, and an input signal is input to a base of the first NPN transistor, A negative feedback differential amplifier circuit in which a feedback signal is input to the base of two NPN transistors, a diode-connected PNP transistor provided between the high-potential side power source and the low-potential side power source, and the base connected to the collector; One end is connected to the current source provided between the collector of the PNP transistor and the low-potential side power source, one end is connected to the output side of the input stage, and the other end is connected between the collector of the PNP transistor and the current source. A connected resistor; adjusting means for adjusting both ends of the resistor to the same potential; and converting means for converting the output impedance of the input stage. Amplifier comprising an impedance conversion circuit provided on the output side of the stage.

(Supplementary Note 4) A first NPN transistor and a second NPN transistor which are configured in a plurality of stages and form a differential pair in the input stage are provided, and an input signal is input to a base of the first NPN transistor, A negative feedback differential amplifier circuit in which a feedback signal is input to the base of two NPN transistors, a diode-connected PNP transistor provided between a high-potential side power source and a low-potential side power source, and a base connected to a collector; One end is connected to the current source provided between the collector of the PNP transistor and the low-potential side power supply, and one end is connected to the output side of the second amplification stage, and the other end is connected to the collector of the PNP transistor and the current A resistor connected between the sources, adjusting means for adjusting both ends of the resistor to the same potential, and converting means for converting the output impedance of the input stage, Amplifier comprising an impedance conversion circuit provided on the output side of the serial amplifier stages.

1 is a circuit diagram showing an amplifier according to Embodiment 1 of the present invention. FIG. 5 is a circuit diagram showing an amplifier according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing an amplifier according to Embodiment 3 of the present invention. FIG. 6 is a circuit diagram showing an amplifier according to Embodiment 4 of the present invention.

Explanation of symbols

1, 1a, 1b, 1c amplifier 2, 2b differential amplifier circuit 2a, 2c differential input stage 3, 3a, 3b, 3c impedance conversion circuit 4 amplifier stage 5, 5a output stage BC1, BC1a, BC1b, BC2, BC2a, BC2b, BC2c, BC3 Current sources Ia, Ib, Ic, Id, Ie, If, Ig, Ih, Im, In, Ip Current IN, IN1, IN2 Input terminals N1-15, N20 Nodes NB1, NB2 NPN transistors NT1, NT2 NT11, NT12 Nch MOS transistor OUT Output terminals PB1-3 PNP transistors PT1-5, PT3a, PT3b, PT5a, PT11-15 Pch MOS transistors R1, R1a, R1b, R1c R2, R2a, R3, R3a Resistors Vb1-4 Bias Terminal Vdd High potential side power supply Vss Low potential side power source

Claims (4)

A first transistor and a second transistor which are provided between a high potential side power source and a low potential side power source and which are configured by one stage or a plurality of stages and which form a differential pair at an input stage, are provided. An input signal is input to the control terminal of the second transistor, a feedback signal is input to the control terminal of the second transistor, and a differential amplifier circuit that performs a negative feedback operation ;
Provided between the high potential side power source and the low potential side power source, one end is connected to the output node of the differential amplifier circuit, and the control terminal is connected to the other end of the resistor and is diode-connected. a third transistor, one end is connected to a control terminal of the resistor of the other end and said third transistor, and a current source and the other end is connected to the low potential side power supply, said third transistor The shape is between the first voltage drop, which is the voltage difference between the high potential side power supply voltage and the output node, the high potential side power supply voltage, and the voltage on the low potential side power supply side of the third transistor. An impedance conversion circuit that is adjusted so that the second voltage drop, which is a voltage difference, is the same ;
And a negative feedback differential amplification operation . A first transistor and a second transistor which are provided between a high potential side power source and a low potential side power source, are configured in a plurality of stages, and which form a differential pair in an input stage. And a differential amplifier circuit that performs a negative feedback operation by inputting a feedback signal to the control terminal of the second transistor ,
A resistor provided between the high potential side power source and the low potential side power source, one end connected to the output node of the input stage, and a control terminal connected to the other end of the resistor and a third diode connected And a current source having one end connected to the other end of the resistor and the control terminal of the third transistor and the other end connected to the low-potential side power supply, and the shape of the third transistor Is a voltage difference between the first voltage drop, which is a voltage difference between the high potential side power supply voltage and the output node, and between the high potential side power supply voltage and the voltage on the low potential side power supply side of the third transistor. An impedance conversion circuit adjusted so that the second voltage drop is the same ;
And a negative feedback differential amplification operation . Provided between a high-potential side power supply and a low-potential side power supply, which is composed of three or more stages, and a first transistor and a second transistor forming a differential pair are provided in the input stage, and the control of the first transistor A differential amplifier circuit that receives an input signal at a terminal and receives a feedback signal at a control terminal of the second transistor to perform a negative feedback operation ;
A resistor connected between the high-potential-side power supply and the low-potential-side power supply, one end of which is connected to the output node of the second amplification stage, and a control terminal connected to the other end of the resistor, diode connected A third transistor , one end of which is connected to the other end of the resistor and the control terminal of the third transistor, and the other end of which is connected to the low-potential-side power source . The shape of the transistors of the first voltage drop, which is a voltage difference between the high potential side power supply voltage and the output node, the high potential side power supply voltage, and the voltage on the low potential side power supply side of the third transistor An impedance conversion circuit that is adjusted so that the second voltage drop that is the voltage difference between them is the same ;
And a negative feedback differential amplification operation . The third transistor is a Pch MOS transistor,
The Pch MOS transistor has a source connected to the high potential side power supply, a gate connected to the drain and the other end of the resistor.
The amplifier according to any one of claims 1 to 3, wherein:

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