JP4804036B2 - Image processing system - Google Patents

Description

  The present invention relates to an image processing system applicable to, for example, car navigation systems and other moving image / still image display devices in general.

  Conventionally, when an image is displayed in accordance with a video signal display method, a configuration in which image data and its output timing are controlled by software processing by a processor dedicated to image processing or a central processing unit (CPU) has been mainly adopted. It has become.

  However, in this configuration, both the image processing dedicated processor and the CPU are specialized for image data transfer, and other processes cannot be executed in a time division manner. As a result, the bus occupancy increases and the performance of the entire system decreases.

  As a prior art document relating to the present invention, the following Patent Document 1 gives a command sequence necessary for compression / decompression of a moving image from a CPU in advance, and controls the compression / decompression according to a vertical synchronization signal of the moving image. The present invention discloses an image processing method and apparatus capable of avoiding competition with general-purpose functions of a computer system and realizing high-quality compression / decompression processing in accordance with the timing of moving images.

Japanese Patent No. 3159951

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a simple circuit in a circuit on the image data receiving side, thereby effectively using CPU power, reducing bus occupancy, and An object of the present invention is to provide an image processing system that eliminates the need for a dedicated processor.

  To achieve the above object, according to the present invention, an image data receiving circuit that receives image data and displays an image on a display device, and a central processing unit that transfers the image data to the image data receiving circuit are provided. An image processing system comprising: a buffer for storing a certain amount of image data transferred from the central processing unit; and a synchronization signal generation for generating a horizontal synchronization signal and a vertical synchronization signal in image display Means, a transfer request output means for outputting an image data transfer request to the central processing unit, and image data to the transfer request output means in synchronization with a horizontal synchronizing signal or a vertical synchronizing signal until the image data is filled in the buffer. In addition to performing control to output a transfer request, in accordance with an instruction from the central processing unit, image data already stored in the buffer is updated. Image data reception control means for controlling the reuse as image data to be transferred, and the central processing unit can re-use the already transferred image data as image data to be newly transferred. In some cases, an image processing system is provided, comprising image data transfer necessity determination means for instructing the image data receiving circuit to reuse the image data without transferring the image data. Is done.

  In one preferred embodiment, the buffer stores image data for one line, and the image data reception control means receives the image data for the next line after completing reception of the image data for one line. Is inquired of the central processing unit as to whether it is equivalent to the received image data, and the image data transfer necessity determination means responds whether or not reuse is possible in response to the inquiry.

  In one preferred embodiment, the buffer stores image data for one line, and the image data reception control means receives the image data for the next line after completing reception of the image data for one line. When a transmission request is output, if a data enable signal is not received from the central processing unit, reuse is executed.

  In one preferred embodiment, the buffer stores image data for one line, and the image data reception control means receives the image data for the next line after completing reception of the image data for one line. If a signal instructing reuse is received from the central processing unit before outputting a transmission request, the reuse is executed.

  In one preferred embodiment, when image data is reused, it recognizes that there is no bus use for image data transfer between the image data receiving circuit and the central processing unit, and transfers data for other media. Do.

  In one preferable aspect, the buffer stores image data for one frame, and the image data transfer necessity determination means includes a pixel unit corresponding to one frame and the previous frame. The difference value is calculated, and if the difference value is equal to or smaller than the predetermined threshold, the pixel data is instructed to be reused without being transferred.

  In one preferable aspect, the buffer stores image data for one frame, and the image data transfer necessity determination means includes a pixel unit corresponding to one frame and the previous frame. In addition, the difference value of the luminance signal component and the difference value of the color difference signal component are calculated. If both of the difference values or at least one of them is equal to or less than a predetermined threshold value, the pixel data is not transferred. Instructs reuse of pixel data.

  In one preferable aspect, the threshold value is a variable value corresponding to the brightness of the pixel data.

  In one preferable aspect, the image data transfer necessity determination means includes a difference value of an AGC voltage level or a difference of AGC voltage fluctuation between the currently received image data and the image data received a predetermined time ago. If the value is calculated and the difference value is equal to or smaller than a predetermined threshold value, the image data being received is not transferred.

  In one preferred embodiment, when the image data being received is not transferred, the image data receiving circuit does not display an image on the display device.

  In one preferable aspect, the threshold value is a variable value corresponding to the vehicle speed and / or the reception frequency.

  In a preferred aspect, the threshold value is configured to be settable by a user.

  In one preferable aspect, the buffer stores image data for one frame, and the image data transfer necessity determination unit is configured to correspond to a line unit between one frame and the previous frame. The difference value is calculated, and if the difference value is equal to or smaller than a predetermined threshold value, the line data is not transferred and the line data is instructed to be reused.

  In one preferable aspect, the buffer stores image data for one frame, and the image data transfer necessity determination unit calculates a difference value between one frame and the previous frame. If the difference value is equal to or smaller than the predetermined threshold value, the frame data is not transferred and the reuse of the frame data is instructed.

  In one preferable aspect, the central processing unit transfers data for one line composed of an average value between n lines, and the image data receiving circuit transfers the transferred data for one line. Is repeated for n lines and displayed on the display device.

  In one preferred aspect, the buffer stores image data for a half frame or a fixed number of pixels.

  In one preferred embodiment, the buffer is composed of at least two memories corresponding to the image data being transferred and the image data being displayed.

  In one preferred aspect, the image data reception control means outputs an image data transfer request to the central processing unit at a timing corresponding to the enlargement or reduction when the image is enlarged or reduced.

  In one preferred embodiment, the image data reception control means notifies the central processing unit of an address required for the next transfer when thinning reproduction is necessary.

  In one preferred aspect, the image data reception control means notifies the necessary address and performs enlargement by reading back the same address a plurality of times when performing partial enlargement display of the image.

  In the image processing system according to the present invention, the central processing unit (CPU) does not need to consider the timing because it only has to send the image data every time an image data transfer request is received from the image data receiving circuit. In addition, the already sent image data is reused. Therefore, it is possible to effectively use CPU power, reduce the bus occupancy rate, and eliminate the need for a dedicated processor.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of an image processing system according to the present invention. In the figure, reference numeral 10 is an antenna, reference numeral 12 is an AGC (automatic gain control) circuit, reference numeral 14 is an image data transfer necessity determination circuit, reference numeral 16 is a storage medium, reference numeral 18 is a CPU (central processing unit), reference numeral 20 is A data receiving circuit, reference numeral 40 indicates a display device. The image data transfer necessity determination circuit 14 may be provided in the CPU 18.

  The display device 40 includes an NTSC display device, a separate RGB display device, a PAL display device, a SECAM display device, a composite data display device, a Y / C display device, and a YCbCr display device. Either a display device having a VFD interface or a display device having an organic EL interface may be used.

  The data receiving circuit 20 receives the image data transferred from the CPU 18 and performs a process of displaying an image on the display device 40, and is configured as one ASIC (Application Specific Integrated Circuit). The data receiving circuit 20 includes a display FIFO (First-In First-Out) memory 22, a display interface circuit 24, an audio FIFO memory 26, an audio interface circuit 28, an image transfer request output circuit 30, and an audio transfer request output circuit 32. , A horizontal and vertical synchronization signal generation circuit 34, a reception control circuit 36, and the like are provided.

  The display FIFO memory 22 is, for example, a buffer that stores image data for one line in image transfer. The image transfer request output circuit 30 is a circuit that outputs an image data transfer request to the CPU 18. The horizontal and vertical synchronization signal generation circuit 34 is a circuit that generates a horizontal synchronization signal and a vertical synchronization signal in image display. The reception control circuit 36 basically receives signals from the horizontal and vertical synchronization signal generation circuit 34 until a certain amount of image data (for example, data for one line of image) is filled in the display FIFO memory 22. This is a circuit for controlling the image transfer request output circuit 30 to output an image data transfer request. Hereinafter, an example of the image data transfer operation will be described.

  When receiving the horizontal synchronization signal generated by the horizontal and vertical synchronization signal generation circuit 34, the reception control circuit 36 instructs the image transfer request output circuit 30 to output an image data transfer request. When receiving the instruction, the image transfer request output circuit 30 outputs an image data transfer request to the CPU 18. When receiving the image data transfer request from the data receiving circuit 20, the CPU 18 returns a data enable signal to the data receiving circuit 20. The reception control circuit 36 repeats control for causing the image transfer request output circuit 30 to output an image data transfer request until the display FIFO memory 22 has received one line of data.

  In this way, the data receiving circuit 20 prompts the CPU 18 to transfer data for each line. Therefore, the CPU 18 does not need to recognize the timing for outputting the image data, and only monitors the image data transfer request from the data receiving circuit 20. Upon confirming that reception of data for one line has been completed, the reception control circuit 36 performs control to pass the data to the display interface circuit 24 and start outputting image data.

  When the above processing for one line is completed, it is determined whether or not the data stored in the display FIFO memory 22 can be reused. The following three methods are possible as the realization method, and these methods are shown in FIG. 2, FIG. 3 and FIG.

  In the method of FIG. 2, after the processing for one line is completed, the data reception circuit 20 (reception control circuit 36) is equivalent to the CPU 18 for data equivalence, that is, the previous line. Ask whether or not. Then, an answer is received for a certain period (for example, until the next horizontal synchronization signal is received and a request output is instructed to the image transfer request output circuit 30). When the reception control circuit 36 receives a signal indicating that it is equivalent, the reception control circuit 36 does not give a transfer request output instruction to the image transfer request output circuit 30 for the next horizontal synchronization period, and is stored in the display FIFO memory 22. Control to reuse data.

  Next, in the method of FIG. 3, no special signal is issued to the CPU 18 after the processing for one line is completed. However, if the reception control circuit 36 receives the next horizontal synchronization signal and causes the image transfer request output circuit 30 to output an image data transfer request, it does not receive a data enable signal from the CPU 18, so It is determined that the data is equivalent to the previous line, and control for reusing the data stored in the display FIFO memory 22 is performed.

  Finally, in the method of FIG. 4, the reception control circuit 36 receives a signal indicating that it is equivalent from the CPU 18 until the next horizontal synchronization signal is received after the processing for one line is completed. Control for reusing the data stored in the display FIFO memory 22 without determining that the data for the next line is equivalent to the previous line and not giving a transfer request output instruction to the image transfer request output circuit 30 I do.

  When the image data is reused, the reception control circuit 36 determines that there is no bus use for image data transfer between the data reception circuit 20 and the CPU 18 and transfers data for other media. Control to do. For example, the reception control circuit 36 requests the CPU 18 to transfer audio data by controlling the audio transfer request output circuit 32 to output an audio data transfer request. Thus, the data receiving circuit 20 has a bus arbiter function.

  Next, processing on the CPU 18 side will be described in detail. FIG. 5 is a functional block diagram for explaining a first configuration example of the image data transfer necessity determination circuit 14. In this example, it is assumed that the display FIFO memory 22 stores image data for one frame, and that the data receiving circuit 20 can reuse the image data of the previous frame in units of pixels. In the configuration example shown in FIG. 5, the difference value | A−B | = C between the pixel data B in one frame and the corresponding pixel data A in the previous frame is calculated. Then, the difference value C is compared with a predetermined threshold value. If the difference value C is equal to or smaller than the threshold value, the reuse instruction signal is activated to indicate the reuse of the pixel data without transferring the pixel data. Is done. This configuration example is based on the fact that a minute difference cannot be seen by human eyes.

  The threshold shown in FIG. 5 is preferably a variable value corresponding to the brightness of the pixel data, that is, the magnitude of the luminance signal. That is, it is possible to increase the frequency of reuse by increasing the threshold value for dark images by using the fact that human eyes have low light and darkness and color discrimination ability. Moreover, this threshold value may be configured to be settable by the user. In this case, it is possible to provide a preset switch for setting a threshold value by the user.

  FIG. 6 is a functional block diagram for explaining a second configuration example of the image data transfer necessity determination circuit 14. In this example, it is assumed that the display FIFO memory 22 stores image data for one frame, and that the data receiving circuit 20 can reuse the image data of the previous frame in units of pixels. In the configuration example shown in FIG. 6, the difference value of the luminance signal (Y) component and the difference value of the chrominance signal (Cb, Cr) component are calculated for each corresponding pixel unit between one frame and the previous frame. Is done. If both of the difference values are equal to or less than a predetermined threshold value or at least one of the difference values is equal to or less than the predetermined threshold value, the pixel data is not transferred and is instructed to be reused. Therefore, the reuse instruction signal is activated. Note that the threshold value in this example is also preferably a variable value corresponding to the brightness of the pixel data.

  FIG. 7 is a functional block diagram for explaining a third configuration example of the image data transfer necessity determination circuit 14. In the configuration example shown in FIG. 7, AGC data relating to image data being received is analog / digital converted via an antenna 10 and an AGC (automatic gain control) circuit 12. Then, the converted AGC data is differenced from the AGC data that has been received and analog / digital converted a predetermined time ago, and the difference value of the AGC voltage level or the difference value of the AGC voltage fluctuation is calculated. If this difference value is greater than or equal to a predetermined threshold value, the image data being received is not transferred.

  When the image data being received is not transferred as described above, the data receiving circuit 20 preferably does not display the image on the display device 40. This is because the in-vehicle TV signal has a large variation in the received electric field, and the screen can hardly be recognized. In addition, since the fluctuation of the AGC voltage increases as the vehicle speed increases, the threshold value is preferably a variable value corresponding to the vehicle speed. In addition, since the fluctuation of the AGC voltage increases as the reception frequency increases, the threshold value may be a variable value corresponding to the reception frequency. Furthermore, the threshold value can be a variable value corresponding to the vehicle speed and the reception frequency. Alternatively, the threshold value may be configured to be settable by the user, and a preset switch can be provided for this purpose.

  As a modification of the configuration of FIG. 5 described above, a corresponding line unit difference value between one frame and the previous frame is calculated, and if the difference value is equal to or less than a predetermined threshold value, The line data may be instructed to be reused without transferring the line data.

  FIG. 8 is a functional block diagram for explaining a fourth configuration example of the image data transfer necessity determination circuit 14. In the configuration example shown in FIG. 8, it is assumed that the display FIFO memory 22 stores image data for one frame. In this example, the difference value | A−B | = C between the pixel data B in one frame and the corresponding pixel data A in the previous frame is calculated. The difference value C is cumulatively added for one frame. Thus, the difference value between one frame and the previous frame is calculated, and if the difference value is equal to or less than a predetermined threshold, the previous frame data is reused without transferring the frame data. As such, the reuse instruction signal is activated.

  Hereinafter, further configuration examples for reducing the image data transfer amount according to the present invention will be described. In the example shown in FIG. 9, the CPU 18 transfers data for one line composed of an average value between n lines, as shown in FIG. Then, the data receiving circuit 20 repeats the transferred data for one line for n lines and causes the display device to display the data. Thus, the image data transfer amount is reduced.

  In addition, the display FIFO memory 22 can be configured as a buffer that stores image data for a half frame or a predetermined number of pixels. Specifically, a circuit that issues a transmission request to the CPU (host) before the buffer becomes empty using a small-capacity FIFO, flip-flop (FF), memory, etc. And a circuit for outputting data. Although it is inferior in terms of the CPU interrupt interval and the degree of freedom of image processing as compared with the case of having a line memory, it requires less memory capacity and is advantageous in constructing an inexpensive system.

  Further, the display FIFO memory 22 may be composed of at least two memories corresponding to the image data being transferred and the image data being displayed. Specifically, a memory that can be divided into a plurality of areas or a plurality of areas, a circuit that manages the empty or remaining amount of the memory, and a circuit that outputs data in synchronization with the image from the memory are provided. Like that. By configuring the memory (buffer) in a plurality of areas, the degree of freedom in the transfer interval is increased, which is effective in a system equipped with a host (CPU) that handles a plurality of images or a plurality of media.

  Further, the reception control circuit 36 can output an image data transfer request to the CPU 18 at a timing corresponding to the enlargement or reduction when the image is enlarged or reduced. Specifically, when it is necessary to display the same line twice according to the setting of enlargement, a data transfer request for one time is made to the CPU 18 for the display for two times. On the other hand, when the reduction is set, a circuit for performing differentiation or the like on each pixel according to the number of reductions and outputting data in synchronization with the image is provided. In this way, it is not necessary to transfer the same data multiple times, and the host occupancy rate is reduced.

  In addition, the reception control circuit 36 can be configured to notify the CPU 18 of an address necessary for the next transfer when thinning reproduction is required. Specifically, before issuing a transfer request, a circuit for notifying the CPU 18 of the requested address, length, address skipping width, etc., and a circuit for outputting data from the memory in synchronism are provided. When the image is cut out or displayed on the same monitor, once the setting is made on the data receiving side, the host (CPU) will judge and request an address from the next time. This is advantageous in the cost efficiency of a system with a low CPU processing capacity.

  In addition, the reception control circuit 36 can be configured to notify the necessary address and to perform enlargement by reading back the same address a plurality of times when performing partial enlarged display of the image. Specifically, before issuing a transfer request, a circuit that notifies the CPU 18 of the requested address and length, cuts and transfers the screen, and a circuit that repeatedly displays the same memory in the horizontal or vertical direction according to the display pixel. And are provided. In image zooming and cutout enlargement display, once the data receiving circuit (device) is set, the host (CPU) will judge and request an address from the next time, so the processing capability of the host (CPU) is low. It is advantageous in terms of cost efficiency of the system.

1 is a block diagram showing an embodiment of an image processing system according to the present invention. It is a figure for demonstrating the 1st method in which CPU instruct | indicates reuse of image data with respect to a data receiving circuit. It is a figure for demonstrating the 2nd method in which CPU instruct | indicates reuse of image data with respect to a data receiving circuit. It is a figure for demonstrating the 3rd method in which CPU instruct | indicates the reuse of image data with respect to a data receiving circuit. It is a functional block diagram for demonstrating the 1st structural example about an image data transfer necessity determination circuit. It is a functional block diagram for demonstrating the 2nd structural example about an image data transfer necessity determination circuit. It is a functional block diagram for demonstrating the 3rd structural example about an image data transfer necessity determination circuit. FIG. 10 is a functional block diagram for explaining a fourth configuration example of the image data transfer necessity determination circuit. It is a figure for demonstrating the further structural example for reducing the amount of image data transfers.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Antenna 12 AGC (automatic gain control) circuit 14 Image data transfer necessity judgment circuit 16 Storage medium 18 CPU (central processing unit)
20 Data Receiving Circuit 22 Display FIFO Memory 24 Display Interface Circuit 26 Audio FIFO Memory 28 Audio Interface Circuit 30 Image Transfer Request Output Circuit 32 Audio Transfer Request Output Circuit 34 Horizontal and Vertical Sync Signal Generation Circuit 36 Reception Control Circuit 40 Display Device

Claims (20)

An image processing system comprising: an image data receiving circuit for receiving image data and displaying an image on a display device; and a central processing unit for transferring the image data to the image data receiving circuit, wherein the image data receiving circuit ,
A buffer for storing a certain amount of image data transferred from the central processing unit;
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in image display;
Transfer request output means for outputting an image data transfer request to the central processing unit;
Control is performed so that the transfer request output means outputs an image data transfer request in synchronization with a horizontal synchronization signal or a vertical synchronization signal until the image data is filled in the buffer, and the buffer according to an instruction from the central processing unit Image data reception control means for performing control of reusing the image data already stored in the image data as image data to be newly transferred;
Comprising the central processing unit,
An image that instructs the image data receiving circuit to reuse image data without transferring the image data when the already transferred image data can be reused as image data to be newly transferred. Data transfer necessity determination means,
An image processing system comprising:   The buffer stores image data for one line, and the image data reception control unit is configured to receive image data for the next line after reception of the image data for one line is completed. 2. The image processing system according to claim 1, wherein the central processing unit is inquired as to whether they are equivalent, and the image data transfer necessity determination unit responds whether or not reuse is possible in response to the inquiry.   The buffer stores image data for one line, and the image data reception control means outputs an image data transmission request for the next line after completing reception of the image data for one line. The image processing system according to claim 1, wherein reuse is executed when a data enable signal is not received from the central processing unit.   The buffer stores image data for one line, and the image data reception control means, after completing the reception of the image data for one line, before outputting an image data transmission request for the next line. The image processing system according to claim 1, wherein reuse is executed when a signal instructing reuse is received from the central processing unit.   The data transfer for other media is performed by recognizing that there is no bus use for image data transfer between the image data receiving circuit and the central processing unit when the image data is reused. Image processing system.   The buffer stores image data for one frame, and the image data transfer necessity determination unit calculates a corresponding pixel unit difference value between one frame and the previous frame, The image processing system according to claim 1, wherein if the difference value is equal to or less than a predetermined threshold value, the pixel data is instructed to be reused without being transferred.   The buffer stores image data for one frame, and the image data transfer necessity determination unit determines a difference between luminance signal components in a corresponding pixel unit between one frame and the previous frame. The difference value between the value and the chrominance signal component is calculated, and if both of the difference values or at least one of them is less than or equal to a predetermined threshold value, the pixel data is not transferred and the reuse of the pixel data is instructed. The image processing system according to claim 1. The image processing system according to claim 6 or 7, wherein the threshold value is a variable value corresponding to the brightness of pixel data of a previous frame . The image data transfer necessity determination means calculates an AGC voltage level difference value or an AGC voltage fluctuation difference value between the currently received image data and the image data received a predetermined time ago, and the difference The image processing system according to claim 1, wherein if the value is equal to or greater than a predetermined threshold value, the image data being received is not transferred.   The image processing system according to claim 9, wherein when the image data being received is not transferred, the image data receiving circuit does not display an image on a display device.   The image processing system according to claim 9, wherein the threshold value is a variable value corresponding to a vehicle speed and / or a reception frequency.   The image processing system according to claim 6, wherein the threshold value is configured to be settable by a user.   The buffer stores image data for one frame, and the image data transfer necessity determination unit calculates a corresponding line unit difference value between one frame and the previous frame, The image processing system according to claim 1, wherein if the difference value is equal to or smaller than a predetermined threshold value, the line data is instructed to be reused without being transferred.   The buffer stores image data for one frame, and the image data transfer necessity determination unit calculates a difference value between one frame and the previous frame, and the difference value is predetermined. 2. The image processing system according to claim 1, wherein if it is equal to or less than the threshold value, the frame data is instructed to be reused without being transferred.   The central processing unit transfers data for one line composed of an average value between n lines, and the image data receiving circuit repeatedly displays the transferred data for one line for n lines. The image processing system according to claim 1, wherein the image processing system is displayed on a device.   The image processing system according to claim 1, wherein the buffer stores image data for a half frame or a predetermined number of pixels.   The image processing system according to claim 1, wherein the buffer includes at least two memories corresponding to image data being transferred and image data being displayed. It said image data receiving control means performs control to change the number of times said to central processing unit outputs the images data transfer request at the time of enlargement or reduction of an image, the image processing system according to claim 1. The image processing system according to claim 1, wherein the image data reception control unit notifies the central processing unit of information related to the thinning reproduction when thinning reproduction is necessary. 2. The image data reception control unit according to claim 1, wherein when performing partial enlarged display of an image, the image data reception control unit notifies an address of a portion to be enlarged and displays the same address multiple times to realize enlargement. Image processing system.

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