JP4810451B2 - Layout design system and semiconductor integrated circuit device design method - Google Patents

Description

  The present invention relates to a design technique of a semiconductor integrated circuit device, and more particularly to a technique effective for layout design in a logic circuit.

  Some of the semiconductor integrated circuit devices such as semiconductor memories and microcomputers include asynchronous circuits, and the layout design thereof is mainly performed by a transistor level hand packing method.

  Up to now, the layout of the asynchronous circuit has been designed in advance based on the resistance value and capacitance value of the parasitic element. Entered the pattern.

  At that time, in order to finally verify with high accuracy by comparing with the value obtained by hand calculation while looking at the layout data, whether the layout design is the same as the resistance value and capacitance value specified in the logic circuit diagram Then, verification of whether the logical diagram and the layout diagram match (generally called LVS (Layout Versus Schematic)) is performed.

  In addition, care related to signal integrity such as crosstalk noise is also communicated from the logic designer to the layout designer, and the signal lines that are susceptible to noise and the signal lines that are susceptible to noise are designed not to be adjacent to each other. ing.

  However, the present inventors have found that the above-described asynchronous circuit layout design technique has the following problems.

  That is, if the match can be confirmed by the verification by LVS, it is necessary to extract the parasitic capacitance and parasitic resistance, and then perform a simulation to analyze the timing and confirm it, which takes a lot of processing time. is there.

  Further, when a violation occurs in the timing analysis, a reversion to the logical design or layout design occurs, which causes an increase in the design period.

  An object of the present invention is to provide a technique capable of greatly reducing violations in timing analysis after layout design and greatly reducing the period of layout correction in a logic circuit and the number of reworks to the logic design stage. It is in.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention relates to a layout design system for supporting layout design of a logic circuit in a semiconductor integrated circuit device, which extracts logic connection information from a logic circuit diagram and performs layout design based on the logic connection information. The parasitic capacitance and parasitic resistance of any wiring that connects between the elements in the wiring layout are extracted, and the extracted parasitic capacitance and parasitic capacitance and parasitic resistance included in the logical connection information are extracted. And a comparison / violation information generator that outputs error information when the extracted parasitic capacitance or parasitic resistance is larger than the parasitic capacitance or parasitic resistance of the logical connection information.

  Further, according to the present invention, the layout editing control unit includes a logic circuit diagram storage unit for storing a logic circuit diagram to which logic connection information is input, and a logic connection from the logic circuit diagram stored in the logic circuit diagram storage unit. A logical connection information extracting unit for extracting information and a layout editing unit for designing a layout based on the logical connection information extracted by the logical connection information extracting unit. Among the layout patterns being input, an RC extraction unit that extracts parasitic capacitance and parasitic resistance of an arbitrary wiring pattern at the input stage of the wiring pattern, and a parasitic capacitance, parasitic resistance and logical connection information extraction unit extracted by the RC extraction unit Is compared with the parasitic capacitance and parasitic resistance included in the extracted logical connection information, and the comparison unit outputs the comparison result, and the RC information based on the comparison result of the comparison unit When the parasitic capacitance and parasitic resistance stored in the storage unit are larger than the resistance value and capacitance included in the logical connection information, it is determined that the resistance value and capacitance restrictions are violated and output as error information. It consists of an RC value / violation information generator.

  Further, according to the present invention, the comparison / violation information generation unit feeds back the parasitic resistance and capacitance values extracted by the RC extraction unit to the logic circuit diagram stored in the logic circuit diagram storage unit. The layout editing unit displays the parasitic resistance and parasitic capacitance values extracted by the RC extraction unit after the layout design on the logic circuit diagram.

  Further, the present invention provides a wiring list file storage unit for storing a wiring list file in which the layout editing control unit defines signal lines that are easily affected by crosstalk, names of signal lines that are easily affected, and special wiring rules. Coupling capacity when a signal line that is easily affected by crosstalk described in the wiring list file stored in the wiring list file storage unit and a signal line that is easily affected cross or run in parallel. A limit value file storage unit that stores a limit value file that stores the limit value of the signal, and the RC extraction unit performs parallel processing on signals defined in the wiring list file when extracting parasitic capacitance and parasitic resistance of the wiring. The inter-wiring capacitance, overlapping capacitance, etc. are extracted, and the comparison unit determines the limit value in the limit value file and the parasitic capacitance, parasitic resistance value, wiring width, and interval extracted by the RC extraction unit. Comparison, RC value / violation information generating unit, when it is determined that exceeds the limit value of the limit value file, and outputs the error information as a violation.

  Further, according to the present invention, the comparison / violation information generation unit feeds back the parasitic resistance and capacitance values extracted by the RC extraction unit to the logic circuit diagram stored in the logic circuit diagram storage unit. And a simulation execution unit that executes circuit simulation based on a logical circuit diagram obtained by feeding back the parasitic resistance and parasitic capacitance values of the actual layout extracted by the RC extraction unit by the RC value feedback unit.

  Further, according to the present invention, error information output from the comparison / violation information generation unit is displayed on a layout drawing designed by the layout editing control unit.

  Furthermore, according to the present invention, the logical connection information extracted by the layout editing control unit includes property information such as a device name, an instance name, and a size in which the layout is arranged, connection information between devices, and parasitic capacitance and parasitic resistance of wiring. Includes limit values.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The present invention is a semiconductor integrated circuit device design method for designing a layout of a logic circuit provided in a semiconductor integrated circuit device, and extracts logical connection information from a logical circuit diagram stored in a logic circuit diagram storage unit. A step of designing a layout based on the logical connection information, a step of extracting a parasitic capacitance and parasitic resistance of an arbitrary laid-out wiring, and a step of extracting a wiring included in the extracted parasitic capacitance, parasitic resistance and logical connection information. Comparing the parasitic capacitance and the limit value of the parasitic resistance, and displaying the error information on the layout diagram when the parasitic capacitance or the parasitic resistance is larger than the limit value.

  Further, the present invention includes a step of feeding back the parasitic resistance and capacitance values extracted by the step of extracting the parasitic capacitance and parasitic resistance of the arbitrary wiring and displaying them on a logic circuit diagram.

  Furthermore, the present invention extracts the logical connection information from the logical circuit diagram stored in the logical circuit diagram storage unit, performs the layout design based on the logical connection information, and the wiring parasitic capacitance and parasitic resistance. At the time of extraction, the signal lines that are easily affected by crosstalk, the signal line names that are easily affected, and the signals defined in the wiring list file that defines special wiring rules are extracted. And the step of comparing the limit value of the limit value file that stores the limit value of the coupling capacitance when crossing or running in parallel with the extracted parasitic capacitance, parasitic resistance value, wiring width, and interval respectively A step of displaying error information on a layout diagram when it is determined that the limit value of the value file is exceeded.

  The present invention also includes a step of feeding back the parasitic resistance and capacitance value extracted by the step of extracting the parasitic capacitance and parasitic resistance of the arbitrary wiring, and the extracted parasitic resistance and capacitance value thus fed back. And executing a simulation based on the logic circuit diagram including the step of displaying the simulation result.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The return to logic design and layout design can be greatly reduced.

  (2) Further, the number of logic circuit diagram edits and the number of layout edits can be reduced.

  (3) By the above (1) and (2), the design period in the semiconductor integrated circuit device can be significantly shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a block diagram showing a configuration example of an EDA system according to Embodiment 1 of the present invention, FIG. 2 is a flowchart showing an example of layout design processing by the EDA system of FIG. 1, and FIG. 3 is an EDA system of FIG. It is explanatory drawing which shows an example of the logic circuit diagram stored in the logic circuit diagram storage part provided in FIG.

  In the first embodiment, an EDA (Electronics Design Automation) system 1 is a tool that supports layout design of a semiconductor device in a semiconductor integrated circuit device, for example.

  As shown in FIG. 1, an EDA system 1 serving as a layout design system includes a logical circuit diagram storage unit 2, a logical connection information extraction unit 3, a logical connection information storage unit 4, and a layout editing unit 5 that function as a layout editing control unit. And a layout data storage unit 6 that functions as a comparison / violation information generation unit, an RC extraction unit 7, an RC information storage unit 8, a comparison unit 9, an RC value / violation information generation unit 10, and a display unit 11. Yes.

  The logic circuit diagram storage unit 2 stores a logic circuit diagram to which logic connection information is input. A logical connection information extraction unit 3 is connected to the logical circuit diagram storage unit 2. The logical connection information extraction unit 3 extracts from the logical circuit diagram storage unit 2 property information such as the arranged device name, instance name, size, connection information between devices (hereinafter referred to as logical connection information). To do.

  A logical connection information storage unit 4 is connected to the logical connection information extraction unit 3. The logical connection information storage 4 stores the logical connection information extracted by the logical connection information extraction unit 3.

  The layout editing unit 5 performs layout input and editing operations in consideration of the logical connection information stored in the logical connection information storage unit 4. A logical connection information storage unit 4, a layout data storage unit 6, an RC extraction unit 7, an RC value / violation information generation unit 10, and a display unit 11 are connected to the layout editing unit 5, respectively.

  The layout data storage unit 6 stores the layout data of the layout editing unit 5. The RC extraction unit 7 includes the parasitic capacitance and parasitic resistance of the target wiring pattern at the input stage of the wiring pattern (wiring pattern can be easily recognized by the layout layer number) among the layout patterns being input by the layout editing unit 5. To extract.

  A layout data storage unit 6, an RC information storage unit 8, and a comparison unit 9 are connected to the RC extraction unit 7. The RC information storage unit 8 stores the parasitic capacitance (C) and parasitic resistance (R) extracted by the RC extraction unit 7.

  The comparison unit 9 is connected to the logical connection information storage unit 4, the RC information storage unit 8, and the RC value / violation information generation unit 10. The comparison unit 9 compares the RC information stored in the logical connection information storage unit 4 with the RC value between the RC information storage unit 8 and outputs the comparison result to the RC value / violation information generation unit 10.

  A layout editing unit 5 is connected to the RC value / violation information generating unit 10. The RC value / violation information generation unit 10 determines the comparison result of the comparison unit 9, generates error information when a violation occurs, and causes the display unit 11 to display the information via the layout editing unit 5. At the same time, the RC value extracted by the RC extraction unit 7 is displayed on the display unit 11 via the layout editing unit 5.

  The display unit 11 includes, for example, a display and displays a layout pattern edited by the layout editing unit 5.

  Next, the operation of the EDA system 1 according to the first embodiment will be described using the processing flow of FIG. 2 and the logic circuit diagram example of FIG.

  As shown in FIG. 3, the logic circuit diagram is generally composed of input / output pins 12, transistors 13, basic logic gates 14, macro symbols 15, wirings 16 connecting the macro symbols 15, and the like.

  In order for the logic circuit to perform the operation desired by the logic designer, the timing of the propagated signal is important, and it is necessary to consider signal delay due to parasitic capacitance and parasitic resistance added to the wiring.

  Therefore, the logic designer usually adds a parasitic capacitance 17 and a parasitic resistance 18 that are expected in advance to the logic diagram and performs a simulation to check whether a desired operation is being performed.

  For important signal lines, the layout designer may instruct the layout wiring width / interval 19 expected by the layout designer. The layout designer performs the layout design according to the logic circuit diagram delivered from the logic designer. The logic design includes not only the above-mentioned elements such as transistors and their connection information, but also the parasitic capacitance and parasitic resistance added to the wiring. It is necessary to design so that it will become the intention and expected value.

  An object of the present invention is to provide an environment in which a layout can be easily designed so as to have a parasitic capacitance and a resistance value expected by a logic designer, and is realized by the processing flow shown in FIG.

  First, the logical connection information extraction unit 3 is stored in advance in the logical circuit diagram storage unit 2 in the same manner as a layout design apparatus (generally called a schematic driven layout apparatus) that performs layout design based on logical connection information. Corresponding logical connection information is extracted from the logical circuit diagram (step S101), and the extraction result is stored in the logical connection information storage unit 4.

  As described above, the logical connection information extracted by the logical connection information extraction unit 3 includes information on instance names such as transistors, input / output pins, basic gates, and macro symbols, pin names, cell names, and the like. In addition to property information such as the gate length and gate width, the values include parasitic resistance values and parasitic capacitance values, which are limit values inserted in advance in the logic circuit diagram.

  Subsequently, the layout editing unit 5 performs layout design according to the logical connection information stored in the logical connection information storage unit 4 as in the case of a general schematic driven layout device (step S102).

  At this time, if the wiring layout between elements is being input, the RC extraction unit 7 extracts the parasitic capacitance and the parasitic resistance of the wiring (step S103). In general, there are multiple methods for extracting parasitic capacitance, and the extraction accuracy and processing time are different for each. However, the algorithms for extraction methods can be processed at high speed in consideration of immediacy by using known methods. And

  In addition, the extraction by the RC extraction unit 7 can specify whether to perform extraction for all the wirings that are being input, or to extract only the signal lines in which parasitic capacitance and parasitic resistance extracted in the processing of step 101 are present. And

  Furthermore, although extraction is performed during input, it is also possible to perform extraction at a user's arbitrary step or at a specified signal line after completion of input or creation of a cell layout.

  The parasitic capacitance and parasitic resistance extracted by the RC extraction unit 7 are stored in the RC information storage unit 8. Subsequently, the comparison unit 9 compares the parasitic capacitance stored in the RC information storage unit 8 and the parasitic resistance with the parasitic resistance value and the capacitance value stored in the logical connection information storage unit 4 (steps). S104), and outputs the comparison result to the RC value / violation information generation unit 10.

  Based on the comparison result, the RC value / violation information generation unit 10 determines whether the parasitic capacitance and the parasitic resistance extracted by the RC extraction unit 7 are not violated, that is, stored in the RC information storage unit 8. It is determined whether or not the parasitic capacitance and the parasitic resistance thus exceeded exceed the resistance value and the capacitance value stored in the logical connection information storage unit 4 (step S105).

  If it does not exceed in the process of step S105, the layout design of step S102 ends. If it exceeds in the process of step S105, error information is generated as a violation and output to the layout editing unit 5. .

  The layout editing unit 5 receives the error information from the RC value / violation information generation unit 10 and displays the error information on the layout diagram of the display unit 11 (step S106). Guidance is made so that the layout can be designed in compliance with the constraints added at the stage.

  As a result, according to the first embodiment, the layout design can be performed while satisfying the restrictions on the parasitic capacitance and the parasitic resistance given to the signal line that the logic designer has strict timing restrictions in advance.

  Compared to the design process flow in which simulation is performed after extracting parasitic capacitance and resistance after completing normal layout design, it is possible to significantly reduce rework to logic design and layout design. It can be dramatically shortened.

(Embodiment 2)
FIG. 4 is a block diagram showing a configuration example of the EDA system according to the second embodiment of the present invention, and FIG. 5 is a flowchart showing a processing example of layout design by the EDA system of FIG.

  In the second embodiment, as shown in FIG. 4, the EDA system 1 includes a logical circuit diagram storage unit 2, a logical connection information extraction unit 3, a logical connection information storage unit 4 and a layout in FIG. An RC value feedback unit 20 is newly provided in the editing unit 5, the layout data storage unit 6, the RC extraction unit 7, the RC information storage unit 8, the comparison unit 9, the RC value / violation information generation unit 10, and the display unit 11. It becomes the composition.

  The RC value feedback unit 20 is connected to the RC value / violation information generation unit 10 and the logic circuit diagram storage unit 2. The RC value feedback unit 20 feeds back the parasitic resistance and parasitic capacitance values of the actual layout extracted by the RC extraction unit 7 to the logic circuit diagram stored in the logic circuit diagram storage unit 2.

  Next, the operation of the EDA system 1 in the second embodiment will be described using the processing flow of FIG.

  In FIG. 5, steps S201 to S206 are the same as the processing of steps S101 to S106 in FIG. After the layout design in step S202 is completed, the RC value feedback unit 20 uses the actual layout parasitic resistance and parasitic capacitance values extracted by the RC extraction unit 7 as the logic circuit of the logic circuit diagram storage unit 2. Feedback is made to the figure (step S207).

  In the process of step S207, it is possible to select whether to feed back the parasitic capacitance and parasitic resistance previously inserted in the logic circuit diagram or to feed back to the designated net.

  Accordingly, in the second embodiment, the actual RC value extracted by the RC extraction unit 7 after the layout design can be reflected in the logic circuit diagram, so that the logic designer can obtain a more accurate layout information estimation result. Thus, the logic circuit diagram can be edited, and the number of logic circuit diagram edits and the number of layout edits can be reduced.

(Embodiment 3)
FIG. 6 is a block diagram showing a configuration example of the EDA system according to the third embodiment of the present invention, and FIG. 7 is a flowchart showing an example of layout design processing by the EDA system of FIG.

  In the third embodiment, as shown in FIG. 6, the EDA system 1 includes a logical circuit diagram storage unit 2, a logical connection information extraction unit 3, a logical connection information storage unit 4 and a layout in FIG. 1 of the first embodiment. The editing unit 5, the layout data storage unit 6, the RC extraction unit 7, the RC information storage unit 8, the comparison unit 9, the RC value / violation information generation unit 10, and the display unit 11, the wiring list file storage unit 21 and the limit value file The storage unit 22 is newly provided. The layout editing unit 5 is connected to the wiring list file storage unit 21 and the limit value file storage unit 22, respectively.

  The wiring list file storage unit 21 stores a wiring list file in which signal lines that are easily affected by crosstalk, signal line names that are easily affected, and special wiring rules (wiring width, spacing, etc.) are defined.

  The limit value file storage unit 22 includes signal lines that are easily affected by crosstalk described in the wiring list file stored in the wiring list file storage unit 21 and signal lines that are easily affected by crossing or in parallel. A limit value file that stores the limit value of the coupling capacity when running is stored.

  The layout editing unit 5 uses the logical connection information extracted from the logical circuit diagram, the RC value extracted from the logical connection information stored in the logical connection information storage unit 4, and the wiring stored in the limit value file storage unit 22. The layout is edited while referring to the coupling capacity limit value of the list file and guiding the value so as not to exceed the value.

  Furthermore, when extracting the parasitic capacitance and parasitic resistance at the layout design stage, the RC extraction unit 7 is described in the total parasitic capacitance of the target signal line and the wiring list file stored in the wiring list file storage unit 21. In the case of signal lines, the coupling capacitance is individually extracted as a comparison target.

  The comparison unit 9 includes the parasitic capacitance, parasitic resistance, and coupling extracted by the RC extraction unit 7, the RC value extracted from the logical connection information in the logical connection information storage unit 4, and the limit value file in the limit value file storage unit 22. Compare with. If the result is a violation, the violation part and the violation value are displayed on the display unit 11.

  FIG. 7 is a processing flow showing an operation example of the EDA system 1 according to the third embodiment.

  First, the logical connection information extraction unit 3 is stored in advance in the logical circuit diagram storage unit 2 in the same manner as a layout design apparatus (generally called a schematic driven layout apparatus) that performs layout design based on logical connection information. Corresponding logical connection information is extracted from the logical circuit diagram (step S301), and the extraction result is stored in the logical connection information storage unit 4.

  Subsequently, the layout editing unit 5 receives from the wiring list file storage unit 21 a signal line name that is easily affected by crosstalk, a signal line name that is easily affected, and a signal to which special restrictions other than the default wiring width and interval are added. A wiring list file describing the line name and its constraint value is read (step S302).

  Then, the layout editing unit 5 reads from the wiring list file storage unit 21 a limit value file that defines the capacity between the parallel wirings and the overlapping capacity value in which the influence of crosstalk is a problem (step S302).

  In the third embodiment, the flow is defined by reading the limit value in the external file. However, the menu is displayed from the layout design apparatus, and the user directly imports the signal line name and the limit value into the layout design apparatus. Is also possible.

  Subsequently, the layout editing unit 5 performs a layout design according to the logical connection information extracted by the logical connection information extraction unit 3 as in a general schematic driven layout device (step S304).

  Then, if the wiring layout between elements is being input, the RC extraction unit 7 extracts the parasitic capacitance and parasitic resistance of the wiring (step S305) and stores them in the RC information storage unit 8. In addition, as in the first embodiment, it is possible to specify whether extraction is performed for all wirings that are being input, or only signal lines in which parasitic capacitance and parasitic resistance extracted in the process of step S301 are extracted. Shall.

  Further, when extracting, for the signal lines defined in the total wiring capacity and the wiring list file, that is, the signal lines that are concerned about the influence of crosstalk, information such as the capacity between the parallel wirings and the overlapping capacity is also stored. Shall.

  Then, the comparison unit 9 compares the limit value of the limit value file with the extracted parasitic capacitance, parasitic resistance value, wiring width, interval, and the like (step S306), and outputs the comparison result to the RC value / violation information generation unit 10. To do.

  If the RC value / violation information generating unit 10 determines that the limit value of the limit value file has been exceeded (step S307), the RC value / violation information generating unit 10 generates error information as a violation and outputs the error information to the layout editing unit 5. Violation is displayed on the display unit 11 via 5 (step S308).

  If the limit value of the limit value file is not exceeded (step S307), the parasitic capacitance, parasitic resistance value, wiring width, interval, etc. extracted in the process of step S305 are displayed on the layout via the display device in real time. By displaying on the screen, the user can guide the layout design so that the user can comply with a desired constraint, that is, a constraint added in the logic design stage.

  As a result, in the third embodiment, design is performed in consideration of information related to crosstalk and special wiring restrictions (wiring width, spacing, wiring layer, etc.) in addition to the wiring capacity and wiring resistance in the layout design stage. This makes it possible to reduce the number of design rework due to a timing violation after layout design or a constraint violation at the time of wiring, and thus the design period can be greatly shortened.

(Embodiment 4)
FIG. 8 is a block diagram showing a configuration example of the EDA system according to the fourth embodiment of the present invention, and FIG. 9 is a flowchart showing an example of layout design processing by the EDA system of FIG.

  In the fourth embodiment, as shown in FIG. 8, the EDA system 1 includes a logical circuit diagram storage unit 2, a logical connection information extraction unit 3, a logical connection information storage unit 4 and a layout in FIG. 4 of the second embodiment. The simulation unit 23, the layout data storage unit 6, the RC extraction unit 7, the RC information storage unit 8, the comparison unit 9, the RC value / violation information generation unit 10, the display unit 11, and the RC value feedback unit 20 The simulation result storage unit 24 is newly provided.

  A logic circuit diagram storage unit 2 is connected to the simulation execution unit 23. The simulation execution unit 23 performs an actual circuit simulation using the logic circuit diagram in which the parasitic resistance and parasitic capacitance values of the actual layout are fed back by the RC value feedback unit 20 as input.

  In addition, a simulation execution unit 23 is connected to the simulation result storage unit 24 and stores a simulation result by the simulation execution unit 23. The simulation result stored in the simulation result storage unit 24 is displayed on the display unit 11 via the layout editing unit 5.

  FIG. 9 is a flowchart showing an example of a processing flow of the EDA system according to the fourth embodiment.

  In FIG. 9, the processing of steps S401 to S407 is the same as the processing of steps S201 to S207 in FIG. 5 of the second embodiment.

  When the feedback to the logic circuit diagram of the parasitic resistance and parasitic capacitance values of the actual layout by the RC value feedback unit 20 in step S407 is completed, the simulation execution unit 23 actually extracts the data stored in the logic circuit diagram storage unit 2 The simulation is executed based on the logic circuit diagram including the information on the parasitic resistance and the parasitic capacitance value (step S408), the timing analysis is performed, and the simulation result is stored in the simulation result storage unit 24.

  The simulation result stored in the simulation result storage unit 24 is displayed on the display unit 11 by the layout editing unit 5 and analyzed based on the display.

  As a result, according to the fourth embodiment, the logic circuit diagram including the actual RC value information extracted after the layout design can be used as an input to actually execute the simulation and analyze the timing. The construction period can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for logic circuit layout design support technology in a semiconductor integrated circuit device.

It is a block diagram which shows the structural example of the EDA system by Embodiment 1 of this invention. 3 is a flowchart showing an example of layout design processing by the EDA system of FIG. 1. FIG. 2 is an explanatory diagram illustrating an example of a logic circuit diagram stored in a logic circuit diagram storage unit provided in the EDA system of FIG. 1. It is a block diagram which shows the structural example of the EDA system by Embodiment 2 of this invention. 5 is a flowchart showing an example of layout design processing by the EDA system of FIG. 4. It is a block diagram which shows the structural example of the EDA system by Embodiment 3 of this invention. 7 is a flowchart showing an example of layout design processing by the EDA system of FIG. 6. It is a block diagram which shows the structural example of the EDA system by Embodiment 4 of this invention. 7 is a flowchart showing an example of layout design processing by the EDA system of FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 EDA system 2 Logical circuit diagram storage part 3 Logical connection information extraction part 4 Logical connection information storage part 5 Layout edit part 6 Layout data storage part 7 RC extraction part 8 RC information storage part 9 Comparison part 10 RC value / violation information generation part 11 Display Unit 12 Input / Output Pin 13 Transistor 14 Basic Logic Gate 15 Macro Symbol 16 Wiring 17 Parasitic Capacitance 18 Parasitic Resistance 19 Wiring Width / Interval 20 RC Value Feedback Unit 21 Wiring List File Storage Unit 22 Limit Value File Storage Unit 23 Simulation Execution Unit 24 Simulation result storage

Claims (11)

A layout design system for supporting layout design of a logic circuit in a semiconductor integrated circuit device,
A layout editing control unit that extracts logical connection information from the logical circuit diagram and performs layout design based on the logical connection information;
The parasitic capacitance and parasitic resistance of an arbitrary wiring connecting between the elements laid out in the wiring are extracted, and the extracted parasitic capacitance and the parasitic capacitance and parasitic resistance included in the parasitic resistance and the logical connection information are extracted. A comparison / violation information generation unit that outputs error information when the extracted parasitic capacitance or parasitic resistance is larger than the parasitic capacitance or the parasitic resistance of the logical connection information. A layout design system characterized by that. The layout design system according to claim 1,
The layout editing control unit
A logic circuit diagram storage unit for storing a logic circuit diagram to which logic connection information is input;
A logical connection information extraction unit for extracting logical connection information from the logical circuit diagram stored in the logical circuit diagram storage unit;
Based on the logical connection information extracted by the logical connection information extraction unit, a layout editing unit that performs layout design,
The comparison / violation information generation unit
An RC extraction unit that extracts parasitic capacitance and parasitic resistance of an arbitrary wiring pattern in a wiring pattern input stage among layout patterns being input by the layout editing unit;
A comparison unit that compares the parasitic capacitance and parasitic resistance extracted by the RC extraction unit with the parasitic capacitance and parasitic resistance included in the logical connection information extracted by the logical connection information extraction unit, and outputs a comparison result;
Based on the comparison result of the comparison unit, when the parasitic capacitance and parasitic resistance extracted by the RC extraction unit are larger than the resistance value and capacitance included in the logic connection information, the resistance value and capacitance A layout design system comprising: an RC value / violation information generation unit that determines that a constraint violation occurs and outputs error information. The layout design system according to claim 2,
The comparison / violation information generation unit
An RC value feedback unit is provided for feeding back the parasitic resistance and capacitance values extracted by the RC extraction unit to the logic circuit diagram stored in the logic circuit diagram storage unit,
The layout editing unit
A layout design system, wherein a parasitic resistance and a parasitic capacitance value extracted by the RC extraction unit after layout design are displayed on the logic circuit diagram. The layout design system according to claim 2,
The layout editing control unit
A wiring list file storage section for storing a wiring list file that defines signal lines that are easily affected by crosstalk, signal line names that are easily affected, and special wiring rules;
Coupling capacity when a signal line susceptible to crosstalk described in the wiring list file stored in the wiring list file storage unit and a signal line susceptible to the crossing run in parallel or in parallel. A limit value file storage unit for storing a limit value file storing limit values;
The RC extraction unit
When extracting the parasitic capacitance and parasitic resistance of wiring, extract the parallel inter-wiring capacitance, overlapping capacitance, etc. for the signals defined in the wiring list file,
The comparison unit includes:
Compare the limit value of the limit value file with the parasitic capacitance, parasitic resistance value, wiring width, and interval extracted by the RC extraction unit,
The RC value / violation information generation unit
A layout design system that outputs error information as a violation when it is determined that the limit value of the limit value file is exceeded. The layout design system according to claim 2,
The comparison / violation information generation unit
An RC value feedback unit that feeds back the parasitic resistance and capacitance values extracted by the RC extraction unit to the logic circuit diagram stored in the logic circuit diagram storage unit;
A layout design system comprising: a simulation execution unit that executes a circuit simulation based on a logic circuit diagram obtained by feeding back the parasitic resistance and parasitic capacitance values of the actual layout extracted by the RC extraction unit by the RC value feedback unit. The layout design system according to claim 2 or 4,
The error information output by the comparison / violation information generation unit is:
A layout design system, wherein the layout editing control unit is displayed on a layout drawing designed by the layout editing control unit. In the layout design system according to any one of claims 1 to 6,
The logical connection information extracted by the layout editing control unit is:
A layout design system including property information such as a device name, instance name and size arranged, connection information between devices, and parasitic capacitance and parasitic resistance limit values of wiring. A design method of a semiconductor integrated circuit device for designing a layout of a logic circuit provided in a semiconductor integrated circuit device,
Extracting logical connection information from the logical circuit diagram stored in the logical circuit diagram storage unit, and performing a layout design based on the logical connection information;
A step of extracting parasitic capacitance and parasitic resistance of an arbitrary wiring laid out;
Compare the extracted parasitic capacitance and parasitic resistance with the wiring parasitic capacitance and parasitic resistance limit value included in the logical connection information, and lay out error information when the parasitic capacitance or parasitic resistance is larger than the limit value A method for designing a semiconductor integrated circuit device, comprising the step of: The method of designing a semiconductor integrated circuit device according to claim 8,
A method for designing a semiconductor integrated circuit device, comprising the step of feeding back a parasitic resistance and a capacitance value extracted in the step of extracting a parasitic capacitance and parasitic resistance of the arbitrary wiring and displaying them on a logic circuit diagram. The method of designing a semiconductor integrated circuit device according to claim 8,
Extracting logical connection information from the logical circuit diagram stored in the logical circuit diagram storage unit, and performing a layout design based on the logical connection information;
Parallel wiring for signals defined in a wiring list file that defines signal lines that are easily affected by crosstalk, names of signal lines that are easily affected, and special wiring rules when extracting parasitic capacitance and resistance of wiring Extracting the inter-capacity, overlap capacity, etc .;
A step of comparing the limit value of the limit value file storing the limit value of the coupling capacitance when running in parallel or in parallel with the extracted parasitic capacitance, parasitic resistance value, wiring width, interval,
And a step of displaying error information on a layout diagram when it is determined that the limit value of the limit value file has been exceeded. The method of designing a semiconductor integrated circuit device according to claim 8,
Feeding back the parasitic capacitance and capacitance value extracted by the step of extracting the parasitic capacitance and parasitic resistance of the arbitrary wiring;
A method for designing a semiconductor integrated circuit device, comprising: executing a simulation based on a logic circuit diagram including the fed back parasitic resistance and capacitance value, and displaying the simulation result.

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