JP4820665B2 - Display control circuit - Google Patents

Description

  The present invention relates to a display control circuit, and more particularly to access control for a video memory storing image data for display.

FIG. 2 is a configuration diagram of a conventional display control circuit.
This display control circuit temporarily accumulates display image data given from a CPU (Central Processing Unit) 1 via a system bus 2 and outputs it to a display device such as an LCD (Liquid Crystal Display) in accordance with the display timing. To do.

  The display control circuit includes a CPU I / F (Interface) unit 3, a phase adjustment unit 4, a memory control unit 5, a VRAM (Video Random Access Memory) 6, an LCD I / F unit 7, and a timing control unit 8. The CPU I / F unit 3 is for connecting to the CPU 1 via the system bus 2. The phase adjustment unit 4 adjusts the phase of the system clock SCLK on the CPU 1 side and the display clock DCLK for display. The memory control unit 5 controls access to the VRAM 6. The VRAM 6 temporarily accumulates display image data given from the CPU 1. The LCD I / F unit 7 converts the image data into a data format that matches the format of the display device and outputs it to an LCD (not shown). The timing controller 8 controls the operation timing of the entire display control circuit.

  This display control circuit operates in accordance with two clocks: a system clock SCLK for interfacing with the CPU 1 and a display clock DCLK as a synchronization signal for outputting display data to the LCD. The system clock SCLK is supplied to the CPU I / F unit 3 and the phase adjustment unit 4, and the display clock DCLK is supplied to the phase adjustment unit 4, the memory control unit 5, the VRAM 6, the LCD I / F unit 7, and the timing control unit 8. Yes.

  FIG. 3 is a signal waveform diagram showing the operation of FIG. 2 and shows a part of a signal output from the LCD I / F unit 7 to the LCD. The lower half of FIG. 3 is an enlarged display of a part of the upper half.

  As shown in FIG. 3, signals output to the LCD include a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and display data DATA. In general, display data DATA is not transferred during a certain period before and after the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC are sandwiched, and the respective periods are defined as a vertical blank period VB and a horizontal blank period HB.

  On the other hand, the VRAM 6 is accessed from the CPU 1 via the system bus 2, CPU I / F unit 3, phase adjustment unit 4 and memory control unit 5, and the image data stored in the VRAM 6 is stored in the memory. There is a read access to the LCD I / F unit 7 via the control unit 5. Among these, access for reading image data is periodically performed at a fixed timing according to the display clock DCLK.

  On the other hand, access for writing image data may be performed at an arbitrary timing or during the vertical blank period VB and the horizontal blank period HB.

  When image data is written at an arbitrary timing, there is a possibility that access for reading the image data occurs at the same time. In order to display an image, it is necessary to continue reading image data at a fixed timing, and therefore, read access must be given priority. Therefore, the memory control unit 5 has a function of waiting for the write access until the read access is completed when the write and read access occur simultaneously.

  When writing image data in accordance with the vertical blanking period VB and the horizontal blanking period HB, there is no possibility of competing with access for reading image data. Therefore, the write access is not waited until the read access is completed, but the write access is waited by the phase adjustment unit 4 in order to adjust the timing with the vertical blank period VB and the horizontal blank period HB. become.

JP-A-6-332845 International publication WO95 / 08168

  In the display control circuit, the phase adjustment unit 4 and the memory control unit 5 wait for the write access to the VRAM 6 from the CPU 1 so that the write and read accesses to the VRAM 6 do not compete. For this reason, there has been a problem that the operating efficiency of the CPU 1 is lowered.

  An object of the present invention is to eliminate the waiting time when the CPU writes to the VRAM.

  The present invention provides a display control circuit for temporarily storing image data for display given in synchronization with a system clock in a video memory, then reading the image data from the video memory according to the image clock, and outputting the image data to a display device. The system clock is selected while a vertical blank signal and a horizontal blank signal designating a period during which data is not transferred to the display device, and the image is output when the vertical blank signal and the horizontal blank signal are not output. A clock which selects a clock and supplies it to the image memory as an access clock signal, and outputs a status display signal indicating which of the system clock or the image clock is selected to the image data supply source It is characterized by providing a selection unit.

  In the present invention, the clock selection unit selects the system clock while the vertical blank signal or horizontal blank signal is output, and selects the image clock when these vertical blank signal and horizontal blank signal are not output. Thus, the selected clock signal is supplied to the image memory, and a status display signal indicating which one of the system clock and the image clock is selected is output to the image data supply source. Thereby, since CPU etc. which are the supply sources of image data can output image data according to the operation state of a display control circuit, waiting time at the time of writing to video memory from CPU etc. can be eliminated, There is an effect that the operation efficiency of the CPU or the like can be improved.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a display control circuit showing an embodiment of the present invention.
This display control circuit temporarily accumulates display image data provided from the CPU and outputs it to a display device such as an LCD in accordance with the display timing.

  The display control circuit includes a CPU I / F unit 11, a memory control unit 12, a VRAM 13, an LCD I / F unit 14, a timing control unit 15, and a clock selection unit 16. The CPU I / F unit 11 is for connecting to the CPU 1 via the system bus 2. The memory control unit 12 performs access control of the VRAM 13. The VRAM 13 temporarily stores display image data provided from the CPU 1. The LCD I / F unit 14 converts the image data into a data format that matches the format of the display device and outputs the data to an LCD (not shown). The timing control unit 15 controls the operation timing of the entire display control circuit.

  This display control circuit operates in accordance with two clocks: a system clock SCLK for interfacing with the CPU 1 and a display clock DCLK as a synchronization signal for outputting display data to the LCD. The system clock SCLK is given to the CPU I / F unit 11, the memory control unit 12, the timing control unit 15, and the clock selection unit 16. Further, the display clock DCLK is given to the memory control unit 12, the LCD I / F unit 7, and the clock selection unit 16.

  The clock selection unit 16 selects the system clock SCLK during a period when data transfer to the LCD is not performed, that is, during the vertical blank period VB and the horizontal blank period HB, and during the period when data transfer to the LCD is performed. The display clock DCLK is selected, and the selected clock signal CLK is supplied to the VRAM 13. For example, as shown in FIG. 1, the clock selection unit 16 includes an OR gate 16a that outputs a logical sum (OR) of a vertical blank signal VBLK and a horizontal blank signal HBLK output from the LCD I / F 14 as a selection signal SL; When the selection signal SL is at the level “H”, the system clock SCLK is selected. When the selection signal SL is at the level “L”, the selector (SEL) 16 b is selected to select the display clock DCLK. The selection signal SL is given to the CPU 1 as a state display signal for displaying the operation state of the display control circuit.

  FIG. 4 is a signal waveform diagram showing the operation of FIG. The lower half of FIG. 1 is an enlarged display of a part of the upper half. The operation of FIG. 1 will be described below with reference to FIG.

  As shown in the upper half of FIG. 4, when the vertical blank signal VBLK output from the LCD I / F 14 becomes “H” during the vertical blank period, the selection signal output from the OR gate 16a of the clock selection unit 16 in FIG. SL becomes “H”, the system clock SCLK is selected by the selector 16b, and is supplied to the VRAM 13 as the clock signal CLK. Thereby, the display image data output from the CPU 1 is written into the VRAM 13 in accordance with the system clock SCLK.

  Further, as shown in the lower half of FIG. 4, when the horizontal blank signal HBLK output from the LCD I / F 14 becomes “H” during the horizontal blank period, it is output from the OR gate 16a of the clock selection unit 16 in FIG. The selection signal SL becomes “H”, the system clock SCLK is selected by the selector 16b, and is supplied to the VRAM 13 as the clock signal CLK. Thereby, the display image data output from the CPU 1 is written into the VRAM 13 in accordance with the system clock SCLK.

  On the other hand, in a period that is neither a vertical blank period nor a horizontal blank period, the vertical blank signal VBLK and the horizontal blank signal HBLK are both “L”. Accordingly, the selection signal SL output from the OR gate 16a of the clock selection unit 16 in FIG. 1 becomes “L”, the display clock DCLK is selected by the selector 16b, and is supplied to the VRAM 13 as the clock signal CLK. Thereby, the display image data stored in the VRAM 13 is read according to the display clock DCLK and transferred to the LCD.

  As described above, the display control circuit of the present embodiment outputs the selection signal SL at “H” during the vertical blank period and the horizontal blank period, and selects the system clock SCLK or the display clock DCLK according to the selection signal SL. And a clock selection unit 16 for supplying to the VRAM 13. As a result, the CPU 1 can determine whether or not the access to the VRAM 16 is performed without contention by examining the selection signal SL, thereby preventing contention between the write access to the VRAM 16 from the CPU 1 and the read access to the image data from the VRAM 16 can do. Further, since the CPU 1 can perform other processing during a period in which the VRAM 16 cannot be accessed, there is an advantage that the waiting time for writing to the VRAM 16 does not occur and the operation efficiency is improved.

  Further, as the clock signal CLK supplied from the clock selection unit 16 to the VRAM 16, the system clock SCLK is selected when accessible from the CPU 1, and the display clock DCLK is selected when reading image data. Thus, if the CPU 1 does not access when the display clock DCLK is selected, there is an advantage that it is not necessary to perform phase alignment between the system clock SCLK and the display clock DCLK, and the circuit configuration can be simplified.

  In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. For example, the LCD has been described as the display device, but the present invention can be similarly applied to other display devices. Further, the configuration of the clock selection unit 16 is not limited to the illustrated circuit.

It is a block diagram of the display control circuit which shows the Example of this invention. It is a block diagram of the conventional display control circuit. FIG. 3 is a signal waveform diagram illustrating the operation of FIG. 2. It is a signal waveform diagram which shows the operation | movement of FIG.

Explanation of symbols

1 CPU
2 System bus 11 CPU I / F
12 Memory Control Unit 13 VRAM Timing Control Unit 14 LCD I / F
15 Timing control unit 16 Clock selection unit

Claims (1)

In a display control circuit that once stores image data for display given in synchronization with a system clock in a video memory, reads the image data from the video memory according to an image clock, and outputs the image data to a display device.
The system clock is selected while a vertical blank signal and a horizontal blank signal designating a period during which image data is not transferred to the display device, and when the vertical blank signal and horizontal blank signal are not output, the system clock is selected. An image clock is selected and supplied to the image memory as an access clock signal, and a status display signal indicating which of the system clock or the image clock is selected is output to the image data supply source. A display control circuit comprising a clock selection unit.

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