JP4820802B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to the manufacture of a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM (Dynamic Random Access Memory) and a logic integrated circuit are mixedly mounted. It is.

  In recent years, in the advanced technology fields such as multimedia and information communication, by realizing a system-on-chip structure in which a microcomputer, DRAM, ASIC, etc. are mixedly mounted on one chip, data transfer speed is increased and space saving (mounting) There is an active movement to increase the density) and reduce power consumption.

  One of the means for increasing the speed of the logic integrated circuit section is a technique for forming a silicide layer on the surfaces of the source and drain.

  However, if silicide is formed on the source and drain of the memory cell selection MISFET constituting the DRAM memory cell, the leakage current increases and the refresh characteristics are sacrificed.

  Thus, in order to achieve one-chip integration while maintaining the performances of both the DRAM and the logic integrated circuit, it is necessary to newly develop an embedded process suitable for one-chip integration.

  An object of the present invention is to provide a technique for realizing a one-chip implementation in a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted while maintaining the performances of the DRAM and the logic integrated circuit together. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a storage capacitor constituting a memory, a first MISFET to which the storage capacitor is connected, and a second MISFET constituting a peripheral circuit of the memory. In
(A) forming the first MISFET having a gate electrode, a source and a drain region in a first region of the main surface of the semiconductor substrate, and forming a gate electrode in a second region different from the first region of the main surface of the semiconductor substrate; Forming the second MISFET having source and drain regions;
(B) forming a first insulating film in the first region and the second region of the main surface of the semiconductor substrate so as to cover the first MISFET and the second MISFET;
(C) After forming a mask that selectively covers the first region, the first insulating film in the second region is etched by anisotropic first etching, and the first region Forming a first sidewall spacer formed of a part of the first insulating film on a side wall of the gate electrode of the 2MISFET, and removing the first insulating film in the other part; and in the first region, Leaving the first insulating film;
(D) after the step (c), removing the mask and forming a first metal film on the first insulating film in the first region and the second MISFET in the second region;
(E) after the step (d), by annealing the semiconductor substrate, forming a metal silicide film by the first metal film on the surface of the source and drain regions of the second MISFET;
(F) After the step (e), removing the unreacted first metal film that is not silicided by the annealing;
(G) after the step (f) , forming a second insulating film in the first region and the second region of the main surface of the semiconductor substrate so as to cover the first MISFET and the second MISFET;
(H) After the step (g), the second insulating film on the source and drain regions of the first MISFET is selectively and second etched by the second etching using the first insulating film as an etching stopper. Removing in a self-aligned manner with respect to the gate electrode of the first MISFET;
(I) After the step (h), by selectively removing the first insulating film on the source and drain regions of the first MISFET by an anisotropic third etching, the first MISFET Forming a first through hole exposing a surface of the source and drain regions, and forming a second sidewall spacer formed of a part of the first insulating film on a sidewall of the gate electrode of the first MISFET; When,
(J) after the step (i), forming a first electrode connected to the source and drain regions of the first MISFET through the first through hole;
Is included.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A high-speed operation of the logic integrated circuit can be realized and a decrease in the refresh characteristic of the DRAM can be avoided, so that it is possible to realize a one-chip while maintaining both the performance of the DRAM and the logic integrated circuit. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  As shown in FIG. 1, a semiconductor integrated circuit device according to the present embodiment includes a CPU (information processing unit), a memory unit composed of DRAM, a logic integrated circuit unit composed of ASIC, and an analog circuit unit in the same semiconductor. A microcomputer formed on the main surface of the chip.

  As shown in FIG. 2, the DRAM constituting the memory section of the microcomputer includes a memory array (MARY), a direct peripheral circuit composed of a sense amplifier, a row decoder and a column decoder adjacent to the memory array (MARY), an input / output circuit (not shown), The circuit includes an indirect peripheral circuit including a logic circuit, an address selection circuit, a read amplifier, a write amplifier, and the like.

  A DRAM memory array (MARY) is composed of a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells arranged at their intersections, which will be described later. One memory cell that stores 1-bit information is composed of one information storage capacitor C and one memory cell selection MISFET Qs connected in series therewith. One of the source and drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL.

  The left part (first region) of FIG. 3 is a cross-sectional view of the main part of the semiconductor substrate showing each part of the DRAM memory array (MARY) constituting the memory part of the microcomputer and the direct peripheral circuit adjacent thereto. The right part (second region) of the drawing is a cross-sectional view of the main part of the semiconductor substrate showing a part of the logic integrated circuit part.

  A p-type well 2 and an n-type well 3 are formed in the first region and the second region of the semiconductor substrate 1 made of p-type single crystal silicon. Although not particularly limited, the p-type well 2 common to the memory array (MARY) and a part of the peripheral circuit directly is used to prevent the influence of noise from circuits formed in other regions of the semiconductor substrate 1. The p-type semiconductor substrate 1 is electrically separated by an n-type semiconductor region 4 formed thereunder.

  Element isolation trenches 5 are formed on the respective surfaces of the p-type well 2 and the n-type well 3. The element isolation trench 5 has a structure in which a silicon oxide film is embedded in a trench formed in the semiconductor substrate 1, and its surface is substantially the same as the surfaces of the active regions of the p-type well 2 and the n-type well 3. It is flattened so that it is at the height.

  Memory cells are formed in the active region of the p-type well 2 of the memory array (MARY). Each of the memory cells includes an n-channel type MISFET Qs for memory cell selection and an information storage capacitive element C formed above the memory cell selection MISFET Qs and connected in series with the memory cell selection MISFET Qs. ing. That is, this memory cell has a stacked capacitor structure in which the information storage capacitive element C is arranged above the memory cell selection MISFETQs.

  The memory cell selection MISFET Qs includes a first gate oxide film 6, a gate electrode 8A formed integrally with the word line WL, and a source and drain (n-type semiconductor region 9). The film thickness of the first gate oxide film 6 is about 7 to 8 nm. The gate electrode 8A (word line WL) is formed by laminating a low-resistance polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)), a TiN (titanium nitride) film, and a W (tungsten) film. The sheet resistance is 2Ω / □ or less. A silicon nitride film 10 is formed on the gate electrode 8A, and a silicon nitride film 11 is formed on the side wall.

The active region of the p-type well 2 of the direct peripheral circuit is formed with n-channel type MISFET Qn _1, in the active region of the n-type well 3 p-channel type MISFET Qp ₁ is formed. That is, this direct peripheral circuit is constituted by a complementary metal oxide semiconductor (CMOS) circuit (complementary MISFET circuit) in which an n-channel MISFET Qn ₁ and a p-channel MISFET Qp ₁ are combined.

The n-channel type MISFET Qn ₁ is composed of a first gate oxide film 6, a gate electrode 8B, a source and a drain. The thickness of the first gate oxide film 6 is the same as that of the first gate oxide film 6 of the memory cell selection MISFET Qs (about 7 to 8 nm). The gate electrode 8B is made of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs, and its sheet resistance is 2Ω / □ or less. A silicon nitride film 10 is formed on the gate electrode 8B, and a side wall spacer 11a made of silicon nitride is formed on the side wall. n-channel type MISFET Qn ₁ source, each of the drain, a low impurity concentration n ^- consists of a LDD consisting -type semiconductor region 12 heavily doped ^{n +} -type semiconductor region 13. (Lightly Doped Drain) structure, A Ti silicide (TiSi ₂ ) layer 20 is formed on the surface of the n ⁺ type semiconductor region 13.

The p-channel type MISFET Qp ₁ is composed of a first gate oxide film 6, a gate electrode 8C, a source and a drain. The thickness of the first gate oxide film 6 is the same as that of the first gate oxide film 6 of the memory cell selection MISFET Qs (about 7 to 8 nm). The gate electrode 8C is made of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFETQs, and its sheet resistance is 2Ω / □ or less. A silicon nitride film 10 is formed on the gate electrode 8C, and a sidewall spacer 11a made of silicon nitride is formed on the side wall. p-channel type MISFET Qp ₁ source, each of the drain, a low impurity concentration p ^- consists of a LDD structure consisting -type semiconductor region 14 and the heavily doped ^{p +} -type semiconductor region 15., ^{p +} -type semiconductor region A Ti silicide layer 20 is formed on the surface 15.

Logic integrated circuit portion in the active region of the p-type well 2 (second region) are formed n-channel type MISFET Qn _2, in the active region of the n-type well 3 p-channel type MISFET Qp ₂ are formed. That is, the logic integrated circuit portion is constituted by a CMOS circuit in which an n-channel type MISFET Qn ₂ and a p-channel type MISFET Qp ₂ are combined.

The n-channel type MISFET Qn ₂ is composed of the second gate oxide film 7, the gate electrode 8D, the source and the drain. The film thickness of the second gate oxide film 7 is thinner than the first gate oxide film 6 in the first region and is about 4 nm. The gate electrode 8D is made of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFETQs, and its sheet resistance is 2Ω / □ or less. A silicon nitride film 10 is formed on the gate electrode 8D, and a side wall spacer 11a of silicon nitride is formed on the side wall. Each of the source and drain of the n-channel type MISFET Qn ₂ has an LDD structure composed of a low impurity concentration n ⁻ type semiconductor region 16 and a high impurity concentration n ⁺ type semiconductor region 17, and the n ⁺ type semiconductor region. A Ti silicide layer 20 is formed on the surface 17.

p-channel type MISFET Qp _2, the second gate oxide film 7, the gate electrode 8E, are constituted by source and drain. The film thickness of the second gate oxide film 7 is the same as the second gate oxide film 7 of the n-channel type MISFET Qn ₂ (about 4 nm). The gate electrode 8E is made of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFETQs, and its sheet resistance is 2Ω / □ or less. A silicon nitride film 10 is formed on the gate electrode 8E, and a side wall spacer 11a of silicon nitride is formed on the side wall. p-channel type MISFET Qp ₂ source, each of the drain, a low impurity concentration p ^- consists of a LDD structure comprising a semiconductor region 18 heavily doped ^{p +} -type semiconductor region 19., ^{p +} -type semiconductor region A Ti silicide layer 20 is formed on the surface 19.

  A DRAM indirect peripheral circuit is formed in a region (not shown) of the memory unit (first region). This indirect peripheral circuit is composed of a CMOS circuit that combines an n-channel MISFET and a p-channel MISFET.

The n-channel type MISFET of the indirect peripheral circuit has the same configuration as the n-channel type MISFET Qn ₂ of the logic integrated circuit portion. That is, the n-channel type MISFET of the indirect peripheral circuit has a gate electrode made of the same conductive film as the second gate oxide film 7 having a film thickness of about 4 nm and the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs. The source and drain of the LDD structure is composed of a low impurity concentration n ⁻ type semiconductor region and a high impurity concentration n ⁺ type semiconductor region, and a Ti silicide layer 20 is formed on the surface of the n ⁺ type semiconductor region. Has been.

P-channel type MISFET of the indirect peripheral circuit has the same structure as the p-channel type MISFET Qp ₂ of the logic integrated circuit part. That is, the p-channel type MISFET of the indirect peripheral circuit has a gate electrode made of the same conductive film as the second gate oxide film 7 having a film thickness of about 4 nm and the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs. And a source and drain of an LDD structure composed of a low impurity concentration p ⁻ type semiconductor region and a high impurity concentration p ⁺ type semiconductor region, and a Ti silicide layer 20 is formed on the surface of the p ⁺ type semiconductor region. Has been.

  Since the MISFET constituting the indirect peripheral circuit of the DRAM has the same configuration as the MISFET constituting the logic integrated circuit section as described above, the description thereof will be omitted below.

Memory cell selecting MISFETQs memory portion, each upper part of the n-channel type MISFET Qn _1, p-channel type MISFET Qp ₁ and logic integrated circuit part of the n-channel type MISFET Qn _2, p-channel type MISFET Qp _2, the silicon oxide film 22 formed Has been. The surface of the silicon oxide film 22 is flattened so that its height is substantially the same over the entire surface of the semiconductor substrate 1.

  A silicon oxide film 23 is formed on the silicon oxide film 22. Bit lines BL and first-layer wirings 24 and 25 for direct peripheral circuits are formed above the silicon oxide film 23 in the memory portion, and the logic integrated circuit first layer wirings 24 and 25 are formed above the silicon oxide film 23 in the logic integrated circuit portion. Single-layer wirings 26 and 27 are formed. These bit lines BL and first layer wirings 24 to 27 are composed of a two-layer conductive film in which a TiN film and a W film are laminated, and the sheet resistance is 2Ω / □ or less.

The bit line BL is electrically connected to one of the source and drain (n-type semiconductor region 9) of the memory cell selection MISFET Qs through the contact hole 30 in which the plug 28 is embedded. The plug 28 is made of a polycrystalline silicon film doped with an n-type impurity (for example, P). One end of the bit line BL is directly connected to _one of the source and drain (n ⁺ type semiconductor region 13) of the n-channel type MISFET Qn1 of the peripheral circuit directly through the contact hole 32.

A first layer end of the wiring 24 of the direct peripheral circuit, the source contact hole 33 n-channel type MISFET Qn ₁ through, is electrically connected to the drain of the other ^{(n +} -type semiconductor region 13), the other end, a contact hole 34 And is electrically connected to _one of the source and drain (p ⁺ -type semiconductor region 15) of the p-channel type MISFET Qp1. Direct peripheral circuit first layer wiring 25, the source contact hole 35 p-channel type MISFET Qp ₁ through, and is electrically connected to the drain of the other ^{(p +} -type semiconductor region 15).

The first layer wiring 26 of the logic integrated circuit is electrically connected to n-channel type MISFET Qn ₂ source, one drain and ^{(n +} -type semiconductor region 17) through the contact hole 36. One end of the first layer wiring 27 of the logic integrated circuit portion is electrically connected to the other of the source and drain of the n-channel type MISFET Qn ₂ (n ⁺ type semiconductor region 17) through the contact hole 37, and the other end is connected to the contact hole. It is electrically connected to the p-channel type MISFET Qp ₂ source, one drain and ^{(p +} -type semiconductor region 19) through 38.

  A silicon nitride film 40 is formed on the bit lines BL and the first layer wirings 24 to 27, and sidewall spacers 41 made of a silicon nitride film are formed on the side walls. A silicon oxide film 42 is formed further above the bit line BL and the first layer wirings 24-27.

On the upper part of the silicon oxide film 42 of the memory array (MARY), an information storage capacitive element C composed of a lower electrode (storage electrode) 43, a capacitor insulating film 44 and an upper electrode (plate electrode) 35 is formed. . The lower electrode 43 of the information storage capacitive element C is formed of a W film, and the memory cell is formed through a through hole 47 in which a plug 48 of a W (or polycrystalline silicon) film is embedded and a contact hole 31 in which a plug 28 of a polycrystalline silicon film is embedded. The selection MISFET Qs is electrically connected to the other of the source and drain (n-type semiconductor region 9). The capacitor insulating film 44 is made of a tantalum oxide (Ta ₂ O ₅ ) film, and the plate electrode 45 is made of a TiN film. A silicon nitride film 46 is formed on the plate electrode 45.

  A spin-on-glass film 51 and a silicon oxide film 52 are formed on the information storage capacitor element C. Second layer wirings 53 to 56 are formed above the silicon oxide film 52 in the memory portion, and a second layer wiring 57 is formed above the silicon oxide film 52 in the logic integrated circuit portion. These second layer wirings 53 to 57 are constituted by a three-layer conductive film in which a TiN film, an Al (aluminum) alloy film, and a TiN film are stacked.

  The second layer wiring 55 of the memory section is electrically connected to the upper electrode 45 of the information storage capacitor C through a through hole 58 in which a W film plug 61 is embedded, and a plate voltage (for example, Vdd / V) is applied to the upper electrode 45. 2) is supplied. The second layer wiring 56 of the direct peripheral circuit is electrically connected to the first layer wiring 24 through a through hole 59 in which a W film plug 61 is embedded. The second layer wiring 57 of the logic integrated circuit portion is electrically connected to the first layer wiring 27 through a through hole 60 in which a W film plug 61 is embedded.

  A silicon oxide film 62 is formed on the second layer wirings 53 to 57, and a third layer wiring 63 for a peripheral circuit and a third layer wiring 64 for a logic integrated circuit section are directly formed on the silicon oxide film 62. These third layer wirings 63 and 64 are constituted by a three-layer conductive film in which a TiN film, an Al alloy film, and a TiN film are laminated. The third layer wiring 63 of the direct peripheral circuit is electrically connected to the second layer wiring 56 through the through-hole 65 in which the W film plug 67 is embedded, and the third layer wiring 64 of the logic integrated circuit portion is connected to the W film. The second layer wiring 57 is electrically connected through the through hole 66 in which the plug 67 is embedded.

  A silicon oxide film 68 is formed on the third layer wirings 63 and 64, and a fourth layer wiring 69 for the logic integrated circuit is formed on the silicon oxide film 68. The fourth layer wiring 69 is composed of a three-layer conductive film in which a TiN film, an Al alloy film, and a TiN film are stacked. The fourth layer wiring 69 is electrically connected to the third layer wiring 64 through the through hole 70 in which the W film plug 71 is embedded.

  On the upper part of the fourth layer wiring 69, about 1 to 3 layers of wiring of the logic integrated circuit portion are formed, and further on the upper part, a two-layer insulating film in which a silicon oxide film and a silicon nitride film are laminated is formed. The passivation film thus formed is formed, but illustration thereof is omitted.

  Next, an example of a method for manufacturing the semiconductor integrated circuit device will be described with reference to FIGS.

First, as shown in FIG. 4, a p-type semiconductor substrate 1 made of single crystal silicon having a specific resistance of about 10 Ωcm is heat-treated to form a silicon oxide film 75 having a thickness of about 10 to 30 nm on the surface. A silicon nitride film 76 having a thickness of about 100 to 140 nm is deposited on the silicon oxide film 30 by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 5, by using the photoresist 77 formed on the silicon nitride film 76 as a mask, the silicon nitride film 76, the silicon oxide film 75, and the semiconductor substrate 1 in the element isolation region are sequentially etched, thereby providing a semiconductor. A groove 5a having a depth of about 350 to 400 nm is formed in the substrate 1. The gas for etching the silicon nitride film 76 uses CF ₄ + CHF ₃ + Ar or CF ₄ + Ar, and the gas for etching the semiconductor substrate 1 uses HBr + Cl ₂ + He + O ₂ .

  Next, as shown in FIG. 6, the silicon oxide film 78 deposited on the semiconductor substrate 1 by the CVD method is polished by the chemical mechanical polishing (CMP) method and left inside the trench 5a. Element isolation trenches 5 are formed. Thereafter, a heat treatment at about 1000 ° C. is performed to densify the silicon oxide film 78 embedded in the element isolation trench 5, and then silicon nitride remaining on the semiconductor substrate 1 by wet etching using hot phosphoric acid. The film 76 is removed.

Next, as shown in FIG. 7, after forming the n-type semiconductor region 4 on the semiconductor substrate 1 in the region where the DRAM memory array (MARY) and part of the peripheral circuit (n-channel type MISFET Qn ₁ ) are directly formed, A p-type well 2 is formed in the semiconductor substrate 1 in a region where the shallow portion of the n-type semiconductor region 4 and a part of the logic integrated circuit portion (n-channel type MISFET Qn ₂ ) are to be formed. An n-type well 3 is formed in the semiconductor substrate 1 in a region for forming the portion (p-channel type MISFET Qp ₁ ) and a region for forming another part (p-channel type MISFET Qp ₂ ) of the logic integrated circuit portion. The n-type semiconductor region 4 is formed by ion implantation of P (phosphorus) into the semiconductor substrate 1 and then extending and diffusing P by a heat treatment at about 1000 ° C. Further, the p-type well 2 and the n-type well 3 are ion-implanted with P in a part of the semiconductor substrate 1 and another part of B (boron) is ion-implanted, and then heat-treated at about 950 ° C. B is stretched and diffused.

  Next, after the silicon oxide film 75 remaining on the surface of the p-type well 2 and the surface of the n-type well is removed using an HF (hydrofluoric acid) -based cleaning solution, as shown in FIG. A clean gate oxide film 79 is formed on the surface of the p-type well 2 and the surface of the n-type well by a wet oxidation method.

  Next, as shown in FIG. 9, the region for forming the memory array (MARY) and the direct peripheral circuit is covered with a photoresist 80, and the gate oxidation on the surface of the p-type well 2 and the n-type well 3 in the logic integrated circuit portion is performed. The film 79 is removed using an HF cleaning solution. The boundary of the photoresist 80 is disposed on the element isolation trench 5 that separates the memory array (MARY) and the region for directly forming the peripheral circuit from the logic integrated circuit portion.

  Next, as shown in FIG. 10, wet oxidation is performed once again to form a second gate oxide film 7 having a thickness of about 4 nm on each surface of the p-type well 2 and the n-type well 3 in the logic integrated circuit portion. At this time, the gate oxide film 79 on the surfaces of the memory array (MARY) formed by the first wet oxidation and the p-type well 2 and the n-type well 3 in the region for directly forming the peripheral circuit is also grown to form the first gate. Since the oxide film 6 is formed, the thickness of the gate oxide film 79 is set in advance so that the film thickness is about 7 to 8 nm.

Next, as shown in FIG. 11, a gate electrode 8A (word line WL) is formed on the first gate oxide film 6 of the memory array (MARY), and directly on the gate oxide film 6 of the peripheral circuit and the logic integrated circuit portion. Gate electrodes 8B to 8E are formed on the second gate oxide film 7, respectively. In order to form the gate electrode 8A (word line WL) and the gate electrodes 8B to 8E, first, a polycrystalline silicon film having a thickness of about 70 nm doped with P is deposited on the semiconductor substrate 1 by the CVD method, and sputtering is performed on the polycrystalline silicon film. A TiN film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited by the method, and a silicon nitride film 10 having a thickness of about 200 nm is further deposited thereon by a CVD method. Next, the silicon nitride film 10, the W film, the TiN film, and the polycrystalline silicon film are patterned by etching using a photoresist as a mask. The gas for etching the silicon nitride film 10 uses CF ₄ + CHF ₃ + Ar or CF ₄ + Ar, and the etching gas for the W film uses Cl ₂ + SF ₆ . Further, Cl ₂ is used as a gas for etching the TiN film, and Cl ₂ + O ₂ is used as a gas for etching the polycrystalline silicon film.

Next, as shown in FIG. 12, the n-type semiconductor region 9 (source and drain) of the memory cell selection MISFET Qs is formed in the p-type well 2 of the memory array (MARY), and directly formed in the p-type well 2 of the peripheral circuit. An n ⁻ type semiconductor region 12 of the n channel type MISFET Qn ₁ is formed, and an n ⁻ type semiconductor region 16 of the n channel type MISFET Qn ₂ is formed in the p type well 2 of the logic integrated circuit portion. Further, the p ⁻ type semiconductor region 14 of the p channel type MISFET Qp ₁ is directly formed in the n type well 2 of the peripheral circuit, and the p ⁻ type semiconductor region 18 of the p channel type MISFET Qp ₂ is formed in the n type well 2 of the logic integrated circuit portion. Form. The n-type semiconductor region 9 and the n ⁻ -type semiconductor regions 12 and 16 are formed by ion implantation of P into the p-type well 2 using a photoresist covering the n-type well 3 as a mask, and the p ⁻ -type semiconductor regions 14 and 18 are formed. Is formed by ion-implanting B into the n-type well 3 using a photoresist covering the p-type well 2 as a mask.

Next, as shown in FIG. 13, after depositing a silicon nitride film 11 having a film thickness of about 10 to 50 nm on the semiconductor substrate 1 by the CVD method, the memory array (MARY) is formed into a photoresist 81 as shown in FIG. Then, the silicon nitride film 11 in the peripheral circuit and logic integrated circuit portion is directly anisotropically etched to form side wall spacers 11a on the side walls of the gate electrodes 8B to 8E. At this time, the boundary of the photoresist 81 is disposed on the element isolation trench 5 that separates the memory array (MARY) and the peripheral circuit directly. This etching minimizes the amount of overetching and minimizes the amount of etching between the silicon oxide film embedded in the element isolation trench 5 and the silicon nitride film 10 on the gate electrodes 8B to 8E. An etching gas (for example, CH ₂ F ₂ , CH ₃ F, or Cl ₂ + O ₂ ) that can have a large selectivity with respect to the silicon film is used.

Next, as shown in FIG. 15, the ^{n +} -type semiconductor region 13 of the n-channel type MISFET Qn ₁ is formed on the p-type well 2 of the peripheral circuits directly, the n-type well 2 of the p-channel type MISFET Qp ₁ ^{p +} -type semiconductor Region 15 is formed. Further, the ^{n +} -type semiconductor region 17 of the n-channel type MISFET Qn ₂ is formed on the p-type well 2 of the logic integrated circuit part, to form a ^{p +} -type semiconductor region 19 of the p-channel type MISFET Qp ₂ to n-type well 2. The n ⁺ type semiconductor regions 13 and 17 are formed by ion implantation of As (arsenic) into the p type well 2 and the p ⁺ type semiconductor regions 15 and 19 are formed by ion implantation of B into the n type well 3. To do.

Next, as shown in FIG. 16, a Ti film 82 having a thickness of about 40 nm is deposited on the semiconductor substrate 1 by a sputtering method, and then heat treatment is performed in a nitrogen atmosphere at 600 to 700 ° C. As shown in FIG. 17, since the memory array (MARY) is covered with the silicon nitride film 11, no silicidation reaction occurs in this region, whereas in the direct peripheral circuit and logic integrated circuit portion, the semiconductor substrate 1 A silicidation reaction occurs in the exposed portions (n ⁺ type semiconductor regions 13 and 17 and p ⁺ type semiconductor regions 15 and 19), and a Ti silicide and de (TiSi ₂ ) layer 20 is formed on the surface thereof. .

  Next, after removing the unreacted Ti film 82 by wet etching, as shown in FIG. 18, a silicon oxide film 22 is deposited on the semiconductor substrate 1 by a CVD method, and then oxidized by using a chemical mechanical polishing method. The surface of the silicon film 22 is planarized.

  Next, as shown in FIG. 19, the silicon oxide film 22 on the n-type semiconductor region (source, drain) of the memory cell selection MISFET Qs is removed by etching using the photoresist 84 as a mask. This etching is performed under the condition that the etching rate of the silicon oxide film 22 with respect to the silicon nitride films 10 and 11 is increased so that the silicon nitride film 11 on the upper portion of the n-type semiconductor region 9 is not removed.

  Next, as shown in FIG. 20, the silicon nitride film 11 and the second gate oxide film 7 above the n-type semiconductor region 9 (source and drain) of the memory cell selection MISFET Qs are etched by using the photoresist 84 as a mask. As a result, the contact hole 30 is formed above one of the source and drain (n-type semiconductor region 9), and the contact hole 31 is formed above the other (n-type semiconductor region 9). In this etching, in order to minimize the amount of chipping of the semiconductor substrate 1, an etching gas that can minimize the overetching amount and can have a large selection ratio with respect to silicon is used. This etching is performed under the condition that the silicon nitride film 10 is anisotropically etched, and the silicon nitride film 11 is left on the sidewall of the gate electrode 8A (word line WL). In this way, the contact holes 30 and 31 are formed in self-alignment with the silicon nitride film 11 on the side wall of the gate electrode 8A (word line WL). In order to form the contact holes 30 and 31 in a self-aligned manner with respect to the silicon nitride film 10, the silicon nitride film 11 is anisotropically etched in advance to form a side wall spacer on the side wall of the gate electrode 8A (word line WL). You may keep it.

  Next, as shown in FIG. 21, after plugs 28 are embedded in the contact holes 30 and 31, a Ti silicide layer 29 is formed on the surfaces of the plugs 28. The plug 28 is formed by depositing a polycrystalline silicon film doped with P on the silicon oxide film 22 by a CVD method, and then polishing the polycrystalline silicon film by a chemical mechanical polishing method to form the inside of the contact holes 30 and 31. It is formed by leaving. P in the polycrystalline silicon film constituting the plug 28 diffuses from the bottom of the contact holes 30 and 31 into the n-type semiconductor region 9 (source and drain) in a later high-temperature process, thereby reducing the resistance of the n-type semiconductor region 9. To do. The Ti silicide layer 29 is formed by heat-treating a Ti film deposited on the silicon oxide film 22 by sputtering in a nitrogen atmosphere at 600 to 700 ° C., and then removing the unreacted Ti film by wet etching. .

  Next, as shown in FIG. 22, after the silicon oxide film 23 is deposited on the silicon oxide film 22 by the CVD method, the silicon oxide film 23 on the contact hole 30 is removed by etching using the photoresist 85 as a mask. To do.

Next, as shown in FIG. 23, the silicon oxide films 23 and 22 and the first gate oxide film 6 (second gate oxide film 7) in the peripheral circuit and logic integrated circuit sections are directly etched by using the photoresist 86 as a mask. by removing, n-channel type MISFET Qn ₁ of the ^{n +} -type semiconductor region 13, p-channel type MISFET Qp ₁ of ^{p +} -type semiconductor region 15, ^{n +} -type n-channel type MISFET Qn ₂ of the logic integrated circuit part of the direct peripheral circuit Contact holes 32 to 38 are formed on the semiconductor region 17 and the p ⁺ type semiconductor region 19 of the p-channel type MISFET Qp ₂ . This etching is performed under the condition that the etching rate of the silicon oxide film with respect to the silicon nitride film 10 and the sidewall spacer 11a is increased, and the contact holes 32 to 38 are formed in a self-alignment with the sidewall spacer 11a.

  Next, as shown in FIG. 24, a bit line BL is formed on the silicon oxide film 23 of the memory array (MARY), and a first layer wiring is formed directly on the silicon oxide film 23 of the peripheral circuit and logic integrated circuit portion. 24-27 are formed. For the bit lines BL and the first layer wirings 24 to 27, a TiN film and a W film are deposited on the silicon oxide film 23 by a sputtering method, and then a silicon nitride film 40 is deposited on the W film by a CVD method. These films are patterned by etching using a photoresist as a mask.

  Next, as shown in FIG. 25, sidewall spacers 41 are formed on the side walls of the bit lines BL and the first layer wirings 24 to 27, and then the upper portions of the bit lines BL and the first layer wirings 24 to 27 are formed by CVD. After the silicon oxide film 42 is deposited, the through holes 47 are formed by removing the silicon oxide films 42 and 23 above the contact holes 31 by etching using a photoresist as a mask. The sidewall spacer 41 is formed by processing a silicon nitride film deposited by the CVD method on the bit line BL and the first layer wirings 24 to 27 by anisotropic etching. Etching for forming the through hole 47 is performed under the condition that the etching rate of the silicon oxide film with respect to the silicon nitride film 40 and the sidewall spacer 41 is increased, and the through hole 47 is self-aligned with the sidewall spacer 41. Form.

  Next, as shown in FIG. 26, after a W film plug 48 is embedded in the through hole 47, a lower electrode (storage electrode) 43 of the information storage capacitor element is formed thereon. The plug 48 is formed by depositing a W film on the silicon oxide film 42 by a CVD method or a sputtering method, and then polishing this W film by a chemical mechanical polishing method and leaving it inside the through hole 47. Similarly, the lower electrode 43 is formed by depositing a W film on the silicon oxide film 42 by CVD or sputtering, and patterning the W film by etching using a photoresist as a mask.

  Next, as shown in FIG. 27, a capacitive insulating film 44 and an upper electrode (plate electrode) 45 of the information storage capacitive element C are formed on the lower electrode (storage electrode) 43. The capacitor insulating film 44 and the upper electrode 45 are formed by depositing a tantalum oxide film on the upper portion of the silicon oxide film 42 by a CVD method or a sputtering method, depositing a TiN film on the upper portion thereof by a sputtering method, and further nitriding the upper portion thereof by a CVD method. After the silicon film 46 is deposited, these films are patterned by etching using a photoresist as a mask.

  Next, as shown in FIG. 28, a spin-on glass film 51 is formed on the information storage capacitor C by spin coating, and then a silicon oxide film 52 is deposited on the spin-on glass film 51 by CVD. Then, the silicon oxide film 52, the spin-on-glass film 51, and the silicon nitride film 46 are etched using the photoresist as a mask to form a through hole 58 on the upper electrode 45 of the information storage capacitor C. At this time, the silicon oxide film 52, the spin-on-glass film 51, the silicon oxide film 42, and the silicon nitride film 40 in the peripheral circuit and the logic integrated circuit portion are simultaneously etched, so that the first peripheral wiring 24 is directly formed on the upper part of the peripheral circuit. A through hole 59 is formed, and a through hole 60 is formed above the first layer wiring 27 of the logic integrated circuit portion.

  Next, as shown in FIG. 29, the W film plug 61 is buried in the through holes 59 to 60, and then second layer wirings 53 to 57 are formed on the silicon oxide film 52. The second layer wiring 55 of the memory array (MARY) is electrically connected to the upper electrode 45 of the information storage capacitive element C through the through hole 58, and the second layer wiring 56 of the peripheral circuit directly is connected to the first electrode through the through hole 59. The second layer wiring 57 of the logic integrated circuit portion is electrically connected to the first layer wiring 27 through the through hole 60 and is electrically connected to the first layer wiring 24. The second layer wirings 53 to 57 are formed by depositing a TiN film, an Al alloy film, and a TiN film on the silicon oxide film 52 by sputtering and then patterning these films by etching using a photoresist as a mask. .

  Next, as shown in FIG. 30, a silicon oxide film 62 is deposited on the second layer wirings 53 to 57, and third layer wirings 63 and 64 are formed on the silicon oxide film 62. In order to form the third layer wirings 63 and 64, first, a silicon oxide film 62 is deposited on the second layer wirings 53 to 57 by the CVD method, and then the silicon oxide film 62 is etched using the photoresist as a mask. Thus, a through hole 65 is directly formed on the second layer wiring 56 of the peripheral circuit, and a through hole 66 is formed on the second layer wiring 57 of the logic integrated circuit portion. Subsequently, a W film plug 67 is embedded in the through holes 65 and 66, and then a TiN film, an Al alloy film, and a TiN film are deposited on the silicon oxide film 62 by a sputtering method, and a photoresist is used as a mask. These films are patterned by etching. The third layer wiring 63 of the direct peripheral circuit is electrically connected to the second layer wiring 56 through the through hole 65, and the third layer wiring 64 of the logic integrated circuit portion is electrically connected to the second layer wiring 57 through the through hole 66. Connected.

  Thereafter, a silicon oxide film 68 is deposited on the third layer wiring 64 in the logic integrated circuit portion, and a fourth layer wiring 69 is formed on the silicon oxide film 68, thereby substantially completing the semiconductor integrated circuit device shown in FIG. To do. In order to form the fourth layer wiring 69, first, a silicon oxide film 68 is deposited on the third layer wirings 56 and 57 by a CVD method, and then the silicon oxide film 68 is etched using a photoresist as a mask. A through hole 70 is formed above the third layer wiring 64 in the logic integrated circuit portion. Subsequently, after plugging a W film plug 71 into the through hole 70, a TiN film, an Al alloy film, and a TiN film are deposited on the upper portion of the silicon oxide film 70 by sputtering, and etching using a photoresist as a mask is performed. These films are patterned. The fourth layer wiring 69 is electrically connected to the third layer wiring 64 through the through hole 70.

According to the semiconductor integrated circuit device of the present embodiment configured as described above, the following effects can be obtained.
(1) The gate oxide film thickness of the MISFET constituting the logic integrated circuit portion is formed thin, the gate electrode is composed of a conductive material having a sheet resistance of 2Ω / □ or less, and the source and drain are silicided. As a result, high-speed operation of the logic integrated circuit can be realized.
(2) Since the source and drain of the memory cell selection MISFET constituting the DRAM memory cell are not silicided, an increase in leakage current due to the silicidation can be prevented and deterioration of the refresh characteristics can be avoided.
(3) By configuring the gate electrode of the memory cell selecting MISFET constituting the DRAM memory cell with a conductive material having a sheet resistance of 2Ω / □ or less, the gate delay can be reduced. Further, since the backing of the word line by the metal wiring becomes unnecessary, the manufacturing process of the DRAM is simplified and the manufacturing yield is improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiments, the DRAM sense amplifier, row decoder, and column decoder are defined as direct peripheral circuits. For example, the sense amplifier, row decoder, column decoder, logic circuit, address selection circuit, read amplifier, and write amplifier are directly peripheral. It may be defined as a circuit, and the input / output circuit may be defined as an indirect peripheral circuit.

  In the above embodiment, the surface of the source and drain of the MISFET constituting the direct peripheral circuit of the DRAM, the surface of the source and drain of the MISFET constituting the indirect peripheral circuit, and the source and drain of the MISFET constituting the logic integrated circuit. A silicide layer is formed on the surface, and no silicide layer is formed on the surface of the source and drain of the memory cell selection MISFET constituting the memory cell of the DRAM. For example, the MISFET constituting the indirect peripheral circuit of the DRAM is not formed. Silicide layers are formed on the surface of the source and drain and the surface of the source and drain of the MISFET constituting the logic integrated circuit, and the surface of the source and drain of the memory cell selecting MISFET constituting the memory cell of the DRAM, and the DRAM The source and drain of the MISFET that directly constitutes the peripheral circuit To the in-the surface may not form a silicide layer. In this case, since the manufacturing process of the peripheral circuit and the DRAM memory array can be made common, it is possible to distribute the DRAM memory array and the direct peripheral circuit independently as a DRAM core. Also, it becomes possible to distribute the logic integrated circuit portion having the source and drain silicided alone as a logic core.

  In the above embodiment, Ti is used as the silicide material, but other metal materials such as Co (cobalt) may be used.

  The present invention is suitable for application to a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted.

1 is an overall configuration diagram of a semiconductor chip showing a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a configuration diagram of a DRAM memory array and a direct peripheral circuit constituting a memory unit of a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a part of a memory part and a logic integrated circuit part of a semiconductor integrated circuit device according to an embodiment of the present invention; It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is embodiment of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 4. FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 5. FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 7. FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 8. FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 11. FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 15; FIG. 17 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 18; FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device following FIG. 19; FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 20; FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 21. FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 22; FIG. 24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 23. FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 24. FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 25. FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 26. FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 27; FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 28. FIG. 30 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor integrated circuit device following FIG. 29;

Explanation of symbols

1 semiconductor substrate 2 p-type well 3 n-type well 4 n-type semiconductor region 5 element isolation trench 6 first gate oxide film 7 second gate oxide film 8A, 8B, 8C, 8D gate electrode 9 n-type semiconductor region (source, drain) )
10, 11 Silicon nitride film 11a Side wall spacer 12 n ⁻ type semiconductor region 13 n ⁺ type semiconductor region 14 p ⁻ type semiconductor region 15 p ⁺ type semiconductor region 16 n ⁻ type semiconductor region 17 n ⁺ type semiconductor region 18 p ⁻ type Semiconductor region 19 p ⁺ type semiconductor region 20 Ti silicide layers 22 and 23 Silicon oxide films 24 to 27 First layer wiring 28 Plug 29 Ti silicide layers 30 to 38 Contact hole 40 Silicon nitride film 41 Side wall spacer 42 Silicon oxide film 43 Lower part Electrode (storage electrode)
44 Capacitive insulating film 45 Upper electrode (plate electrode)
46 Silicon nitride film 47 Through hole 48 Plug 51 Spin-on glass film 52 Silicon oxide film 53 to 57 Second layer wiring 58, 59, 60 Through hole 61 Plug 62 Silicon oxide film 63, 64 Third layer wiring 65, 66 Through hole 67 Plug 68 Silicon oxide film 69 Fourth layer wiring 70 Through hole 71 Plug C Information storage capacitor BL Bit line MARY Memory array
Qn ₁ , Qn ₂ n-channel MISFET
Qp ₁ , Qp ₂ p channel type MISFET
Qs MISFET for memory cell selection
WL Word line

Claims (6)

In a method of manufacturing a semiconductor integrated circuit device having a storage capacitor constituting a memory, a first MISFET to which the storage capacitor is connected, and a second MISFET constituting a peripheral circuit of the memory,
(A) forming the first MISFET having a gate electrode, a source and a drain region in a first region of the main surface of the semiconductor substrate, and forming a gate electrode in a second region different from the first region of the main surface of the semiconductor substrate; Forming the second MISFET having source and drain regions;
(B) forming a first insulating film in the first region and the second region of the main surface of the semiconductor substrate so as to cover the first MISFET and the second MISFET;
(C) After forming a mask that selectively covers the first region, the first insulating film in the second region is etched by anisotropic first etching, and the first region Forming a first sidewall spacer formed of a part of the first insulating film on a side wall of the gate electrode of the 2MISFET, and removing the first insulating film in the other part; and in the first region, Leaving the first insulating film;
(D) after the step (c), removing the mask and forming a first metal film on the first insulating film in the first region and the second MISFET in the second region;
(E) after the step (d), by annealing the semiconductor substrate, forming a metal silicide film by the first metal film on the surface of the source and drain regions of the second MISFET;
(F) After the step (e), removing the unreacted first metal film that is not silicided by the annealing;
(G) after the step (f) , forming a second insulating film in the first region and the second region of the main surface of the semiconductor substrate so as to cover the first MISFET and the second MISFET;
(H) After the step (g), the second insulating film on the source and drain regions of the first MISFET is selectively and second etched by the second etching using the first insulating film as an etching stopper. Removing in a self-aligned manner with respect to the gate electrode of the first MISFET;
(I) After the step (h), by selectively removing the first insulating film on the source and drain regions of the first MISFET by an anisotropic third etching, the first MISFET Forming a first through hole exposing a surface of the source and drain regions, and forming a second sidewall spacer formed of a part of the first insulating film on a sidewall of the gate electrode of the first MISFET; When,
(J) after the step (i), forming a first electrode connected to the source and drain regions of the first MISFET through the first through hole;
A method for manufacturing a semiconductor integrated circuit device, comprising:   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is a silicon nitride film.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second insulating film is a silicon oxide film. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising:
(K) After the step (j), the second insulating film on the source and drain regions of the second MISFET is selectively removed by a fourth etching, and the surfaces of the source and drain regions of the second MISFET Forming a second through hole exposing the metal silicide layer formed in
(L) After the step (k), a second electrode that is electrically connected to the source and drain regions of the second MISFET through the second through hole is formed , and the first electrode is electrically connected to the first electrode. Forming a third electrode to be electrically connected ;
The method of manufacturing a semiconductor integrated circuit device according to claim containing Mukoto a. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, further comprising:
(M) after the step (l), forming an information storage capacitive element electrically connected to the third electrode;
A method for manufacturing a semiconductor integrated circuit device, comprising: In the manufacturing method of the semiconductor integrated circuit device according to claim 5 ,
The information storage capacitor element includes a lower capacitor electrode made of a metal film and an upper capacitor electrode made of a metal film .

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