JP4821083B2 - Electro-optical device and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device and an electronic apparatus.
[0002]
[Prior art]
Conventionally, as one of liquid crystal display devices as an electro-optical device, there is an active matrix liquid crystal display device in which each pixel includes a pixel transistor formed of a thin film transistor (hereinafter referred to as “TFT”).
[0003]
In this type of active matrix liquid crystal display device, when the pixel transistor is turned off, the voltage level of the image signal supplied to the liquid crystal capacitor element is shifted to the negative electrode side due to the parasitic capacitance of the gate of the pixel transistor. A field-through voltage is generated. As a result, flicker and afterimage occur. In order to suppress the occurrence of this field through voltage, a method is known in which a capacitance component between the pixel electrode and the preceding or subsequent scanning line is formed and added to the liquid crystal capacitance.
[0004]
In this type of active matrix liquid crystal display device, the polarity of the counter electrode voltage is inverted every predetermined period, for example, every scanning line by supplying a polarity signal to the counter electrode, so-called There is a liquid crystal display device that is driven by adopting a common inversion method. By adopting the common inversion method and driving the liquid crystal display device, the burning of the liquid crystal capacitor can be suppressed.
[0005]
In the liquid crystal display device in which the capacitance component of the pixel electrode and the preceding or succeeding scanning line is formed and added to the liquid crystal capacitor and driven by the common inversion method, the pixel of the scanning line that is not selected is added. In contrast, an AC signal synchronized with the common is supplied. At this time, if the AC signal synchronized with the common is not supplied with good timing, the display quality is deteriorated.
[0006]
Therefore, in order to prevent this, a logic gate and a switch element that is controlled to be turned on / off according to a control signal output from the logic gate are provided for each scanning line, and output to the scanning line and the next scanning line. A device that controls an on / off state of a switch element based on a scanning signal is known (for example, Patent Document 1).
[0007]
[Patent Document 1]
Japanese Utility Model Publication No. 7-33075
[0008]
[Problems to be solved by the invention]
However, in the liquid crystal display device of Patent Document 1, the scanning line is in a high impedance state until the image signal is written again in the next frame period, and the scanning line is connected to the scanning line by capacitive coupling with the common electrode. The AC signal is supplied. At this time, the scanning line is in a high impedance state and not an ideal insulating state. Therefore, the potential of the scanning line may fluctuate unexpectedly due to the inflow and outflow of charges due to the leak path. Therefore, if the non-selection period continues for a long time, the potential of the scanning line may transition to an unintended potential. As a result, there is a concern that the OFF state of the switch element cannot be maintained, and the gray level of the pixel cannot be accurately controlled according to the image signal, and the display quality is deteriorated.
[0009]
Accordingly, the present invention has been made in view of such conventional problems, and an object thereof is an electro-optical device and an electronic apparatus that can improve display quality by accurately controlling according to an image signal. Is to provide.
[0010]
[Means for Solving the Problems]
  The electro-optical device according to the aspect of the invention is provided with a plurality of scanning lines, a plurality of signal lines, a switching element provided corresponding to an intersection of the scanning line and the signal line, and a switching element corresponding to the switching element. An electro-optical device comprising: a pixel electrode; and a scanning line driving circuit that sequentially supplies a scanning signal for controlling on / off of the switching element to the scanning line.Arranged between the scanning line driving circuit and the scanning line;
  From the time when the scanning signal is supplied to the preceding scanning line to the time when the scanning signal is supplied to the subsequent scanning line, the scanning line driving circuit and the scanning line driving circuit are electrically connected, A scanning signal supplied to the scanning line is output to the scanning line;
  The latter stageAfter the scanning signal is supplied to the scanning line,In the previous scanning lineUntil the scanning signal is suppliedElectrically disconnecting the scanning line and the scanning line driving circuit of the self-stage,The scanning signal is not suppliedOwn stageA scanning line control circuit is provided for switching the scanning line state between a high impedance state and a state where a predetermined potential is supplied.
[0011]
  According to this, the scanning line control circuitAfter the scanning signal is supplied to the subsequent scanning line, until the scanning signal is supplied to the preceding scanning line, the scanning line output circuit and the scanning line of the own stage are cut off and disconnected, The state of the scanning line at the stage where the scanning signal is not supplied is switched between a high impedance state and a state where a predetermined potential is supplied.Therefore, even in a non-selection period that is not selected for a long period, the scanning line is intermittently set to a predetermined voltage, so that the potential of the scanning line is prevented from transitioning to an unintended potential. be able to. As a result, an electro-optical device having a high-quality display quality can be provided.
[0012]
In this electro-optical device, the selection permission circuit may be configured by an SR flip-flop circuit.
[0013]
In this electro-optical device, the potential of the scanning line may be set to the predetermined potential when the potential of the second electrode is L level.
According to this, in the electro-optical device used as a so-called common electrode in which the second electrode is connected in common with the second electrode of the electro-optical element provided in another pixel, the potential of the common electrode Is at the L level, the scanning line potential is set to the predetermined potential.
[0014]
In this electro-optical device, the potential of the scanning line may be set to the predetermined potential when the potential of the common electrode is H level.
According to this, in the electro-optical device used as a so-called common electrode in which the second electrode is connected in common with the second electrode of the electro-optical element provided in another pixel, the potential of the common electrode When is at H level, the potential of the scanning line is set to the predetermined potential.
[0015]
In the electro-optical device, each of the selection permission circuits includes a first output terminal that outputs a first output signal and a second output terminal that outputs a second output signal. The output terminal and the second output terminal that outputs the second output signal may be interchanged.
[0016]
According to this, it becomes a circuit which can respond also to reversal of a scanning line direction by controlling a changeover switch.
[0017]
In the electro-optical device, the display element may be a liquid crystal capacitive element.
According to this, in a liquid crystal display device provided with a liquid crystal capacitance element, even if it is a non-selection period that is not selected for a long period, the potential of the scanning line is prevented from transitioning to an unintended potential. Thus, a liquid crystal display device having a high-quality display quality can be realized.
[0018]
The electronic apparatus of the present invention includes the electro-optical device.
According to this, an electronic apparatus including an electro-optical device that can suppress the potential of the scanning line from transitioning to an unintended potential even in a non-selected period that is not selected for a long period of time. Can be realized. As a result, it is possible to provide an electronic apparatus equipped with a high-quality display-quality electro-optical device.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments in which the present invention is applied to a liquid crystal display device will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block circuit diagram showing an electrical configuration of the liquid crystal display device. FIG. 2 is a diagram illustrating an electrical configuration of the display panel unit and the scanning line control circuit. FIG. 3 is an equivalent circuit diagram of the pixel. FIG. 4 is an equivalent circuit diagram of the selection permission circuit.
[0020]
As shown in FIG. 1, the liquid crystal display device 10 includes a signal control circuit 11, a display panel unit 12, a scanning line driving circuit 13, a scanning line control circuit 14a, and a signal line driving circuit 15. The signal control circuit 11, the scanning line driving circuit 13, the scanning line control circuit 14a, and the signal line driving circuit 15 of the liquid crystal display device 10 may be configured by independent electronic components. For example, the signal control circuit 11, the scanning line driving circuit 13, the scanning line control circuit 14a, and the signal line driving circuit 15 may each be configured by a one-chip semiconductor integrated circuit device. In addition, the signal control circuit 11, the scanning line driving circuit 13, the scanning line control circuit 14a, and the signal line driving circuit 15 are all or partly configured by a programmable IC chip, and the function is software by a program written in the IC chip. May be realized. The liquid crystal display device 10 according to the present invention is an active matrix type liquid crystal display device, and is a common inversion type liquid crystal display device in which the polarity of the counter electrode is inverted every horizontal period.
[0021]
The signal control circuit 11 inputs a clock pulse CP and image data D supplied from an external device (not shown). The signal control circuit 11 selects the first to nth scanning control lines YS1 to YSn and the first and second dummy scanning control lines YSD1 and YSD2 (see FIG. 2) on the basis of the clock pulse CP. A horizontal synchronizing signal HSYNC for determining The signal control circuit 11 also performs vertical synchronization for determining the timing of outputting the image signals D1, D2,..., Dm to the corresponding signal lines X1, X2,..., Xm (see FIG. 2) based on the clock pulse CP. The signal VSYNC is created. The signal control circuit 11 outputs the horizontal synchronization signal HSYNC to the scanning line driving circuit 13 and outputs the vertical synchronization signal VSYNC to the signal line driving circuit 15. Further, the signal control circuit 11 outputs the image data D to the signal line driving circuit 15.
[0022]
As shown in FIG. 2, the display panel unit 12 includes n scanning lines Y1, Y2,..., Yn extending along the row direction. The display panel unit 12 includes m signal lines X1, X2,..., Xm extending along the column direction. In the present embodiment, the scanning lines Y1, Y2,..., Yn are the first scanning line Y1, the second scanning line Y2,. .. Are provided in order of the nth scanning line Yn. The display panel unit 12 includes a first dummy scanning line YD1 on the upper side (previous stage) of the first scanning line Y1 among the scanning lines Y1, Y2,. Further, the display panel unit 12 includes a second dummy scanning line YD2 on the lower side (rear stage) of the nth scanning line Yn among the scanning lines Y1, Y2,. Pixels 20 are formed at positions corresponding to the intersections of the scanning lines Y1, Y2,..., Yn and the signal lines X1, X2,.
[0023]
Each pixel 20 is connected to the scanning line control circuit 14a via the scanning lines Y1, Y2,. Each pixel 20 is connected to the signal line drive circuit 15 via signal lines X1, X2,..., Xm. Further, the first and second dummy scanning lines YD 1 and YD 2 are not connected to the pixel 20. (If necessary, a configuration may be adopted in which dummy pixels are provided and connected.)
As shown in FIG. 3, each of the pixels 20 is a pixel transistor Qg, a liquid crystal capacitive element 21, and a capacitive element connected in parallel to the liquid crystal capacitive element 21 to reduce leakage of the liquid crystal capacitive element 21. A certain auxiliary capacitance element 22 is provided. FIG. 3 is an equivalent circuit diagram of the pixel 20 formed at a position corresponding to the intersection of the first scanning line Y1 and the first signal line X1. Since all of the electrical configurations of the pixels 20 are the same, only the pixels formed at positions corresponding to the intersections of the first scanning lines Y1 and the first signal lines X1 will be described below for convenience of explanation. .
[0024]
The pixel transistor Qg is a transistor that functions as a switching element. Further, the pixel transistor Qg is usually constituted by a TFT (Thin Film Transistor). In this embodiment, the pixel transistor Qg has an n-type conductivity.
[0025]
The gate of the pixel transistor Qg is connected to the first scanning line Y1. The drain of the pixel transistor Qg is connected to the first signal line X1. The source of the pixel transistor Qg is connected to the pixel electrode E1 of the liquid crystal capacitor 21. A counter electrode E2 is formed through a liquid crystal at a position facing the pixel electrode E1. The source of the pixel transistor Qg is connected to the first electrode P1 of the auxiliary capacitance element 22. The second electrode P2 of the auxiliary capacitance element 22 is connected to the common line LG together with the counter electrode E2. The common line LG is connected in common to the counter electrode E2 of the liquid crystal capacitive element 21 and the second electrode P2 of the auxiliary capacitive element 22 constituting the other pixel 20. That is, the liquid crystal display device 10 of the present embodiment is used as a so-called common electrode in which the counter electrode E2 is connected in common with the counter electrode E2 of the liquid crystal capacitive element 21 provided in another pixel. .
[0026]
As shown in FIG. 2, the scanning line driving circuit 13 is connected to the first to nth scanning control lines YS1, YS2,..., YSn, the first and second dummy scanning control lines YSD1, YSD2, The first to nth scanning control lines YS1, YS2,..., YSn, and the first and second dummy scanning control lines YSD1 and YSD2 are connected to the next scanning line control circuit 14a. The scanning line driving circuit 13 creates the first dummy scanning control signal SRD1, and outputs the created first dummy scanning control signal SRD1 to the first dummy scanning control line YSD1.
[0027]
Further, the scanning line driving circuit 13 creates the second dummy scanning control signal SRD2, and outputs the created second dummy scanning control signal SRD2 to the second dummy scanning control line YSD2. Further, the scanning line driving circuit 13 generates the first to nth scanning control signals SR1, SR2,..., SRn, and the generated first to nth scanning control signals SR1, SR2,. Output to the corresponding first to nth scanning control lines YS1, YS2,.
[0028]
Then, the scanning line driving circuit 13 supplies the first to nth scanning control lines YS1, YS2,..., YSn, and the first and second dummy scanning control lines YSD1, YSD2, respectively, based on the horizontal synchronization signal HSYNC. YSD1.fwdarw.YS1.fwdarw.YS2.fwdarw..fwdarw.YSn.fwdarw.YSD2.fwdarw.YSD1 are selected in this order, and the corresponding scanning control signals SRD1, SR1, SR2,..., SRn, SRD2 are output as shown in FIG.
[0029]
The scanning line control circuit 14 a is disposed between the display panel unit 12 and the scanning line driving circuit 13. The scanning line control circuit 14a is connected to the scanning lines Y1, Y2,..., Yn, and the first and second dummy scanning lines YD1 and YD2. The scanning line control circuit 14a includes first to nth scanning control lines YS1, YS2,..., YSn, and first and second dummy scanning control lines YSD1, YSD2 provided in the preceding scanning line driving circuit 13. It is connected to the. The scanning line control circuit 14a outputs the first to nth scanning control signals SR1, SR2,..., SRn, the first dummy scanning control signal SRD1, and the second dummy scanning control signal output from the scanning line driving circuit 13. Based on the SRD2, the first scanning line Y1 to the nth scanning line Yn, the first dummy scanning line YD1, and the second dummy scanning line YD2 are selectively driven.
[0030]
More specifically, as shown in FIG. 2, the scanning line control circuit 14a includes first to nth switch elements SW1, SW2,..., SWn (n is a natural number), a first transistor Tr1, and a second transistor Tr2. , A selection permission circuit Fa, a polarity signal line LP, and a charging power supply line LC.
[0031]
The first to nth switch elements SW1, SW2,..., SWn are arranged between the first to nth scan control lines YS1, YS2, ..., YSn and the corresponding scan lines Y1, Y2,. Is provided. Each of the first to nth switch elements SW1, SW2,..., SWn is turned on / off based on the first output signal Q1 and the second output signal Q2 (see FIG. 5) output from the selection permission circuit Fa. Be controlled.
[0032]
Each of the first to n-th switch elements SW1, SW2,..., SWn is supplied with the H-level first output signal Q1 from the selection permission circuit Fa and the L-level second output signal Q2. If turned on. As a result, the scanning control line connected to the switch element turned on and the scanning line are electrically connected.
[0033]
Also, the first to nth switch elements SW1, SW2,..., SWn are turned off when an output signal other than the H level first output signal Q1 and the L level second output signal Q2 is input. It becomes a state. Then, the scanning control line connected to the switch element that has been turned off and the scanning line are electrically disconnected.
[0034]
The first transistor Tr1 and the second transistor Tr2 form a pair, and are formed corresponding to each of the first to nth switch elements SW1, SW2,. Each of the first and second transistors Tr1 and Tr2 is an n-type transistor in this embodiment. The gate of the first transistor Tr1 is connected to the corresponding first to nth switch elements SW1, SW2,..., SWn so that the second output signal Q2 output from the selection permission circuit Fa is input. It has become. The source of the first transistor Tr1 is connected to the corresponding scanning line. The drain of the first transistor Tr1 is connected to the source of the second transistor Tr2. The drain of the second transistor Tr2 is connected to the charging power supply line LC. The gate of the second transistor Tr2 is connected to the polarity signal line LP.
[0035]
The selection permission circuit Fa is formed corresponding to each of the first to nth switch elements SW1, SW2,. Since the circuit configuration of the selection permission circuit Fa is the same, the first one connected to the first scanning control line YS1 among the first to nth scanning control lines YS1, YS2,. Only the selection permission circuit Fa formed corresponding to the switch element SW1 will be described, and the detailed description of the other selection permission circuits Fa will be omitted.
[0036]
FIG. 4 is an equivalent circuit of the selection permission circuit Fa formed corresponding to the first switch element SW1. As shown in FIG. 4, the selection permission circuit Fa is a so-called SR flip-flop circuit in which first and second NOR circuits 25a and 25b each having two input terminals are electrically connected to each other. One input terminal of the first NOR circuit 25a is connected to the first dummy scanning control line YSD1, and the first dummy scanning control signal SRD1 is input thereto. One input terminal of the second NOR circuit 25b is connected to the second scanning control line YS2, and receives the second scanning control signal SR2. That is, the selection permission circuit Fa is connected to the first dummy scanning control line YSD1 provided in the preceding stage and the second scanning control line YS2 provided in the subsequent stage from the first scanning control line YS1 in the own stage. The first dummy scanning control signal SRD1 and the second scanning control signal SR2 are input.
[0037]
The selection permission circuit Fa is when the second scanning control line YS2 is not selected (the second scanning control signal SR2 is at L level) and when the first dummy scanning control line YSD1 is selected (first dummy scanning). When the control signal SRD1 becomes H level), a so-called set state is set. In the set state, as shown in FIG. 5, the selection permission circuit Fa outputs a first output signal Q1 at H level and a second output signal Q2 at L level.
[0038]
Further, the selection permission circuit Fa is when the first dummy scanning control line YSD1 is not selected (the first dummy scanning control signal SRD1 is at L level) and when the second scanning control line YS2 is selected (second). Is in the so-called reset state. In the reset state, the selection permission circuit Fa outputs an L level first output signal Q1 and an H level second output signal Q2, as shown in FIG. That is, the selection permission circuit Fa is set when the preceding scanning control line is selected, and is reset when the succeeding scanning control line is selected.
[0039]
As a result, the selection permission circuit Fa switches the scanning control line and the scanning line belonging to the selection permission circuit Fa from the time when the preceding scanning control line is selected until the succeeding scanning line is selected. Electrical connection through That is, when the selection permission circuit Fa is in the set state, the selection permission circuit Fa permits the scanning control signal output from the scanning line driving circuit 13 to be output as a scanning signal to the scanning line. Further, when the selection permission circuit Fa is in the set state, the first transistor Tr1 of the pair of first and second transistors Tr1 and Tr2 belonging to the selection permission circuit Fa is turned off.
[0040]
On the other hand, when the selection permission circuit Fa is in the reset state (until the subsequent scanning line is selected and the preceding scanning control line is selected), the scanning control line belonging to the selection permission circuit Fa is selected by the switch element. And the scanning line are electrically disconnected. That is, the scanning control signal output from the scanning line driving circuit 13 is not permitted to be output as a scanning signal to the scanning line. Further, in this reset state, the selection permission circuit Fa turns on the first transistor Tr1 among the pair of first and second transistors Tr1 and Tr2 belonging to the selection permission circuit Fa.
[0041]
As shown in FIG. 2, the polarity signal line LP is orthogonal to the scanning lines Y1, Y2,..., Yn, and the first and second dummy scanning lines YD1 and YD2, that is, each of the first and second dummy scanning lines YD1 and YD2. It is formed in parallel with the first and second transistors Tr1 and Tr2. The polarity signal line LP is alternately supplied with an H level or L level polarity signal SLP according to the horizontal synchronization signal HSYNC output from the signal control circuit 11. The polarity signal SLP is a signal indicating one horizontal period as shown in FIG. 5, and the signal level is alternately inverted between the H level and the L level in synchronization with the common potential. This polarity signal SLP is supplied to the gate of each second transistor Tr2. Then, the second transistor Tr2 is turned on / off according to the horizontal synchronization signal HSYNC.
[0042]
As shown in FIG. 2, the charging power supply line LC is formed in parallel with the polarity signal line LP. The charging power supply line LC is supplied with a potential necessary for holding the pixel when the common potential becomes the L side. As shown in FIG. 5, the counter voltage Vc is a signal that is inverted in synchronization with the polarity signal SLP. When the polarity signal SLP is inverted to H level, it is inverted to L level, and the polarity signal SLP is changed to L level. When it is inverted, it is inverted to H level. The voltage of the charging power supply line LC is supplied to the corresponding scanning line via the first and second transistors Tr1 and Tr2 during the period when both the first and second transistors Tr1 and Tr2 are turned on. The That is, in each pair of the first and second transistors Tr1 and Tr2, the selection permission circuit Fa is in a reset state (a state where the scanning control line and the scanning line are electrically disconnected), and the polarity signal SLP is H At the level, the voltage of the charging power supply line LC is supplied to the scanning line via the charging power supply line LC.
[0043]
Based on the vertical synchronization signal VSYNC output from the signal control circuit 11, the signal line driving circuit 15 is connected to the image signals corresponding to the signal lines X 1, X 2,. D1, D2,..., Dm (m is a natural number) are generated. The image signals D1, D2,..., Dm are voltage signals generated in the signal line driving circuit 15 based on the image data D output from the signal control circuit 11. The signal line driving circuit 15 supplies the generated image signals D1, D2,..., Dm to the corresponding pixels 20 on the selected scanning line via the signal lines X1, X2,.
[0044]
Next, a driving method of the liquid crystal display device 10 configured as described above will be described with reference to FIG. Hereinafter, since the operation of each pixel 20 is the same, only the operation of each pixel 20 connected to the first scanning line Y1 will be described.
[0045]
FIG. 5 shows the polarity signal SLP, the counter voltage Vc, the first dummy scanning control signal SRD1, the first and second scanning control signals SR1 and SR2, the first and second output signals Q1 and Q2, the first and second outputs. 6 is a timing chart of potentials of two scanning lines Y1 and Y2.
[0046]
First, the first dummy scanning control signal SRD1 of H level is output from the scanning line driving circuit 13 via the first dummy scanning control line YSD1. Then, the first dummy scanning control line YSD1 is selected. At this time, the first and second scanning control lines YS1 and YS2 in the subsequent stage are not selected (first period T1).
[0047]
As a result, the selection permission circuit Fa formed corresponding to the first scanning control line YS1 is set, and the first scanning control signal SR1 output from the scanning line driving circuit 13 is changed to the first scanning signal SC1. Is output to the first scanning line Y1. At this time, since the first scanning control signal SR1 is an L-level scanning control signal, an L-level first scanning signal SC1 that is a reference potential is output to the first scanning line Y1. As a result, all the pixel transistors Qg of each pixel 20 connected to the first scanning line Y1 are turned off.
[0048]
At this time, of the pair of first and second transistors Tr1 and Tr2 belonging to the selection permission circuit Fa, the first transistor Tr1 is turned off. Therefore, the voltage of the charging power supply line LC is not supplied to the first scanning line Y1. That is, the voltage of the charging power supply line LC is not supplied to each pixel 20 connected to the first scanning line Y1 during the first period.
[0049]
Subsequently, when the scanning line driving circuit 13 changes the first dummy scanning control signal SRD1 from the H level to the L level, the first dummy scanning control line YSD1 becomes a non-selected state. As a result, the selection permission circuit Fa continues to output the H-level first output signal Q1 and the L-level second output signal Q2. Accordingly, the first scan control line YS1 is kept electrically connected to the first scan line Y1 via the first switch element SW1.
[0050]
In this state, the first scanning control signal SR1 at H level is output from the scanning line driving circuit 13 (second period T2). As a result, the H-level first scanning signal SC1 is output to the first scanning line Y1. As a result, all the pixels 20 in one row connected to the first scanning line Y1 are selected. At this timing, the image signal D1, D2,..., Dm is supplied from the signal line driving circuit 15 to each pixel 20 via the corresponding signal lines X1, X2,.
[0051]
Thereafter, when the first scanning control signal SR1 changes from the H level to the L level again, all the pixels 20 connected to the first scanning line Y1 are not selected. Therefore, the supply of the image signals D1, D2,..., Dm to each pixel 20 is completed at this timing. As a result, the gradation of each pixel 20 is controlled in accordance with the image signals D1, D2,.
[0052]
Thereafter, when the H-level scanning control signal SR2 is output from the scanning line driving circuit 13 to the second scanning control line YS2, the second scanning control line YS2 is selected (third period T3).
[0053]
As a result, the selection permission circuit Fa formed corresponding to the first scanning control line YS1 is in a reset state, and the first scanning control line YS1 and the first scanning line Y1 are electrically cut off. In the third period T3, the second output signal Q2 at H level is output from the selection permission circuit Fa. As a result, the first transistor Tr1 is turned on. At this time, since the L-level polarity signal SLP is supplied to the gate of the second transistor Tr2, the second transistor Tr2 is turned off. Therefore, in the third period T3, the first scanning line Y1 is electrically disconnected from the charging power supply line LC and is in a high impedance state.
[0054]
Thereafter, until the first dummy scanning control line YSD1 is selected, the first switch element SW1 is turned off, and the first scanning control line YS1 and the first scanning line Y1 are electrically cut off. The During this period, when the polarity signal SLP becomes H level in synchronization with the polarity signal SLP, the voltage of the charging power supply line LC is supplied to the first scanning line Y1 via the charging power supply line LC.
[0055]
Thereafter, in the same manner as described above for the other scanning control lines, the scanning line driving circuit 13 causes the first to nth scanning control lines YS1, YS2,..., YSn, the first and second dummy scanning control lines. YSD1 and YSD2 are line-sequentially selected in the order of YSD1-> YS1-> YS2-> ...-> YSn-> YSD2-> YSD1. Then, the scanning line control circuit 14a establishes electrical connection between the first dummy scanning control line YSD1 and the first dummy scanning line YD1, and between the second dummy scanning control line YSD2 and the second dummy scanning line YD2. The electrical connections and the electrical connections between the first to nth scanning control lines YS1, YS2,... YSn and the first to nth scanning lines Y1, Y2,. The signal line driving circuit 15 sequentially supplies image signals D1, D2,..., Dm corresponding to each row of the first to nth scanning lines Y1, Y2,. Key is controlled. As a result, an image corresponding to the image signals D1, D2,..., Dm can be displayed on the display panel unit 12.
[0056]
In the liquid crystal display device 10 configured as described above, the first to nth scanning control signals SR1, SR2,..., SRn or the first and first scanning control lines supplied to the preceding scanning control line and the succeeding scanning control line, respectively. Based on two dummy scanning control signals SRD1 and SRD2, a scanning line control circuit 14a having a selection permission circuit Fa for electrically connecting or disconnecting the scanning control line of its own stage and the scanning line corresponding to the scanning control line. Is arranged. Then, for example, in the period in which the first scanning control line YS1 and the first scanning line Y1 are electrically disconnected, the selection permission circuit Fa includes the first permission control circuit Fa according to the cycle of the horizontal synchronization signal HSYNC. The state where the voltage of the charging power supply line LC is supplied to the scanning line Y1 and the state where the first scanning line Y1 is in the high impedance state are intermittently switched.
[0057]
Therefore, even if the non-selection period is long, the potential of the first scanning line Y1 is intermittently set to the voltage of the charging power supply line LC. As a result, the first scanning line Y1 can be prevented from transitioning to an unintended potential. That is, for example, before the potential variation of the first to nth scanning lines Y1, Y2,..., Yn becomes excessive due to capacitive coupling with the counter electrode E2, the variation can be corrected according to the period of the horizontal synchronization signal HSYNC. . As a result, the image signals D1, D2,..., Dn can be supplied to each pixel 20 with good timing. Thus, a liquid crystal display device having a high-quality display quality can be provided. The selection permission circuit Fa is formed of a known SR flip-flop circuit. Therefore, the selection permission circuit Fa can be configured without configuring a new circuit.
[0058]
The first electrode, the second electrode, and the switching element described in the claims correspond to the pixel electrode E1, the counter electrode E2, and the pixel transistor Qg in the present embodiment, respectively. The switching circuit described in the claims corresponds to the first transistor Tr1 and the second transistor Tr2 in the present embodiment. Furthermore, the electro-optical device and the electro-optical element described in the claims correspond to the liquid crystal display device 10 and the liquid crystal capacitive element 21 in the present embodiment, respectively.
[0059]
According to the embodiment, the following features can be obtained.
(1) In the embodiment, the liquid crystal display device 10 is formed in the preceding stage between the display panel unit 12 and the scanning line driving circuit 13 on the first to nth scanning lines Y1, Y2,. Selection to permit or disallow the output of the scanning signal to the scanning line of its own stage based on the scanning control signal supplied to the scanning control line and the scanning control signal supplied to the scanning control line formed in the subsequent stage A scanning line control circuit 14a provided with a permission circuit Fa is arranged. If output of the scanning signal to the scanning line of the own stage is not permitted, the voltage of the charging power supply line LC is supplied to the scanning line of the self stage according to the polarity signal SLP or the horizontal synchronization signal is put into a high impedance state. It was set according to the cycle of HSYNC. That is, even if the non-selection period is long, the potential of the first scanning line Y1 is set to the voltage of the charging power supply line LC according to the cycle of the horizontal synchronization signal HSYNC. As a result, the scanning line can be prevented from transitioning to an unintended potential. Therefore, since the image signals D1, D2,..., Dn can be supplied to the pixel 20 with good timing, the gradation of the pixel 20 can be controlled with high accuracy. Thus, a liquid crystal display device having a high-quality display quality can be provided.
[0060]
(2) In the above-described embodiment, the selection permission circuit Fa is configured by a so-called SR flip-flop circuit in which two first and second NOR circuits 25a and 25b are electrically connected to each other. Therefore, the selection permission circuit Fa can be easily configured by using a known SR flip-flop circuit instead of configuring a new circuit.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a diagram showing an electrical configuration of the display panel unit and the scanning line control circuit according to the second embodiment of the present invention. FIG. 7 is a circuit diagram of a selection permission circuit formed in the scanning line control circuit according to the second embodiment of the present invention.
[0061]
The configuration of the liquid crystal display device 10 of the second embodiment is the same as that of the first embodiment except that the configuration of the scanning line control circuit and the selection permission circuit is the configuration shown in FIGS. Therefore, in this 2nd Embodiment, the code | symbol is made equal about the same structural member as the said 1st Embodiment, and the detailed description is abbreviate | omitted.
[0062]
As shown in FIG. 6, the scanning line control circuit 14b in this embodiment is configured to receive a shift direction switching signal DIR. The shift direction switching signal DIR is a signal for switching the direction in which the first to nth scanning lines Y1, Y2,. In addition, the shift direction switching signal DIR is output from the signal control circuit 11 in the present embodiment. The shift direction switching signal DIR is input to each selection permission circuit Fb.
[0063]
The scanning line control circuit 14b includes a selection permission circuit Fb formed corresponding to each of the first to nth switch elements SW1, SW2,. Since all of the circuit configurations of the selection permission circuit Fb are the same, hereinafter, the first scanning control line YS1, which is connected to the first scanning control line YS1 among the first to nth scanning control lines YS1, YS2,. Only the selection permission circuit Fb formed corresponding to the switch element SW1 will be described, and the detailed description of the other selection permission circuit Fb will be omitted.
[0064]
As shown in FIG. 7, the selection permission circuit Fb includes first and second NOR circuits 25a and 25b each having two input terminals and two first and second changeover switches S1 and S2. Yes. The first NOR circuit 25a includes a first output terminal K1 and a second output terminal K2. A first output signal Q1 is output from both the first and second output terminals K1, K2. The second NOR circuit 25b includes a third output terminal K3 and a fourth output terminal K4. A second output signal Q2 is output from both the third and fourth output terminals K3 and K4.
[0065]
The first output signal Q1 output from the first NOR circuit 25a is input to one input terminal of the second NOR circuit 25b. Similarly, the second output signal Q2 output from the second NOR circuit 25b is input to one input terminal of the first NOR circuit 25a.
[0066]
One of the first and third output terminals K1 and K3 is controlled to be switched by the first selector switch S1 and connected to the first output port U1. The first output port U1 is connected to the corresponding first to nth switch elements SW1, SW2,..., SWn. One of the second and fourth output terminals K2 and K4 is controlled to be switched by the second selector switch S2 and connected to the second output port U2. The second output port U2 is connected to the inverter of the switch element and the corresponding first transistor Tr1.
[0067]
Both the first and second changeover switches S1 and S2 are controlled to be switched by the shift direction switching signal DIR. Specifically, the shift direction switching signal DIR includes a normal rotation direction signal and an inversion direction signal. When the shift direction switching signal DIR of the forward direction signal is input, all the selection permission circuits Fb control the first changeover switches S1 to connect the first output terminal K1 and the first output port U1. And, the second changeover switch S2 is controlled to connect the fourth output terminal K4 and the second output port U2. As a result, each selection permission circuit Fb outputs the first output signal Q1 output from the first NOR circuit 25a via the first output port U1 and inputs it to the corresponding switch element. Each selection permission circuit Fb outputs a second output signal Q2 output from the second NOR circuit 25b via the second output port U2, and an inverter and a first transistor of the corresponding switch element. Input to the gate of Tr1. By doing so, the scanning line control circuit 14b converts the first to nth scanning control lines YS1, YS2,..., YSn and the first and second dummy scanning control lines YSD1, YSD2 from YSD1 → YS1 →. Select in the order of YS2 →... YSn → YSD2. As a result, the upper side of the image can be displayed on the first scanning line Y1 side, and the lower side can be displayed on the nth scanning line Yn side.
[0068]
Further, when the shift direction switching signal DIR of the inversion direction signal is input, all the selection permission circuits Fb control the first changeover switches S1 to connect the third output terminal K3 and the first output port U1. In addition, the second changeover switch S2 is controlled to connect the second output terminal K2 and the second output port U2. As a result, each selection permission circuit Fb outputs the first output signal Q1 output from the first NOR circuit 25a via the second output port U2, and inputs it to the corresponding switch element. Each selection permission circuit Fb outputs a second output signal Q2 output from the second NOR circuit 25b via the first output port U1, and an inverter and a first transistor of the corresponding switch element. Input to the gate of Tr1. By doing in this way, the scanning line control circuit 14b in this embodiment uses the first to nth scanning control lines YS1, YS2,..., YSn, and the first and second dummy scanning control lines YSD1, YSD2. YSD2 → YSn →... → YS2 → YS1 → YSD1 As a result, the upper side of the image can be displayed on the first scanning line Y1 side, and the lower side can be displayed on the nth scanning line Yn side.
[0069]
According to the embodiment, the following features can be obtained.
(1) In the above embodiment, the selection permission circuit Fb is configured by the first and second NOR circuits 25a and 25b each having two input terminals and the two first and second changeover switches S1 and S2. did. Then, the shift direction switching signal DIR of the forward direction signal controls each of the first and second changeover switches S1 and S2, so that the first output signal Q1 is applied to the corresponding switch element via the first output port U1. The second output signal Q2 is input to the inverter of the corresponding switch element and the gate of the first transistor Tr1 via the second output port U2 while being input. Thus, the first to nth scanning lines Y1, Y2,..., Yn are selected in the order of Y1 → Y2 →. Further, the shift direction switching signal DIR of the inversion direction signal controls each of the first and second changeover switches S1 and S2, so that the first output signal Q1 of the corresponding switch element is connected via the second output port U2. In addition to being input to the gate of the inverter and the first transistor Tr1, the second output signal Q2 is input to the corresponding switch element via the first output port U1. Thus, the first to nth scanning lines Y1, Y2,..., Yn are selected in the order of Yn → Yn−1 →.
[0070]
As a result, a liquid crystal display device capable of displaying an image upside down on the display panel unit 12 can be provided.
(Third embodiment)
Next, application of the electronic apparatus of the liquid crystal display device 10 as the electro-optical device described in the first to third embodiments will be described with reference to FIG. The liquid crystal display device 10 can be applied to various electronic devices such as a mobile personal computer, a mobile phone, and a digital camera.
[0071]
FIG. 8 is a perspective view showing the configuration of the mobile personal computer. In FIG. 8, the personal computer 50 includes a main body 52 having a keyboard 51 and a display unit 53 using the liquid crystal display device 10. Even in this case, the display quality of the display unit 53 using the liquid crystal display device 10 can be improved.
[0072]
In addition, embodiment of invention is not limited to the said embodiment, You may implement as follows.
In the first and second embodiments, the selection permission circuits Fa and Fb are configured by the two first and second NOR circuits 25a and 25b. However, the present invention is not limited to this, and as shown in FIG. Alternatively, the selection permission circuit Fc may be formed by using the two inverter circuits 60a and 60b and the two NAND circuits 65a and 65b. In FIG. 9, the same effect as that of the above embodiment can be obtained in this way.
[0073]
In the first to third embodiments, the liquid crystal display device 10 is provided with the liquid crystal capacitive element 21 having one color, but may be applied to a liquid crystal display device provided with a liquid crystal capacitive element capable of full color display. .
[0074]
In the above-described embodiment, a suitable effect is obtained by being embodied in a display device including the liquid crystal capacitive element 21, but may be embodied in a display device including an electro-optical element other than the liquid crystal capacitive element 21.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing an electrical configuration of a liquid crystal display device.
FIG. 2 is a diagram showing an electrical configuration of a display panel unit and a scanning line control circuit according to the first embodiment.
FIG. 3 is an equivalent circuit diagram of a pixel.
FIG. 4 is a circuit diagram of a selection permission circuit according to the first embodiment.
FIG. 5 shows a polarity signal, a counter voltage, a first dummy scanning control signal, first and second scanning control signals, first and second output signals, and first and second scanning line potentials, respectively. It is a timing chart.
FIG. 6 is a diagram showing an electrical configuration of a display panel unit and a scanning line control circuit according to a second embodiment.
FIG. 7 is a circuit diagram of a selection permission circuit according to a second embodiment.
FIG. 8 is a perspective view showing a configuration of a mobile personal computer for explaining a third embodiment.
FIG. 9 is a diagram for explaining another example of a selection permission circuit.
[Explanation of symbols]
E1 ... Pixel electrode as the first electrode, E2 ... Counter electrode as the second electrode, Fa, Fb, Fc ... Selection permission circuit, Qg ... Pixel transistor as the switching element, SLP ... Polarity signal, SC1, SC2, ..., SCn: scanning signal, Tr1, Tr2: first and second transistors as switching circuits, X1 to Xm: signal lines, Y1 to Yn: scanning lines, 10: liquid crystal display device as electro-optical device, 20 ... Pixel, 21... Liquid crystal capacitive element as electro-optical element, 50... Mobile personal computer as electronic device.

Claims (7)

A plurality of scanning lines, a plurality of signal lines, a switching element provided corresponding to an intersection of the scanning lines and the signal line, a pixel electrode provided corresponding to the switching element, and the scanning line A scanning line driving circuit that sequentially supplies a scanning signal for controlling on / off of the switching element,
Arranged between the scanning line driving circuit and the scanning line;
From the time when the scanning signal is supplied to the preceding scanning line to the time when the scanning signal is supplied to the subsequent scanning line, the scanning line driving circuit and the scanning line driving circuit are electrically connected, A scanning signal supplied to the scanning line is output to the scanning line;
After the scanning signal is supplied to the subsequent scanning line, the scanning line driving circuit is electrically disconnected from the scanning line driving circuit until the next scanning signal is supplied to the preceding scanning line. , the state of the scan line of the current stage of the scanning signal is not supplied, the electro-optical device of the high impedance state and the predetermined potential is characterized by comprising a scanning line control circuit to switch to a state in which it is supplied. The electro-optical device according to claim 1.
The scanning line control circuit includes:
Based on the scanning signal supplied to the preceding scanning line and the scanning signal supplied to the succeeding scanning line, the output of the scanning signal supplied to the own scanning line to the scanning line is permitted / not permitted. A selection permission circuit for outputting a control signal for controlling the output of the scanning signal to the scanning line of the own stage ;
Based on a control signal from the selection permission circuit, a switch element that electrically connects or disconnects the scanning line of its own stage and the scanning line driving circuit ,
The electro-optical device, wherein the selection permission circuit is configured by an SR flip-flop circuit. The electro-optical device according to claim 1,
An electro-optical device comprising a counter electrode facing the pixel electrode, wherein the potential of the scanning line is set to the predetermined potential when the potential of the counter electrode is L level. The electro-optical device according to claim 1,
An electro-optical device comprising a counter electrode facing the pixel electrode, wherein the potential of the scanning line is set to the predetermined potential when the potential of the counter electrode is at an H level. The electro-optical device according to claim 2.
Each selection permission circuit includes:
Based on the scanning signal supplied to the preceding scanning line and the scanning signal supplied to the succeeding scanning line, the control signal for controlling the output of the scanning signal to the scanning line of its own is selected from a combination of low and high. a first output signal comprising the outputs the second output signal,
Depending on the scanning direction of the scanning line driving circuit, the first output signal and the second output signal are switched ,
The switch element electrically connects or disconnects the scanning line of the first stage and the scanning line driving circuit according to a combination of low and high of the first output signal and the second output signal. An electro-optical device. The electro-optical device according to claim 1,
The electro-optical device, wherein the electro-optical element is a liquid crystal capacitive element.   An electronic apparatus comprising the electro-optical device according to claim 1.

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