JP4826167B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having a plurality of modules whose functions can be substituted for each other, and more particularly to a semiconductor integrated circuit in which a reduction in yield due to a module failure is improved.

  In recent years, in semiconductor integrated circuits, processing dimensions have been miniaturized and circuit configurations have been increased in scale, resulting in a serious decrease in yield due to manufacturing defects. Therefore, a method has been proposed in which a redundant circuit is provided in advance in a part of the entire circuit, and the defective portion is replaced with the redundant circuit so that the entire semiconductor chip does not become a defective product.

  For example, in the FPGA (field programmable gate array) logic circuit data generation method described in Patent Document 1, the necessity of failure avoidance is determined from failure information and logic information. Change the logical information to substitute.

In the semiconductor device described in Patent Document 2, data transfer between a plurality of circuit modules is performed by memory map type addressing. An ID code is assigned to each circuit module, and the failed circuit module is replaced with a redundant circuit module by operating the ID code to control the data transfer destination.
Japanese Patent No. 3491579 Japanese Patent No. 3192220

  The conventional technology described above has the following problems.

  In the FPGA described in Patent Document 1, when a basic cell that is a basic structural unit of a logic circuit is out of order, the wiring route is changed so as to bypass it. There are various types of bypass wiring for avoiding failures, and it is difficult to predict in advance what wiring route will be changed. For this reason, it is difficult to set a clear delay margin that can satisfy the desired delay condition even if any of the basic cells fails. It is necessary to anticipate.

  In the semiconductor device described in Patent Document 2, there is a possibility that the length of the data transfer distance between the circuit modules will vary greatly depending on the state of occurrence of the defect. It is necessary to specify the operation of each module assuming the maximum distance. Therefore, it is necessary to allow for a considerably large delay margin at the design stage, and it is difficult to optimize the performance of the entire system.

  The present invention has been made in view of such circumstances, and an object of the present invention is to relieve even if a defect occurs in a part of the circuit and to operate the entire circuit normally, and to relieve the defect. It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing a change in signal delay accompanying the above.

A semiconductor integrated circuit according to the present invention is arranged in a matrix of M rows (N + 1) columns (M and N are integers greater than 1), and a plurality of modules that can substitute for each other in the same row, and M rows and N columns matrix shape having input and output portions of the multiple arranged, a circuit block arranged alternately rows of the input and output section columns and rows of the module, in response to a control signal input, the A module of M rows and N columns obtained by removing one column from a module of M rows (N + 1) columns is selected, and each module of the selected M rows and N columns is selected in the row direction of the input / output unit of the M rows and N columns. Is connected to the input / output unit adjacent to one side with the first switch circuit, or 1: 1 with the input / output unit adjacent to the other side in the row direction and the second switch circuit. anda module selection unit to be connected to, said first switch circuit and the second When each of the switch circuits has a terminal for inputting a signal from the input / output unit and a terminal for outputting a signal to the module, and is set to ON by the control signal, a signal input to the input terminal Is output from the output terminal and is set to OFF by the control signal, the signal is input from at least one first inverter circuit that puts the output terminal in a high impedance state and the module. A terminal and a terminal for outputting a signal to the input / output unit, and when turned on by the control signal, the signal input to the input terminal is logically inverted and output from the output terminal. When being set to OFF by the control signal, it has at least one second inverter circuit for setting the output terminal in a high impedance state .
Preferably, the semiconductor integrated circuit generates the control signal of the module selection unit so as to select a module of M rows and N columns from a module of the M rows (N + 1) columns excluding a column including a failed module. The control part which comprises.

  According to the semiconductor integrated circuit, two modules connected to the same input / output unit can be arranged so that a difference in distance from the input / output unit is small. If the difference in the distance between the input / output unit and the module becomes smaller, the difference in the wiring length connecting the two becomes smaller, so the signal delay that occurs when the connection between the module and the input / output unit is switched due to defect relief etc. The change of becomes smaller.

According to the control signal, the module selection unit may be the module in the i-th column (i is an integer from 1 to N) belonging to the k-th row (k is an integer from 1 to M) or the (i + 1) -th module. ) One of the modules in the column may be selected, and the selected module may be connected to the input / output unit in the k-th row and the i-th column.
The N input / output units belonging to each row may be arranged at equal intervals, and the module in the k-th row and the i-th column and the module in the k-th row and the (i + 1) -th column are in the k-th row and the i-th column. You may arrange | position in the position where the distance with an input-output part becomes mutually equal.

Preferably, each of the semiconductor integrated circuits is inserted into a common power supply line of M modules belonging to each column, and is connected to the column not connected to the input / output unit according to the control signal. It has (N + 1) power switch circuits that cut off the power supply to the module to which it belongs.
As a result, power is not wasted in modules that are not connected to the input / output unit. Further, if the power supply to the failed module is cut off, the yield is improved.

When modules from the first column to the j-th column (j is an integer from 2 to N) belonging to one row of the matrix have the first function, the (j + 1) -th column belonging to the one row To the (N + 1) th column may have a second function including the first function. Then, when all the modules of the M rows (N + 1) columns operate normally, the control unit removes any one column from the (j + 1) th column to the (N + 1) th column. The control signal of the module selection unit is generated so as to select.
As a result, it is possible to relieve defects generated in the module having the first function by the redundant module having the second function.

In addition, the circuit block and the module selection unit may have a wider interval between wires belonging to the same wiring layer than the module of the M row (N + 1) column, or connect wires belonging to different wiring layers. The number of beers used to do so may be large.
As a result, the probability of failure of the circuit block and the module selection unit is reduced, and the yield is improved.

  The module of the M rows (N + 1) columns may have a higher density of circuit elements per unit area than the circuit block and the module selection unit. This reduces the circuit area.

The semiconductor integrated circuit may include a storage unit that stores a signal designating a module of one column to be separated from the input / output unit of M rows and N columns. In this case, the control unit may generate the control signal according to a signal stored in the storage unit.
The semiconductor integrated circuit may further include a signal input unit that inputs a signal specifying a module of one column to be separated from the input / output unit of M rows and N columns. In this case, the control unit may generate the control signal according to a signal input to the signal input unit.
Further, when a signal having a predetermined initial value is stored in the storage unit, the control unit generates the control signal according to a signal input to the signal input unit, and stores the initial value in the storage unit. When a signal having a value different from the value is stored, the control signal may be generated according to the signal stored in the storage unit.

The module selection unit may connect signal input terminals of modules disconnected from all input / output units to a wiring having a predetermined potential in accordance with the control signal.
Thereby, the potential of the signal input terminal of the module not connected to the input / output unit is stabilized.

  According to the present invention, two modules connected to the same input / output unit can be arranged so that the difference in distance from the input / output unit becomes small. The change in the signal delay that occurs when the connection between the module and the module is switched can be reduced.

<First Embodiment>
FIG. 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.
The semiconductor integrated circuit according to the present embodiment includes modules M11 to M19, M21 to M29, M31 to M39, M41 to M49, a general circuit block 100, and a module selection unit 50, for example, as shown in FIG.

Modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49 are each an embodiment of the module of the present invention.
The general circuit block 100 is an embodiment of the circuit block of the present invention.
The module selection unit 50 is an embodiment of the module selection unit of the present invention.

  Modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49 are arranged in a matrix of 4 rows and 9 columns. Here, if 'k' is an integer from 1 to 4 and 'n' is an integer from 1 to 9, the module Mkn belongs to the kth row and the nth column.

  The module Mkn is a group of circuits having a predetermined function, and modules belonging to the same row can substitute for each other. That is, the modules Mk1 to Mk9 belonging to the k-th row can substitute for each other. The modules Mk1 to Mk9 may all have the same circuit configuration, or may include a module having a different circuit configuration in part as long as the functions can be substituted for each other.

The circuit configuration and function of the module Mkn are arbitrary. For example, a circuit having an arithmetic / processing function such as a DSP (digital signal processor) may be used, or a circuit that performs a relatively simple logical operation like a lookup table may be used. Alternatively, each of a plurality of circuits having equivalent functions included in a semiconductor integrated circuit may be handled as one module.
The module Mkn is not limited to a digital circuit, and may be an analog circuit.

  The general circuit block 100 includes input / output units P11 to P18, P21 to P28, P31 to 38, and P41 for exchanging signals with the modules M11 to M19, M21 to M29, M31 to M39, and M41 to M49. ~ P48, and executes predetermined processing in cooperation with these modules. The circuit configuration and function of the general circuit block 100 are arbitrary. For example, only the wiring may be used.

  The input / output units P11 to P18, P21 to P28, P31 to 38, and P41 to P48 are arranged in a matrix of 4 rows and 8 columns. Here, if ‘i’ is an integer from 1 to 8, the input / output unit Pki belongs to the k-th row and the i-th column.

  Each of the input / output units P11 to P18, P21 to P28, P31 to 38, and P41 to P48 outputs at least one signal to one module and inputs at least one signal generated in the one module.

All of the input / output units Pk1 to Pk8 belonging to the same row may input / output the same combination of signals, or may include different types of input / output units that input / output different combinations of signals.
For example, when the module Mkn has three output terminals, those that input signals from all three output terminals, those that input signals from only one output terminal, and the like are in the input / output units Pk1 to Pk8. It may be mixed.

  The module selection unit 50 selects a 4-row, 8-column module obtained by removing one column from the above-described 4-row, 9-column module according to a control signal supplied from a control unit (not shown), and the selected four rows The 8-column module and the above-described 4-row 8-column input / output unit are connected one-to-one. In this case, the module selection unit 50 connects one module selected according to a control signal from two modules belonging to the same row to each of the input / output units belonging to the same row. That is, the module selection unit 50 selects one of the module Mki or the module Mk (i + 1) belonging to the kth row according to the control signal, and connects this to the input / output unit Pki on the kth row.

  For example, the module selection unit 50 excludes a column including a failed module (a specific column provided for redundancy when there is no failed module) in accordance with a control signal supplied from a control unit (not shown). A module of 4 rows and 8 columns is selected.

  When there is no failed module, for example, as shown in FIG. 1, the module Mki and the input / output unit Pki are connected one-to-one, and the modules M19 to M49 belonging to the ninth column are disconnected from all the input / output units. In the following, a module row that is disconnected from the input / output unit in a normal state where there is no faulty module may be referred to as a redundant column.

FIG. 2 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 1, and shows a connection state between the input / output unit and the module when the module M22 is out of order.
When the module 22 is out of order, the control unit (not shown) separates the second row of modules M12 to M42 including the module 22 from the second row of input / output units P12 to P42. The input / output units P12 to P42 in the second column are connected to the modules M13 to M43 in the third column instead of the modules M12 to M42 in the second column, and the input / output units P21 to P22 in the third column are connected to the third column. Are connected to the modules M14 to M44 in the fourth row instead of the modules M13 to M43. As described above, the connection destination of each input / output unit shifts toward the redundant column (9th column), so that the 4 × 8 input / output unit is paired with the 4 × 8 module excluding the second column. 1, the defect of the module M22 is relieved.

As described above, according to the semiconductor integrated circuit shown in FIG. 1, a module of 4 rows and 8 columns, which is obtained by removing one column from a module of 4 rows and 9 columns, is selected. The input / output units of 4 rows and 8 columns are connected one-to-one. Further, one module selected from two modules belonging to the same row is connected to each of the input / output units belonging to the same row.
Thereby, two modules (Mki, Mk (i + 1)) connected to the same input / output unit Pki can be arranged so that the difference in distance from the input / output unit Pki is small. For example, as shown in FIG. 1, by arranging eight input / output units (Pk1 to Pk8) in each row at equal intervals, two modules (Mki, Mk ( i + 1)) can be arranged.
By reducing the difference in the distance between the input / output unit and the module, the difference in the wiring length connecting the two can be reduced. Therefore, it is possible to reduce the change in signal delay that occurs when the connection between the module and the input / output unit is switched along with the defect relief.

  Further, since it is possible to accurately predict how much the signal delay will change due to defect relief based on the positional relationship between the modules Mki and Mk (i + 1) and the input / output unit Pki, for example, as described above. Compared to the case where accurate prediction is difficult as in Patent Document 1, it is possible to estimate the delay margin smaller. Thereby, a circuit that operates at high speed can be realized.

Further, according to the semiconductor integrated circuit shown in FIG. 1, since it is possible to relieve defects with a simple circuit configuration in which one of two modules is selected and connected to one input / output unit, an increase in the number of circuits and an extra circuit are possible. Generation of power consumption can be minimized.
Since a circuit that can be designed and manufactured by a conventional general method can be used for a switch circuit used for switching connection, a control unit, and a storage unit for holding defect information, a defect relief function is provided. The increase in cost can be suppressed to a minute.

  In addition, since it is not necessary to add a circuit to the general circuit block 100 in order to repair the defect, the conventional circuit can be used as it is, and the design burden by providing the defect repair function is reduced. Can be reduced.

  In addition, the structure in which the modules are regularly arranged makes it easy to optimize the wiring interval and the element characteristics, so that the increase in circuit area and the variation in circuit characteristics are suppressed compared to the structure in which the modules are randomly arranged. Can do.

  Further, according to the semiconductor integrated circuit shown in FIG. 1, since the connection state between the input / output unit and the module can be collectively controlled for each column, the connection state with the input / output unit can be independently set for each module. Compared to control, the number of control signals can be greatly reduced, and the circuit configuration of the control unit can be simplified.

  In addition, when a failure is inspected, the presence / absence of the failure may be inspected for each column, so that the inspection time can be shortened as compared with the case where each module is inspected.

  Furthermore, when writing fault module information using a storage element such as a fuse inside a semiconductor integrated circuit, it is only necessary to write information about the presence or absence of a fault for each column. Can be shortened.

  In the semiconductor integrated circuit according to the present embodiment, when a faulty module exists, all modules belonging to the same column as this are disconnected from the input / output unit, so that a normal module is also wasted. Therefore, when the failure occurrence probability is high, the number of modules that are wasted tends to increase. However, when the probability of failure is not so high or when there are a large number of relatively small modules, in order to achieve the same yield compared to the method of controlling the connection state for each module The required circuit area can be reduced.

  In the semiconductor integrated circuit shown in FIG. 1, the input / output units (Pk1 to Pk8) in the same row are arranged on a straight line. However, they may be arranged on a curved line or a meandering line, for example. , May be arranged in a zigzag manner. If the input / output units Pk1 to Pk8 are arranged at equal intervals on any line, the two modules (Mki, Mk (i + 1)) are arranged so that the distance from the input / output unit Pki is equal to each other. It is possible to arrange.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

  In the semiconductor integrated circuit according to the first embodiment, a portion that performs defect relief (a module of 4 rows and 9 columns) and a portion that does not perform defect relief (the general circuit block 100) are separated. If a defect occurs in a portion where defect repair is not performed, the entire circuit must be discarded. Therefore, it is desirable that the failure rate be as low as possible in this portion. Therefore, in the semiconductor integrated circuit according to the second embodiment, a portion (general circuit block 100) that does not perform defect relief, for example, by a technique such as DFM (design for manufacturing), performs a defect relief (4 rows by 9 columns). Take measures to make it more difficult to break down than modules).

  For example, in the general circuit block 100, the wiring pattern is formed so that the interval between wirings belonging to the same wiring layer is wider than that of a module of 4 rows and 9 columns. Thereby, it is possible to reduce the probability of occurrence of a failure due to a short circuit between the wires.

  Further, in the general circuit block 100, the number of vias used for connecting wirings belonging to different wiring layers may be increased as compared with a 4 × 9 module. For example, a measure is taken such that a wire that is normally connected by one via is connected by two vias. As a result, it is possible to reduce the probability of failure due to lack of vias.

  Conversely, in the 4 × 9 module, the density of circuit elements per unit area may be higher than that of the general circuit block 100. As the density of circuit elements increases, the probability of failure increases, but in the 4 × 9 module, the effect of defect relief can be expected. There is no big impact. Therefore, by increasing the density of the circuit elements in the 4 × 9 module, it is possible to reduce the area and performance of the entire circuit without greatly affecting the yield.

  Note that the module selection unit 50 may be included in a portion where the above-described defect repair is performed, or may be included in a portion where the defect repair is not performed.

  When the module selection unit 50 is included in the portion where the defect is not relieved, the module selection unit 50 is provided with the same measures as the general circuit block 100. In other words, compared to a 4-row 9-column module, a wiring pattern is formed so that the spacing between wirings belonging to the same wiring layer is widened, and wiring is performed using more vias than a 4-row 9-column module. Take measures to connect the. Thereby, the fall of the yield by the failure of the module selection part 50 can be suppressed.

On the other hand, when the module selection unit 50 is included in a portion where no defect is repaired, the probability of occurrence of a failure is higher than when the above countermeasure is taken.
As a case where the failure of the switch circuit affects the entire circuit, for example, a circuit such as a switch provided in a path for inputting a signal to the general circuit block 100 fails in a short-circuit state, A case where a constant voltage signal is continuously input to the circuit block 100 is exemplified. If such a failure does not occur so much, by including the module selection unit 50 in a portion that does not repair the defect, the pitch between wirings and the number of vias can be reduced, so that the circuit area can be reduced. Is obtained.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

  In the semiconductor integrated circuit according to the first embodiment, it is specified that the modules Mk1 to Mk8 belonging to the same row can substitute for each other, but these modules must all have the same function. There is no sex. Even when a part of a plurality of modules has upward compatibility with another part, the function between the modules can be replaced.

For example, it is assumed that there are a module having a first function and a module having a second function including the first function. In this case, the module having the second function can replace all the functions of the module having the first function. On the other hand, the module having the first function cannot replace all the functions of the module having the second function, but can be replaced if it is a part of the functions.
Thus, in this specification, when “modules can substitute for each other's functions”, not only the modules can substitute for each other's functions, but also some of the functions of each other. This includes cases where substitution is possible.

FIG. 3 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit according to the third embodiment.
In the semiconductor integrated circuit shown in FIG. 3, the modules in the fourth column to the ninth column in the semiconductor integrated circuit shown in FIG. 1 are changed to high-functional modules that are upwardly compatible with the modules in the first column to the third column. It is a thing. Since the former module includes the functions of the latter module, even if a defect occurs in the latter module, the defect can be relieved by replacing it with the former module.

When all the modules operate normally, as shown in FIG. 3, the second row of modules M12 to M42 are connected to the second row of input / output units P12 to P42, and the third row of input / output units P13 to P43. Are connected to modules M13 to M43 in the third row.
On the other hand, when the module M22 in the second column is defective (FIG. 4), the modules M13 to M43 in the third column are connected to the input / output units P12 to P42 in the second column, and the input / output units P13 to P3 in the third column are connected. The fourth row of modules M14 to M44 are connected to P43. Since the fourth row of modules M14 to M44 have upward compatibility with the third row of modules M13 to M43, the fourth row of modules M14 connected to the third row of input / output units P13 to P43. To M44 can provide the general circuit block 100 with the same functions as the modules M13 to M43 in the third row.

As described above, in the semiconductor integrated circuit shown in FIG. 3, the high-function modules in the fourth column to the ninth column have upward compatibility with the low-function modules in the first column to the third column, The former function includes the latter function. If all the modules in 4 rows and 9 columns operate normally (FIG. 3), the 4 rows and 8 columns module and the 4 rows and 8 columns input / output except for any one column from the 4th column to the 9th column. Are connected to each other in a one-to-one relationship, and a row of highly functional modules is a redundant column. By using this redundant column, defects of two types of modules (high function and low function) can be relieved.
Accordingly, since it is not necessary to provide a redundant low function module in order to rescue the low function module, an increase in circuit area can be suppressed.

<Fourth Embodiment>
Next, a fourth embodiment will be described.

FIG. 5 is a diagram showing an example of the configuration of the semiconductor integrated circuit according to the present embodiment, and the same reference numerals in FIGS. 1 and 5 denote the same components.
5 includes four rows and nine columns of modules (M11 to M19, M21 to M29, M31 to M39, M41 to M49), and four rows and eight columns of input / output units provided in the general circuit block 100. (P11 to P18, P21 to P28, P31 to 38, P41 to P48) and switch circuits SWA11 to SWA18, SWA21 to SWA28, SWA31 to SWA38, SWA41 to SWA48, SWB11 to SWB18, SWB21 to SW included in the module selection unit 50 SWB28, SWB31 to SWB38, SWB41 to SWB48, power switch circuits PS1 to PS9, a control unit 1, a signal input unit 2, and a storage unit 3.

A group of the switch circuits SWA11 to SWA18, SWA21 to SWA28, SWA31 to SWA38, and SWA41 to SWA48 is an embodiment of the first switch group of the present invention.
A collection of the switch circuits SWB11 to SWB18, SWB21 to SWB28, SWB31 to SWB38, SWB41 to SWB48 is an embodiment of the second switch group of the present invention.
Each of the power switch circuits PS1 to PS9 is an embodiment of the power switch circuit of the present invention.
The control unit 1 is an embodiment of the control unit of the present invention.
The signal input unit 2 is an embodiment of the signal input unit of the present invention.
The storage unit 3 is an embodiment of the storage unit of the present invention.

  In the semiconductor integrated circuit according to the present embodiment, the module Mkn (k = 1,..., 4; n = 1,..., 9) has five inputs (IN1 to IN5) and three outputs (OUT1 to OUT3). A programmable logic circuit.

FIG. 6 is a diagram illustrating an example of the configuration of the module Mkn.
The module Mkn illustrated in FIG. 6 includes two-input one-output look-up tables LT1 and LT2, and a selector circuit SEL1.

  The lookup table LT1 performs a logical operation on the input signals IN1 and IN2, and outputs the result as a signal OUT1. The logical function of the lookup table LT1 is set according to 4-bit data (LA1, LA2, LA3, LA4). The 4-bit data may be stored in a storage means (SRAM, flip-flop, non-volatile memory, etc.) for each lookup table, and may be written to the circuit when manufacturing the circuit or after manufacturing. A via, wiring, or the like may be formed at a specific position of the metal wiring layer using a line beam device or the like, and may be fixed as a circuit during manufacturing.

  In the example of FIG. 6, the lookup table LT1 includes NAND circuits U11 to U14, inverter circuits U21 to U27, and transmission gate circuits TG1 to TG4.

  The inverter circuit U21 logically inverts the input signal IN1. The inverter circuit U22 logically inverts the input signal IN2.

  The NAND circuit U11 outputs an inverted logical product of the input signals IN1 and IN2. The NAND circuit U12 outputs an inverted logical product of the output signal of the inverter circuit U21 and the input signal IN2. The NAND circuit U13 outputs an inverted logical product of the input signal IN1 and the output signal of the inverter circuit U22. The NAND circuit U14 outputs an inverted logical product of the output signal of the inverter circuit U21 and the output signal of the inverter circuit U22.

  The inverter circuit U23 logically inverts the output signal of the NAND circuit U11. The inverter circuit U24 logically inverts the output signal of the NAND circuit U12. The inverter circuit U25 logically inverts the output signal of the NAND circuit U13. The inverter circuit U26 logically inverts the output signal of the NAND circuit U14.

The transmission gate circuit has a p-type MOS transistor and an n-type MOS transistor connected in parallel.
In the transmission gate circuit TG1, the output signal of the NAND circuit U11 is input to the gate of the p-type MOS transistor, and the output signal of the inverter circuit U23 is input to the gate of the n-type MOS transistor.
In the transmission gate circuit TG2, the output signal of the NAND circuit U12 is input to the gate of the p-type MOS transistor, and the output signal of the inverter circuit U24 is input to the gate of the n-type MOS transistor.
In the transmission gate circuit TG3, the output signal of the NAND circuit U13 is input to the gate of the p-type MOS transistor, and the output signal of the inverter circuit U25 is input to the gate of the n-type MOS transistor.
In the transmission gate circuit TG4, the output signal of the NAND circuit U14 is input to the gate of the p-type MOS transistor, and the output signal of the inverter circuit U26 is input to the gate of the n-type MOS transistor.
One terminal of transmission gate circuits TG1, TG2, TG3, TG4 is connected to the output terminal of data LA1, LA2, LA3, LA4, respectively, and the other terminal is connected in common to the input terminal of inverter circuit U27.

  The inverter circuit U27 logically inverts data (LA1 to LA4) input via the transmission gate circuits TG1 to TG4 and outputs the result as a signal OUT1.

When the input signal IN1 has the value “1” and the input signal IN2 has the value “1”, the output signal of the NAND circuit U11 has the value “0”, and the output signals of the other NAND circuits have the value “1”. As a result, only the transmission gate circuit TG1 is turned on, and the other transmission gate circuits are turned off. As a result, the data LA1 is logically inverted in the inverter circuit U27 and output as the signal OUT1.
Thus, when the input signals IN1 and IN2 are given, one of the transmission gate circuits TG1 to TG4 is turned on according to the combination of the values, and any of the data LA1 to LA4 is logically inverted in the inverter circuit U27, and the signal Output as OUT1.

The lookup table LT2 performs a logical operation on the input signals IN3 and IN4, and outputs the result as a signal OUT1. The logical function of the lookup table LT1 is set according to 4-bit data (LB1, LB2, LB3, LB4).
The lookup table LT2 has a configuration similar to that of the lookup table LT1 described above.

  The selector circuit SEL1 selects one of the two lookup tables (LT1, LT2) according to the input signal IN5, and outputs the output signal of the selected lookup table as the signal OUT3.

  In the example of FIG. 6, the selector circuit SEL1 includes inverter circuits U28 and U29 and transmission gate circuits TG5 and TG6.

The inverter circuit U28 logically inverts the input signal IN5.
An input signal IN5 is input to the gates of the p-type MOS transistor of the transmission gate circuit TG5 and the n-type MOS transistor of the transmission gate circuit TG6. The output signal of the inverter circuit U28 is input to the gates of the n-type MOS transistor of the transmission gate circuit TG5 and the p-type MOS transistor of the transmission gate circuit TG6.
One terminal of the transmission gate circuit TG5 is connected to the output terminal of the lookup table LT1 (in the example of FIG. 6, the input terminal of the inverter circuit U27). One terminal of the transmission gate circuit TG6 is connected to the output terminal of the lookup table LT2 (in the example of FIG. 6, the input terminal of the inverter circuit U27). The other terminals of the transmission gate circuits TG5 and TG6 are commonly connected to the input terminal of the inverter circuit U29.
The inverter circuit U29 logically inverts the output signal of the lookup table LT1 or LT2 input via the transmission gate circuit TG5 or TG6, and outputs it as a signal OUT3.

When the input signal IN5 has a value “0”, the transmission gate circuit TG5 is turned on and the transmission gate circuit TG6 is turned off, so that the output signal OUT3 becomes equal to the output signal OUT1 of the lookup table LT1. Conversely, when the input signal IN5 has the value “1”, the output signal OUT3 is equal to the output signal OUT2 of the lookup table LT2.
That is, one of eight data (LA1 to LA4, LB1 to LB4) is selected according to the combination of the values of the input signals IN1 to IN5, logically inverted in the inverter circuit U29, and output as the signal OUT3.
Therefore, when the output signal OUT3 is used, the module Mkn operates as a lookup table with 5 inputs and 1 output.
The above is the description of the module Mkn.

  In the semiconductor integrated circuit according to the present embodiment, the module selection unit 50 has two switch circuits for each input / output unit.

  The switch circuit SWAki is connected between the input / output unit Pki in the k-th row and the i-th column and the module Mki in the k-th row and the i-th column, and the control signal Sci supplied from the control unit 1 has the value “1”. Is turned on when the value is "0" and turned off when the value is "0".

  The switch circuit SWBki is connected between the input / output unit Pki in the k-th row and the i-th column and the module Mk (i + 1) in the k-th row and the (i + 1) -th column, and the control signal Sci supplied from the control unit 1 Is turned off when the value is '1', and turned on when the value is '0'.

The switch circuit SWAki has at least one circuit for turning on / off the signal Sin transmitted from the input / output unit Pki to the module Mki and at least one circuit for turning on / off the signal Sout transmitted from the module Mki to the input / output unit Pki. Have one.
Similarly, the switch circuit SWBki turns on / off the signal Sin transmitted from the input / output unit Pki to the module Mk (i + 1) and the signal Sout transmitted from the module Mk (i + 1) to the input / output unit Pki. Each circuit has at least one circuit to be turned on / off.
In the following, a circuit for turning on / off individual signals in this way is called a switch element, and some configuration examples thereof will be described.

  FIG. 7 is a diagram illustrating a first configuration example of a switch element that turns on / off a signal transmitted from the input / output unit to the module.

The switch element SE1 shown in FIG. 7 is a circuit that turns on / off the signal Sin1 transmitted from the input / output unit Pki to the module Mki, and is included in the switch circuit SWAki.
The switch element SE1 has an input terminal Ti for inputting a signal from the input / output unit Pki and an output terminal To for outputting a signal to the module Mki. When the control signal Sci is the value “1” (high level), the signal input to the input terminal Ti is logically inverted and output from the output terminal To. When the control signal Sci is the value “0” (low level) The output terminal To is set to a high impedance state.

The switch element SE2 illustrated in FIG. 7 is a circuit that turns on / off the signal Sin2 transmitted from the input / output unit Pki to the module Mk (i + 1), and is included in the switch circuit SWBki.
The switch element SE2 has an input terminal Ti for inputting a signal from the input / output unit Pki and an output terminal To for outputting a signal to the module Mk (i + 1). When the control signal Sci is the value “0” (low level), the signal input to the input terminal Ti is logically inverted and output from the output terminal To. When the control signal Sci is the value “1” (high level) The output terminal To is set to a high impedance state.
Further, the switch element SE2 connects the output terminal To to the ground line VSS when a signal instructing to disconnect the connection destination module Mk (i + 1) from all the input / output units is input.

The switch elements SE1 and SE2 both have four transistors (Q1 to Q4).
The p-type MOS transistors Q1 and Q2 are connected in series between the power supply line VCC and the output terminal To, and the n-type MOS transistors Q3 and Q4 are connected in series between the output terminal To and the ground line VSS. The signal SMin1 from the input / output unit Pki is input to the gates of the p-type MOS transistors Q1 and Q4.

In switch element SE1, control signal / Sci obtained by logically inverting control signal Sci is input to the gate of p-type MOS transistor Q2. Control signal Sci is input to the gate of n-type MOS transistor Q3.
On the other hand, in the switch element SE2, the control signal Sci is input to the gate of the p-type MOS transistor Q2, and the control signal / Sci is input to the gate of the n-type MOS transistor Q3.

When the control signal Sci is at a high level (value “1”), since the p-type MOS transistor Q2 and the n-type MOS transistor Q3 are turned on in the switch element SE1, the switch element SE1 operates as an inverter circuit. The signal SMin1 from the input / output unit Pki is logically inverted by this inverter circuit and input to the module Mki. Further, in the switch element SE2, the p-type MOS transistor Q2 and the n-type MOS transistor Q3 are turned off, the output terminal To becomes in a high impedance state, and the module Mk (i + 1) and the input / output unit Pki are disconnected.
When the control signal Sci is at a low level (value “0”), the switch element SE2 operates as an inverter circuit contrary to the above. The signal SMin1 from the input / output unit Pki is logically inverted by the inverter circuit and input to the module Mk (i + 1). Further, in the switch element SE1, the output terminal To is in a high impedance state, and the module Mki and the input / output unit Pki are disconnected.

  FIG. 8 is a diagram illustrating a first configuration example of a switch element that turns on / off a signal transmitted from the module to the input / output unit.

A switch element SE3 illustrated in FIG. 8 is a circuit that turns on / off a signal Sout1 transmitted from the module Mki to the input / output unit Pki, and is included in the switch circuit SWAki.
The switch element SE3 has an input terminal Ti for inputting a signal from the module Mki and an output terminal To for outputting a signal to the input / output unit Pki. When the control signal Sci is the value “1” (high level), the signal input to the input terminal Ti is logically inverted and output from the output terminal To. When the control signal Sci is the value “0” (low level) The output terminal To is set to a high impedance state.

The switch element SE4 illustrated in FIG. 8 is a circuit that turns on / off the signal Sout2 transmitted from the module Mk (i + 1) to the input / output unit Pki, and is included in the switch circuit SWBki.
The switch element SE4 has an input terminal Ti for inputting a signal from the module Mk (i + 1), and an output terminal To for outputting a signal to the input / output unit Pki. When the control signal Sci is the value “0” (low level), the signal input to the input terminal Ti is logically inverted and output from the output terminal To. When the control signal Sci is the value “1” (high level) The output terminal To is set to a high impedance state.

  Similarly to the switch elements SE1 and SE2, the switch elements SE3 and SE4 have four transistors (Q1 to Q4). The p-type MOS transistors Q1 and Q2 are connected in series between the power supply line VCC and the output terminal To, and the n-type MOS transistors Q3 and Q4 are connected in series between the output terminal To and the ground line VSS.

In the switch element SE3, a control signal / Sci is input to the gate of the p-type MOS transistor Q2, a control signal Sci is input to the gate of the n-type MOS transistor Q3, and a module is connected to the gates of the p-type MOS transistors Q1 and Q4. A signal Sout1 from Mki is input.
On the other hand, in switch element SE4, control signal Sci is input to the gate of p-type MOS transistor Q2, control signal / Sci is input to the gate of n-type MOS transistor Q3, and the gates of p-type MOS transistors Q1 and Q4 are input. Receives the signal Sout2 from the module Mk (i + 1).

When the control signal Sci is at a high level (value “1”), the p-type MOS transistor Q2 and the n-type MOS transistor Q3 are turned on in the switch element SE3, and the switch element SE3 operates as an inverter circuit. The signal Sout1 from the module Mki is logically inverted by the inverter circuit and input to the input / output unit Pki. In addition, in the switch element SE4, the p-type MOS transistor Q2 and the n-type MOS transistor Q3 are turned off, the output terminal To is in a high impedance state, and the module Mk (i + 1) and the input / output unit Pki are disconnected.
When the control signal Sci is at a low level (value “0”), the switch element SE4 operates as an inverter circuit contrary to the above. The signal Sout2 from the module Mk (i + 1) is logically inverted by this inverter circuit and input to the input / output unit Pki. In the switch element SE3, the output terminal To is in a high impedance state, and the module Mki and the input / output unit Pki are disconnected.

  FIG. 9 is a diagram illustrating a second configuration example of a switch element that turns on / off a signal transmitted from the input / output unit to the module.

The switch element SE1A shown in FIG. 9 is a circuit for turning on / off the signal Sin1 transmitted from the input / output unit Pki to the module Mki, as in the switch element SE1 shown in FIG. 7, and is included in the switch circuit SWAki.
The switch element SE1A has a transmission gate circuit inserted in a path for transmitting a signal from the input / output unit Pki to the module Mki. This transmission gate circuit includes a p-type MOS transistor Q5 and an n-type MOS transistor Q6 connected in parallel.

The switch element SE2A shown in FIG. 9 is a circuit for turning on / off the signal Sin2 transmitted from the input / output unit Pki to the module Mk (i + 1), as in the switch element SE2 in FIG. 7, and is included in the switch circuit SWBki. .
The switch element SE2A has a transmission gate circuit inserted in a path for transmitting a signal from the input / output unit Pki to the module Mk (i + 1). This transmission gate circuit is configured by a p-type MOS transistor Q5 and an n-type MOS transistor Q6 connected in parallel, similarly to the switch element SE1A.

  In switch element SE1A, control signal / Sci is input to the gate of p-type MOS transistor Q5, and control signal Sci is input to the gate of n-type MOS transistor Q6. On the other hand, in switch element SE2A, control signal Sci is input to the gate of p-type MOS transistor Q5, and control signal / Sci is input to the gate of n-type MOS transistor Q6.

When the control signal Sci is at a high level (value “1”), the p-type MOS transistor Q5 and the n-type MOS transistor Q6 of the switch element SE1A are driven on, and the switch element SE1A becomes conductive. The signal SMin1 output from the input / output unit Pki is input to the module Mki via the switch element SE1A. Further, the p-type MOS transistor Q5 and the n-type MOS transistor Q6 of the switch element SE2A are driven off, the switch element SE2A is cut off, and the module Mk (i + 1) and the input / output unit Pki are disconnected.
When the control signal Sci is at a low level (value “0”), the switch element SE2A is turned on, contrary to the above. The signal SMin1 output from the input / output unit Pki is input to the module Mk (i + 1) via the switch element SE2A. Further, the switch element SE1A is cut off, and the module Mki and the input / output unit Pki are disconnected.

  In the example of FIG. 9, inverter circuits U5 and U6 are inserted in the input side (input / output unit side) paths of the switch elements SE1A and SE2A in order to improve the signal delay due to the resistance component of the transmission gate circuit.

  FIG. 10 is a diagram illustrating a second configuration example of a switch element that turns on / off a signal transmitted from the module to the input / output unit.

A switch element SE3A shown in FIG. 10 is a circuit for turning on / off the signal Sout1 transmitted from the module Mki to the input / output unit Pki, as in the switch element SE3 shown in FIG. 8, and is included in the switch circuit SWAki.
The switch element SE3A has a transmission gate circuit inserted in a path for transmitting a signal from the module Mki to the input / output unit Pki. This transmission gate circuit includes a p-type MOS transistor Q5 and an n-type MOS transistor Q6 connected in parallel.

The switch element SE4A shown in FIG. 10 is a circuit for turning on / off the signal Sout2 transmitted from the module Mk (i + 1) to the input / output unit Pki, as in the switch element SE4 in FIG. 8, and is included in the switch circuit SWBki. .
The switch element SE4A has a transmission gate circuit inserted in a path for transmitting a signal from the module Mk (i + 1) to the input / output unit Pki. This transmission gate circuit is configured by a p-type MOS transistor Q5 and an n-type MOS transistor Q6 connected in parallel, similarly to the switch element SE3A.

  In switch element SE3A, control signal / Sci is input to the gate of p-type MOS transistor Q5, and control signal Sci is input to the gate of n-type MOS transistor Q6. On the other hand, in switch element SE4A, control signal Sci is input to the gate of p-type MOS transistor Q5, and control signal / Sci is input to the gate of n-type MOS transistor Q6.

When the control signal Sci is at a high level (value “1”), the p-type MOS transistor Q5 and the n-type MOS transistor Q6 of the switch element SE3A are driven on, and the switch element SE1A becomes conductive. The signal Sout1 output from the module Mki is input to the input / output unit Pki via the switch element SE3A. Also, the p-type MOS transistor Q5 and the n-type MOS transistor Q6 of the switch element SE4A are driven off, the switch element SE4A is cut off, and the module Mk (i + 1) and the input / output unit Pki are disconnected.
When the control signal Sci is at a low level (value “0”), the switch element SE4A is turned on, contrary to the above. The signal Sout2 output from the module Mk (i + 1) is input to the input / output unit Pki via the switch element SE4A. In addition, the switch element SE3A is cut off, and the module Mki and the input / output unit Pki are disconnected.

  In order to improve signal delay due to the resistance component of the transmission gate circuit, an inverter circuit may be inserted in the path on the input side (module side) of the switch elements SE1A and SE2A.

  FIG. 11 is a diagram illustrating a third configuration example of the switch element for turning on / off a signal transmitted from the input / output unit to the module.

  The switch elements SE1B and SE2B shown in FIG. 11 are obtained by deleting the p-type MOS transistors Q5 of the switch elements SE1A and SE2A shown in FIG. 9, and the basic operation is the same as that of the switch elements SE1A and SE2A. That is, when the control signal Sci is at a high level (value “1”), the signal from the input / output unit Pki is transmitted to the module Mki, and the input / output unit Pki and the module Mk (i + 1) are disconnected. When the control signal Sci is at a low level (value “0”), the signal from the input / output unit Pki is transmitted to the module Mk (i + 1), and the input / output unit Pki and the module Mki are disconnected.

  FIG. 12 is a diagram illustrating a third configuration example of a switch element that turns on / off a signal transmitted from the module to the input / output unit.

  The switch elements SE3B and SE4B shown in FIG. 12 are obtained by deleting the p-type MOS transistors Q5 of the switch elements SE3A and SE4A shown in FIG. 10, and the basic operation is the same as that of the switch elements SE3A and SE4A. That is, when the control signal Sci is at a high level (value “1”), the signal from the module Mki is transmitted to the input / output unit Pki, and the input / output unit Pki and the module Mk (i + 1) are disconnected. When the control signal Sci is at a low level (value “0”), the signal from the module Mk (i + 1) is transmitted to the input / output unit Pki, and the input / output unit Pki and the module Mki are disconnected.

  When a high level signal is input to the switch elements (SE1B, SE2B, SE3B, SE4B) shown in FIGS. 11 and 12, the signal output through these switch elements is the n-type MOS transistor Q6. A voltage drop corresponding to the threshold value occurs. Therefore, when the switch elements shown in FIGS. 11 and 12 are used, it is required that the influence (delay, noise margin, etc.) on the circuit operation due to this voltage drop be within an allowable range.

  Here, referring to FIG. 13 and FIG. 14 for the structure when the switch elements of the first configuration example (FIGS. 7 and 8) and the second configuration example (FIGS. 9 and 10) are formed on a semiconductor substrate. To explain.

FIG. 13 is a plan view showing a structural example of the switch elements (SE1 to SE4) of the first configuration example shown in FIGS.
FIG. 13A shows an example in which two MOS transistors are formed in each of two active regions (D1, D2), and FIG. 13B shows four active regions (D3-D6). An example in which one MOS transistor is formed for each is shown.

  In the structural example shown in FIG. 13A, active regions D1 and D2 are formed side by side on a semiconductor substrate. An n-type impurity is introduced into the active region D1, and a p-type impurity is introduced into the active region D2. The active regions D1 and D2 have a rectangular shape as shown in FIG. 13A, for example, and their sizes are substantially the same. Between the active regions, regions (element isolation regions) for electrically isolating elements in different active regions are provided.

  Gate electrodes G1 to G3 are provided on the active regions D1 and D2 via a gate oxide film (not shown).

The gate electrode G1 is provided over the two active regions (D1, D2). A channel of the p-type MOS transistor Q1 is formed in a portion facing the gate electrode G1 in the active region D1. In the active region D2, the channel of the n-type MOS transistor Q4 is formed in the portion facing the gate electrode G1.
The gate electrode G1 corresponds to the input terminal Ti in the switch elements (SE1 to SE4) of the first configuration example.

The gate electrode G2 is provided on the active region D1 on the right side of the gate electrode G1 in the drawing. A channel of the p-type MOS transistor Q2 is formed in a portion facing the gate electrode G2 in the active region D1.
The gate electrode G3 is provided on the active region D2 on the right side of the gate electrode G1 in the drawing. A channel of the n-type MOS transistor Q3 is formed in a portion facing the gate electrode G3 in the active region D2.
The gate electrodes G2 and G3 correspond to terminals for inputting the control signal Sci or its logical inversion signal / Sci.

  A region A1 on the left side of the gate electrode G1 in the active region D1 corresponds to the source of the p-type MOS transistor Q1. This region A1 is connected to the metal wiring W1 through a via (not shown). The metal wiring W1 corresponds to the power supply line VCC.

  A region A2 sandwiched between the gate electrodes G1 and G2 in the active region D1 corresponds to the drain of the p-type MOS transistor Q1 and the source of the p-type MOS transistor Q2. The drain of the p-type MOS transistor Q1 and the source of the p-type MOS transistor Q2 are connected to each other in this region A2.

  A region A3 on the right side of the gate electrode G2 in the active region D1 corresponds to the drain of the p-type MOS transistor Q2. Further, the region A4 on the right side of the gate electrode G3 in the active region D2 corresponds to the drain of the n-type MOS transistor Q3. The areas A3 and A4 are connected to each other via a via (not shown) and a metal wiring W2. A connection point between the regions A3 and A4 corresponds to the output terminal To in the switch elements (SE1 to SE4) of the first configuration example.

  In the active region D2, a region A5 sandwiched between the gate electrodes G1 and G3 corresponds to the source of the n-type MOS transistor Q3 and the drain of the n-type MOS transistor Q4. The source of the n-type MOS transistor Q3 and the drain of the n-type MOS transistor Q4 are connected to each other in this region A5.

  A region A6 on the left side of the gate electrode G1 in the active region D2 corresponds to the source of the n-type MOS transistor Q4. This region A6 is connected to the metal wiring W3 through a via (not shown). The metal wiring W3 corresponds to the ground line VSS.

In the structural example shown in FIG. 13B, four active regions D3, D4, D5, and D6 are formed in a matrix on a semiconductor substrate. In the example of FIG. 13B, the active region D4 is formed on the right side of the active region D3, the active region D6 is formed below the active region D3, the active region D5 is below the active region D4, and the active region D6. It is formed on the right side.
An n-type impurity is introduced into the active regions D3 and D4, and a p-type impurity is introduced into the active regions D5 and D6. The active regions D3 to D6 have a rectangular shape as shown in FIG. 13B, for example, and their sizes are substantially the same. An element isolation region is provided between the active regions.

  Gate electrodes G4 to G6 are provided on the active regions D3 to D6 via a gate oxide film (not shown).

The gate electrode G4 is provided over the active regions D3 and D6. A channel of the p-type MOS transistor Q1 is formed in a portion facing the gate electrode G4 in the active region D3. In the active region D6, the channel of the n-type MOS transistor Q4 is formed in the portion facing the gate electrode G4.
The gate electrode G4 corresponds to the input terminal Ti in the switch elements (SE1 to SE4) of the first configuration example.

The gate electrode G5 is provided on the active region D4. A channel of the p-type MOS transistor Q2 is formed in a portion facing the gate electrode G5 in the active region D4.
The gate electrode G6 is provided on the active region D5. A channel of the n-type MOS transistor Q3 is formed in a portion facing the gate electrode G6 in the active region D5.
The gate electrodes G5 and G6 correspond to terminals for inputting the control signal Sci or its logical inversion signal / Sci.

  A region A7 on the left side of the gate electrode G4 in the active region D3 corresponds to the source of the p-type MOS transistor Q1. This region A7 is connected to the metal wiring W4 through a via (not shown). Metal wiring W4 corresponds to power supply line VCC.

  A region A8 on the right side of the gate electrode G4 in the active region D3 corresponds to the drain of the p-type MOS transistor Q1. Further, the region A9 on the left side of the gate electrode G5 in the active region D4 corresponds to the source of the p-type MOS transistor Q2. The regions A8 and A9 are connected to each other via a via (not shown) and metal wirings W5, W6, and W7.

  A region A10 on the right side of the gate electrode G5 in the active region D4 corresponds to the drain of the p-type MOS transistor Q2. Further, the region A11 on the right side of the gate electrode G6 in the active region D5 corresponds to the drain of the n-type MOS transistor Q3. The areas A3 and A4 are connected to each other via a via (not shown) and a metal wiring W8. A connection point between the regions A10 and A11 corresponds to the output terminal To in the switch elements (SE1 to SE4) of the first configuration example.

  A region A12 on the left side of the gate electrode G6 in the active region D5 corresponds to the source of the n-type MOS transistor Q3. Further, a region A13 on the right side of the gate electrode G4 in the active region D6 corresponds to the drain of the n-type MOS transistor Q1. The regions A12 and A13 are connected to each other via a via (not shown) and metal wirings W9, W10, and W11.

  A region A14 on the left side of the gate electrode G1 in the active region D6 corresponds to the source of the n-type MOS transistor Q4. This region A14 is connected to the metal wiring W12 through a via (not shown). The metal wiring W3 corresponds to the ground line VSS.

FIG. 14 is a plan view showing a structural example of the switch elements (SE1A to SE4A) of the second configuration example shown in FIG. 9 and FIG.
FIG. 14A shows an example in which two MOS transistors are formed in each of two active regions (D7, D8), and FIG. 14B shows four active regions (D9 to D12). An example in which one MOS transistor is formed for each is shown.

  In the structural example shown in FIG. 14A, active regions D7 and D8 are formed side by side on a semiconductor substrate. An n-type impurity is introduced into the active region D7, and a p-type impurity is introduced into the active region D8. The active regions D7 and D8 have a rectangular shape as shown in FIG. 14A, for example, and their sizes are substantially the same. An element isolation region is provided between the active regions.

  Gate electrodes G7 to G9 are provided on the active regions D7 and D8 via a gate oxide film (not shown).

  The gate electrode G7 is provided over the two active regions (D7, D8). A channel of the p-type MOS transistor Q7 is formed in a portion facing the gate electrode G7 in the active region D7. In the active region D8, the channel of the n-type MOS transistor Q8 is formed in the portion facing the gate electrode G7.

  The p-type MOS transistor Q7 and the n-type MOS transistor Q8 are transistors that constitute an inverter circuit that is inserted into the path on the input side of the switch elements (SE1A to SE4A). The gate electrode G7 corresponds to the input terminal of this inverter circuit.

The gate electrode G8 is provided on the active region D7 on the right side of the gate electrode G7 in the drawing. A channel of the p-type MOS transistor Q5 is formed in a portion facing the gate electrode G8 in the active region D7.
The gate electrode G9 is provided on the active region D8 on the right side of the gate electrode G7 in the drawing. In the active region D8, a channel of the n-type MOS transistor Q6 is formed in a portion facing the gate electrode G9.
The gate electrodes G8 and G9 correspond to terminals for inputting the control signal Sci or its logical inversion signal / Sci.

  A region A15 on the left side of the gate electrode G7 in the active region D7 corresponds to the source of the p-type MOS transistor Q7. This region A15 is connected to the metal wiring W13 through a via (not shown). Metal wiring W13 corresponds to power supply line VCC.

  A region A20 on the left side of the gate electrode G7 in the active region D8 corresponds to the source of the n-type MOS transistor Q8. This region A20 is connected to the metal wiring W15 via a via (not shown). Metal wiring W15 corresponds to power supply line VCC.

A region A16 sandwiched between the gate electrodes G7 and G8 in the active region D7 corresponds to the drain of the p-type MOS transistor Q7 and the source of the p-type MOS transistor Q5. A region A19 sandwiched between the gate electrodes G7 and G9 in the active region D8 corresponds to the drain of the n-type MOS transistor Q8 and the source of the n-type MOS transistor Q6.
The regions A16 and A19 are connected to each other via a via (not shown) and the metal wiring W14. The connection point between the regions A16 and A19 corresponds to the output terminal of the inverter circuit described above and also corresponds to the terminal on the signal input side in the switch elements (SE1A to SE4A) of the second configuration example.

  A region A17 on the right side of the gate electrode G8 in the active region D7 corresponds to the drain of the p-type MOS transistor Q5. In the active region D8, the region A18 on the right side of the gate electrode G9 corresponds to the drain of the n-type MOS transistor Q6. The regions A17 and A18 are connected to each other via a via (not shown) and a metal wiring W16. The connection point between the regions A17 and A18 corresponds to a terminal that outputs a signal in the switch elements (SE1A to SE4A) of the second configuration example.

In the structural example shown in FIG. 14B, four active regions D9, D10, D11, and D12 are formed in a matrix on a semiconductor substrate. In the example of FIG. 14B, the active region D11 is formed on the right side of the active region D9, the active region D10 is formed below the active region D9, the active region D12 is below the active region D11, and the active region D10. It is formed on the right side.
An n-type impurity is introduced into the active regions D9 and D11, and a p-type impurity is introduced into the active regions D10 and D12. The active regions D9 to D12 have a rectangular shape as shown in FIG. 14B, for example, and their sizes are substantially the same. An element isolation region is provided between the active regions.

  Gate electrodes G10 to G12 are provided on the active regions D9 to D12 via a gate oxide film (not shown).

The gate electrode G10 is provided over the active regions D9 and D10. A channel of the p-type MOS transistor Q7 is formed in a portion facing the gate electrode G10 in the active region D9. In the active region D10, the channel of the n-type MOS transistor Q8 is formed in the portion facing the gate electrode G10.
The gate electrode G10 corresponds to the input terminal of the inverter circuit configured by the p-type MOS transistor Q7 and the n-type MOS transistor Q8.

The gate electrode G11 is provided on the active region D11. A channel of the p-type MOS transistor Q5 is formed in a portion facing the gate electrode G11 in the active region D11.
The gate electrode G12 is provided on the active region D12. A channel of the n-type MOS transistor Q6 is formed in a portion facing the gate electrode G12 in the active region D12.
The gate electrodes G11 and G12 correspond to terminals for inputting the control signal Sci or its logical inversion signal / Sci.

  A region A21 on the left side of the gate electrode G10 in the active region D9 corresponds to the source of the p-type MOS transistor Q7. This region A21 is connected to the metal wiring W17 through a via (not shown). The metal wiring W17 corresponds to the power supply line VCC.

  A region A28 on the left side of the gate electrode G10 in the active region D10 corresponds to the source of the n-type MOS transistor Q8. This region A28 is connected to the metal wiring W19 via a via (not shown). The metal wiring W19 corresponds to the ground line VSS.

  A region A22 on the right side of the gate electrode G10 in the active region D9 corresponds to the drain of the p-type MOS transistor Q7. Further, a region A27 on the right side of the gate electrode G10 in the active region D10 corresponds to the drain of the n-type MOS transistor Q8. The regions A22 and A27 are connected to each other via a via (not shown) and a metal wiring W18. A connection point between the regions A22 and A27 corresponds to an output terminal of an inverter circuit configured by the p-type MOS transistor Q7 and the n-type MOS transistor Q8.

  A region A23 on the left side of the gate electrode G11 in the active region D11 corresponds to the source of the p-type MOS transistor Q5. Further, the region A26 on the left side of the gate electrode G12 in the active region D12 corresponds to the source of the n-type MOS transistor Q6. The regions A23 and A26 are connected to each other via a via (not shown) and a metal wiring W21. A connection point between the regions A23 and A26 corresponds to a terminal on a signal input side in the switch elements (SE1A to SE4A) of the second configuration example.

  Metal wirings W18 and W21 are connected via metal wiring W20. As a result, the output terminals of the inverter circuits (Q7, Q8) and the input terminals of the switch elements (SE1A to SE4A) are connected.

  A region A24 on the right side of the gate electrode G11 in the active region D11 corresponds to the drain of the p-type MOS transistor Q5. Further, the region A25 on the right side of the gate electrode G12 in the active region D12 corresponds to the drain of the n-type MOS transistor Q6. The areas A24 and A25 are connected to each other via a via (not shown) and a metal wiring W22. The connection point between the regions A24 and A25 corresponds to a terminal that outputs a signal in the switch elements (SE1A to SE4A) of the second configuration example.

In the switch elements (SE1A to SE4A) of the second configuration example shown in FIG. 14A, metal wiring is used to connect the regions A16 and A19 sandwiched between the gate electrode G7 and the gate electrodes G8 and G9. W14 and beer are provided. On the other hand, in the switch elements (SE1 to SE4) of the first configuration example shown in FIG. 13A, it is not necessary to connect the regions A2 and A5 sandwiched between the gate electrode G1 and the gate electrodes G2 and G3. Therefore, metal wiring and vias as shown in FIG.
Therefore, the switch elements (SE1 to SE4) of the first configuration example may have a smaller area than the circuit in which the inverter elements (Q7, Q8) are added to the switch elements (SE1A to SE4A) of the second configuration example. it can.

However, when each transistor is formed in a separate active region, the area of both does not change much, as can be seen from a comparison between FIGS. 13B and 14B.
Further, when the inverter circuits (Q7, Q8) are deleted and only the switch elements (SE1A to SE4A) of the second configuration example are used, the switch elements (SE1A to SE4A) of the second configuration example are the first configuration example. The area can be made smaller than the switch elements (SE1 to SE4). However, in this case, since the signal delay occurs due to the resistance component of the transmission gate circuit (Q5, Q6), the operation speed of the circuit is slower than when the switch elements (SE1 to SE4) of the first configuration example are used. .

  The switch elements included in the switch circuits SWAki and SWBki of the module selection unit 50 have been described above.

  The control unit 1 generates control signals Sc <b> 1 to Sc <b> 8 that control the operation of each switch circuit of the module selection unit 50 in accordance with a signal stored in the storage unit 3 or a signal input from the signal input unit 2.

  The control unit 1 is instructed to disconnect the modules in the nth column (n = 1,..., 9) from all the input / output units in the signal stored in the storage unit 3 or the signal input from the signal input unit 2. In this case, the following control signals Sc1 to Sc8 are output according to the value of the integer n.

[2 ≦ n ≦ 8]
In this case, the control unit 1 sets the control signals Sc1 to Sc (n−1) to the value “1”, and sets the control signals Scn to Sc8 to the value “0”.

  When the control signal Scn becomes “0”, the switch circuits SWA1n, SWA2n, SWA3n, and SWA4n are turned off, and when the control signal Sc (n−1) becomes the value “1”, the switch circuits SWB1 (n−1) and SWB2 (N-1), SWB3 (n-1), SWB4 (n-1) are turned off. As a result, the four modules belonging to the nth column are disconnected from all the input / output units.

  Further, when the control signals Sc1 to Sc (n−1) become the value “1”, the switch circuits SWA1p, SWA2p, SWA3p, SWA4p are turned on, and the switch circuits SWB1p, SWB2p, SWB3p, SWB4p are turned off (p is 1). (An integer up to (n-1) is shown). Thus, the four input / output units P1p, P2p, P3p, and P4p belonging to the p-th column are connected to the four modules M1p, M2p, M3p, and M4p belonging to the p-th column, respectively. That is, the input / output units in the first to (n−1) th columns are connected to the modules in the first to (n−1) th columns, respectively.

  On the other hand, when the control signals Scn to Sc8 have the value “1”, the switch circuits SWA1q, SWA2q, SWA3q, SWA4q are turned off, and the switch circuits SWB1q, SWB2q, SWB3q, SWB4q are turned on (q is an integer from n to 8). Show). As a result, the four input / output units P1q, P2q, P3q, and P4q belonging to the q-th column have four modules M1 (q + 1), M2 (q + 1), M3 (q + 1), and M4 belonging to the (q + 1) -th column, respectively. Connected to (q + 1). That is, the input / output units in the n-th column to the eighth column are connected to the modules in the (n + 1) -th column, respectively.

[N = 1]
In this case, the control unit 1 sets all of the control signals Sc1 to Sc8 to the value “0”.
As a result, the switch circuits SWA11, SWA21, SWA31, and SWA41 are all turned off, so that the modules belonging to the first column are disconnected from all the input / output units.
If 'i' is an integer from 1 to 8, the switch circuits SWA1i, SWA2i, SWA3i, SWA4i are turned off, and the switch circuits SWB1i, SWB2i, SWB3i, SWB4i are turned on. Thus, the four input / output units P1i, P2i, P3i, and P4i belonging to the i-th column respectively have four modules M1 (i + 1), M2 (i + 1), M3 (i + 1), and M4 belonging to the (i + 1) -th column. Connected to (i + 1). That is, the input / output units in the first column to the eighth column are connected to the modules in the second column to the ninth column, respectively.

[N = 9]
In this case, the control unit 1 sets all of the control signals Sc1 to Sc8 to the value “1”.
As a result, the switch circuits SWB18, SWB28, SWB38, and SWB48 are all turned off, so that the modules in the ninth column are disconnected from all the input / output units.
If 'i' is an integer from 1 to 8, the switch circuits SWA1i, SWA2i, SWA3i, SWA4i are turned on, and the switch circuits SWB1i, SWB2i, SWB3i, SWB4i are turned off. Therefore, the four input / output units P1i, P2i, P3i, and P4i belonging to the i-th column are connected to the four modules M1i, M2i, M3i, and M4i belonging to the i-th column, respectively. That is, the input / output units in the first column to the eighth column are connected to the modules in the first column to the eighth column, respectively.

In addition, when the signal stored in the storage unit 3 has a predetermined initial value, the control unit 1 generates control signals Sc1 to Sc8 according to the signal input from the signal input unit 2 and stores the control signals Sc1 to Sc8 in the storage unit 3. When the signal to be processed has a value different from the predetermined initial value, control signals Sc1 to Sc8 are generated according to the signal stored in the storage unit 3.
Thus, for example, in an initial state where no signal is written to the storage unit 3 (when a module is inspected, etc.), the control signal Sc1 according to a signal input to the signal input unit 2 from the outside of the semiconductor integrated circuit. Since ~ Sc8 can be generated, the connection between the input / output unit and the module can be arbitrarily controlled. Further, after the signal is written to the storage unit 3, the control signals Sc1 to Sc8 can be generated according to the written signal, so that the input / output unit and the module can be connected without inputting the signal from the outside. The connection can be fixed in a desired state.

  For example, as shown in FIG. 15, the control unit 1 includes a decoding unit 13, NOR circuits 11-2 to 11-8, and inverter circuits 11-1 and 12-1 to 12-8.

The decoding unit 13 decodes a signal input from the storage unit 3 or the signal input unit 2 and outputs the decoding result as instruction signals Sd1 to Sd8.
That is, when the decoding unit 13 is instructed to disconnect the module in the n-th column from all the input / output units in the signal stored in the storage unit 3 or the signal input from the signal input unit 2, the value of the integer n In response to this, the following instruction signals Sd1 to Sd8 are generated.
If “n” is an integer from 1 to 8, only the instruction signal Sdn is set to the value “1”, and the other instruction signals are set to the value “0”.
If “n” is an integer 9, the instruction signals Sd1 to Sd8 are all set to the value “0”.

  The instruction signal Sdi (i = 1,..., 8) output from the decoding unit 13 is a signal for instructing whether to disconnect the i-th module from all the input / output units. When the value of the instruction signal Sdi is “1”, the module selection unit 50 disconnects the modules in the i-th column from all the input / output units.

  When the signal stored in the storage unit 3 has the predetermined initial value described above, the decoding unit 13 generates the instruction signals Sd1 to Sd8 according to the signal input from the signal input unit 2. When the signal stored in the storage unit 3 has a value different from the predetermined initial value, the instruction signals Sd1 to Sd32 are generated according to the signal stored in the storage unit 3.

  The NOR circuit 11-j (j represents an integer from 2 to 8) is an inverted OR of the control signal / Sc (j-1) output from the inverter circuit 12- (j-1) and the instruction signal Sdj. And the calculation result is output as a control signal Scj.

  The inverter circuit 12-j logically inverts the control signal Scj and outputs it as the control signal / Scj.

The inverter circuit 11-1 logically inverts the instruction signal Sd1 and outputs it as the control signal Sc1.
The inverter circuit 12-1 logically inverts the control signal Sc1 and outputs it as the control signal / Sc1.

  When the instruction signal Sdj (j = 2,..., 8) of the decoding unit 13 becomes “1”, the NOR circuit 11-j to which the instruction signal Sdj is input outputs a control signal Scj having a value “0”. When “j” is smaller than 8, the control signal / Scj having the value “1” obtained by logically inverting the control signal Scj is input to the NOR circuit 11- (j + 1), and therefore the NOR circuit 11- (j + 1) also has the value “0”. 'Control signal Sc (j + 1) is output. In this way, the control signals Sc (j + 1) to Sc8 output from the NOR circuits 11- (j + 1) to 11-8 downstream from the NOR circuit 11-j all have the value '0'.

  When the instruction signal Sd1 of the decoding unit 13 becomes the value “1”, the control signal Sc1 obtained by logically inverting the instruction signal Sd1 becomes the value “0”, and the control signal / Sc1 obtained by further logically inverting this is the NOR circuit 11-2. And its output signal (control signal Sc2) has the value '0'. As a result, the values of the control signals Sc2 to Sc8 output from the NOR circuits 11-2 to 11-8 all become the value “0”. That is, when the instruction signal Sd1 has the value “1”, the control signals Sc1 to Sc8 all have the value “0”.

  On the other hand, when all the instruction signals (Sd1 to Sd8) of the decoding unit 13 have the value “0”, the input signals of the inverter circuit 11-1 and the NOR circuits 11-2 to 11-8 all have the value “0”. The control signals Sc1 to Sc8 all have the value “1”.

  Therefore, when the n-th column module is disconnected from all the input / output units, when “n” is an integer from 2 to 8, only the instruction signal Sdn is set to the value “1” by the decoding unit 13. Therefore, the control signals Sc1 to Sc (n−1) have the value “1”, and the control signals Scn to Sc8 have the value “0”. When ‘n’ is an integer 1, the instruction signal Sd1 is set to the value ‘1’ by the decoding unit 13, so that the control signals Sc1 to Sc8 all have the value ‘0’. When 'n' is an integer 8, the instruction signals Sd1 to Sd8 are all set to the value '0' by the decoding unit 13, so that the control signals Sc1 to Sc8 are all set to the value '1'.

The storage unit 3 stores a signal designating one column to be separated from all the input / output units among the nine columns of modules. In addition, the storage unit 3 stores a signal having a predetermined initial value in an initial state where writing is not performed.
The memory | storage part 3 can be comprised by a fuse element, a non-volatile memory, etc., for example.

  The signal input unit 2 is a circuit for inputting a signal designating one module row to be separated from all the input / output units. For example, in the case of inspecting a semiconductor integrated circuit, the control unit 1 is connected from an external device. It is used to input a signal.

  The power switch circuits PS <b> 1 to PS <b> 9 turn on or off the power of the modules for each column according to the signal output from the control unit 1. That is, the power supply of the module belonging to the row separated from all the input / output units is turned off.

  The power switch circuit PSi (i = 1,..., 8) is inserted in the common power supply line of the modules (M1i, M2i, M3i, M4i) belonging to the i-th column, and the instruction signal Sdi has the value “0”. Turns on in the case of, and turns off when the value is “1”. The instruction signal Sdi has a value of “1” when the module in the i-th column is disconnected from all the input / output units. In this case, the power supply to the module in the i-th column is cut off.

  The power switch circuit PS9 is inserted in the common power supply line of the modules (M19, M29, M39, M49) belonging to the ninth column, and is turned on when the control signal Sc8 has the value “0”, the value “1”. In case of off. The control signal Sc8 has a value of “1” when the module M9 is disconnected from all the input / output units. In this case, the power supply to the module M9 is cut off.

FIG. 16A shows an example of the configuration of the power switch circuit PSi (i = 1,..., 8).
For example, as shown in FIG. 16A, the power switch circuit PSi includes an n-type MOS transistor Qnh1, a p-type MOS transistor Qph1, and an inverter circuit U1.

In the p-type MOS transistor Qph1, its source is connected to the power supply line VCC, its drain is connected to the virtual power supply line V-VCC of the i-th column module, and an instruction signal Sdi is input to its gate.
As the p-type MOS transistor Qph1, a high-threshold type p-type MOS transistor having a smaller leakage current than a normal p-type MOS transistor in a semiconductor integrated circuit may be used.

The n-type MOS transistor Qnh1 has a source connected to the ground line VSS and a drain connected to the virtual ground line V-VSS of the i-th module.
As the n-type MOS transistor Qnh1, a high-threshold type n-type MOS transistor having a smaller leakage current than a normal n-type MOS transistor used in a semiconductor integrated circuit may be used.

  Inverter circuit U1 logically inverts the signal input to the gate of p-type MOS transistor Qph1 and inputs the inverted signal to the gate of n-type MOS transistor Qnh1.

According to the power switch circuit PSi shown in FIG. 16A, when the instruction signal Sdi has a value “0” (when a module belonging to the i-th column is connected to any input / output unit), the p-type MOS transistor A low level signal is input to the gate of Qph1 and a high level signal is input to the gate of the n-type MOS transistor Qnh1, and both of these transistors are turned on. Therefore, power is supplied to the modules belonging to the i-th column from the power supply line VCC and the ground line VSS.
On the other hand, when the instruction signal Sdi is “1” (when the module belonging to the i-th column is disconnected from all the input / output units), both the p-type MOS transistor Qph1 and the n-type MOS transistor Qnh1 are turned off, and the i-th column The power supply to the modules belonging to is cut off.

FIG. 16B is a diagram showing an example of the configuration of the power switch circuit PS9.
The power switch circuit PS9 has the same configuration as the power switch circuit PSi (i = 1,..., 8) shown in FIG. The power switch circuit PS8 is different from the power switch circuit PSi shown in FIG. 16A in that the control signal Sc8 is input instead of the instruction signal Sdi.
The control signal Sc8 becomes the value “0” when any of the instruction signals Sd1 to Sd8 becomes the value “1”. That is, a module belonging to any of the first to eighth columns is disconnected from all the input / output units, and instead a module belonging to the ninth column is connected to an input / output unit belonging to the eighth column The value becomes '0'. In this case, a low level signal is input to the gate of the p-type MOS transistor Qph1, and a high level signal is input to the gate of the n-type MOS transistor Qnh1, and both of these transistors are turned on. In addition, power is supplied from the ground line VSS.
On the other hand, the control signal Sc8 becomes the value “1” when all of the instruction signals Sd1 to Sd8 become the value “0”. That is, when the modules belonging to the first column to the eighth column are respectively connected to the input / output units and the modules belonging to the ninth column are separated from all the input / output units as redundant columns, the value becomes “0”. In this case, both the p-type MOS transistor Qph1 and the n-type MOS transistor Qnh1 are turned off, and the power supply to the modules belonging to the ninth column is cut off.

  Here, the defect relief operation in the semiconductor integrated circuit according to the present embodiment having the above-described configuration will be described with reference to FIGS.

FIG. 17 shows a default connection state before the defect inspection.
In the example shown in FIG. 17, the input / output units in the first column to the eighth column are connected to the modules in the first column to the eighth column, respectively, and the module in the ninth column is a redundant column.

FIG. 18 shows a connection state when the module M22 in the second row and second column has a defect.
In this case, the control unit 1 disconnects the second row of modules (M12, M22, M32, M42) including the module M22 from the second row of input / output units. The input / output units in the second column to the eighth column are connected to the modules in the third column to the ninth column, respectively. That is, the connection destination of each input / output unit shifts toward the redundant column (the ninth column). Thereby, the input / output unit of 4 rows and 8 columns is connected to the module of 4 rows and 8 columns excluding the second column including the defect one-to-one, and the defect of the module M22 is relieved.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, the power supply to the modules belonging to the column separated from the input / output unit is cut off, so that unnecessary power is consumed in the modules that do not contribute to the operation of the circuit. It can be prevented from being consumed. If a fault that causes a large current to flow through the power supply line occurs in the module, it can be cut off to prevent the influence on the power supply system and other circuits, effectively reducing yield loss due to the module fault be able to.

  In addition, since the power supplies of all modules belonging to the same column are controlled in common, the number of power switch circuits can be reduced as compared with the case where the power supplies of individual modules are controlled.

  Further, the connection state of all modules belonging to the same column is commonly controlled by the same control signal supplied from the control unit 1. As a result, the number of control signals can be greatly reduced as compared with the case where the connection state of each module with the input / output unit is controlled independently, and the circuit configuration of the control unit 1 can be simplified.

  In addition, when a failure is inspected, it is only necessary to inspect the presence or absence of a failure for each column, so that the inspection time can be shortened as compared with the case of inspecting individual modules.

  In addition, when information on a faulty module is written in a storage element such as a fuse constituting the storage unit 3, it is sufficient to write information on the presence / absence of a fault in a module set for each column. The time required can be shortened.

<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described.
The present embodiment relates to a method for manufacturing the above-described semiconductor integrated circuit.

  FIG. 19 is a diagram showing an example of a method for manufacturing the semiconductor integrated circuit shown in FIG.

Step ST101:
The circuit shown in FIG. 5 is formed on a semiconductor substrate.

Step ST202:
For example, in an external inspection device or the like, a signal specifying a row of modules to be disconnected from all input / output units is generated and input to the signal input unit 2.
In the storage unit 3 formed in step ST101, a signal having a predetermined initial value is stored because the writing process has not yet been performed. Therefore, in the control unit 1, the control signals Sc1 to Sc8 are generated so that the module specified by the signal input to the signal input unit 2 is disconnected from all the input / output units.

Step ST103:
The operation of the module currently connected to the input / output unit is inspected by an inspection method such as a scan path test.

Step ST104:
It is determined whether or not a defective module is detected in the inspection in step ST103.

Steps ST105, ST106, ST107:
If it is determined in step ST104 that a module having a defect is detected, and defective modules are detected in two or more columns in total including this, it is determined that the semiconductor integrated circuit currently being inspected is a defective product, and the processing is performed. The process ends (step ST107).
On the other hand, if there is still only one detected defective module, a signal designating the detected defective module as a module to be disconnected from all input / output units is supplied to the signal input unit 2 by the inspection device or the like (step (ST106) The inspection in step ST103 is performed again.

Step ST108:
When a module having a defect is not detected in step ST104, a signal designating a defective module to be disconnected from all the input / output units is written in the storage unit 3 in accordance with a signal input to the signal input unit 2 at that time. For example, when the storage unit 3 is composed of a fuse, a process for cutting the fuse is performed.
When a signal different from the initial value is written in the storage unit 3, the control unit 1 generates control signals Sc <b> 1 to Sc <b> 8 according to the signal stored in the storage unit 3. Thereby, the defective module determined to be defective in the inspection in step ST103 is separated from all the input / output units.

  When a defective module to be separated from all the input / output units is determined in step ST108, programming for the module having no defect becomes possible. For example, when a program memory is provided in each module, a process of writing data for setting the function of the module in these memories is performed.

  As mentioned above, although several embodiment of this invention was described, this invention is not limited only to said form, For example, the following various variations are included.

In the present invention, the module selection unit may connect the signal input terminals of the modules separated from all the input / output units to a wiring having a predetermined potential.
In the switch elements shown in FIGS. 7, 9, and 11, the output terminal To is in a high impedance state when turned off. Therefore, when the module is disconnected from all the input / output units, the signal input terminal of the module is in a high impedance state, and the potential becomes unstable. When power is supplied to the module in this state, a circuit inside the module operates in accordance with an unstable potential of the signal input terminal, so that useless power is consumed due to a through current or the like. Therefore, if the signal input terminals of the modules separated from all the input / output units as described above are connected to wiring of a predetermined potential, the potential of the signal input terminals can be stabilized, so that the power consumption due to the through current or the like is reduced. Increase can be prevented.

FIG. 20 is a diagram showing a configuration example of the module selection unit 50 to which a circuit for stabilizing the potential of the signal input terminal of each module is added in the semiconductor integrated circuit shown in FIG. In FIG. 20, only the portion related to the module in the first row is shown, but the same applies to the other rows.
The switch circuit SWCkn (k = 1,..., 4; n = 1,..., 9) is connected between the signal input terminal of the module kn and the ground line VSS, and the module Mkn is connected to all the input / output units. When disconnected, the signal input terminal is connected to the ground line VSS.
The switch circuit SWCki (i = 1,..., 32) is turned on when the instruction signal Sdi has a value “1”, that is, when the module Mi is disconnected from all the input / output units, and turned off in other cases. The switch circuit SWCk9 is turned on when the control signal Sc8 is “1”, that is, when the modules in the ninth column are disconnected from all the input / output units, and turned off in other cases.

  All of the semiconductor integrated circuits described above may be formed on the same semiconductor chip, or may be divided into a plurality of semiconductor chips by using a technique such as SIP (system in package).

  In the above-described embodiment, a CMOS type semiconductor integrated circuit is mainly exemplified, but the present invention is not limited to this. For example, the present invention can be applied to an integrated circuit composed of various circuit elements such as bipolar transistors.

  The numerical values (the number of modules, the number of input / output units, the number of module blocks, the number of rows, the number of columns, etc.) specifically shown in the above-described embodiments are examples, and can be appropriately changed to arbitrary numerical values.

1 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a first embodiment. FIG. 2 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 1. It is a figure which shows an example of a structure of the semiconductor integrated circuit which concerns on 3rd Embodiment. FIG. 4 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 3. It is a figure which shows an example of a structure of the semiconductor integrated circuit which concerns on 4th Embodiment. It is a figure which shows an example of a structure of a module. It is a figure which shows the 1st structural example of the switch element which turns on / off the signal transmitted to a module from an input-output part. It is a figure which shows the 1st structural example of the switch element which turns on / off the signal transmitted to an input-output part from a module. It is a figure which shows the 2nd structural example of the switch element which turns on / off the signal transmitted to a module from an input-output part. It is a figure which shows the 2nd structural example of the switch element which turns on / off the signal transmitted to an input-output part from a module. It is a figure which shows the 3rd structural example of the switch element which turns on / off the signal transmitted to a module from an input-output part. It is a figure which shows the 3rd structural example of the switch element which turns on / off the signal transmitted to an input-output part from a module. It is a top view which shows the structural example of the switch element of the 1st structural example shown in FIG.7 and FIG.8. It is a top view which shows the structural example of the switch element of the 2nd structural example shown in FIG.9 and FIG.10. It is a figure which shows an example of a structure of a control part. It is a figure which shows an example of a structure of a power switch circuit. 6 shows a default connection state of the semiconductor integrated circuit shown in FIG. FIG. 6 is a diagram showing an example of defect relief in the semiconductor integrated circuit shown in FIG. 5. FIG. 6 is a diagram showing an example of a manufacturing method of the semiconductor integrated circuit shown in FIG. 5. It is a figure which shows the structural example of the module selection part provided with the switch circuit for connecting a signal input terminal to wiring of predetermined electric potential.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control part, 13 ... Decoding part, 2 ... Signal input part, 3 ... Memory | storage part, 50 ... Module selection part, 100 ... General circuit block, M11-M19, M21-M29, M31-M39, M41-M49 ... Module , P11 to P18, P21 to P28, P31 to 38, P41 to P48, input / output unit, SWA11 to SWA18, SWA21 to SWA28, SWA31 to SWA38, SWA41 to SWA48, SWB11 to SWB18, SWB21 to SWB28, SWB31 to SWB38, SWB41 ~ SWB48 ... switch circuit, PS1 to PS9 ... power switch circuit, Q1, Q2, Q5, Qph1 ... p-type MOS transistor, Q3, Q4, Q6, Qnh1 ... n-type MOS transistor

Claims (7)

A plurality of modules arranged in a matrix of M rows (N + 1) columns (M and N are integers greater than 1), and can be substituted for each other in the same row ;
M rows and N have multiple output section matrix arranged in columns, and a circuit block column of the input-output portion are alternately arranged in columns and rows of the module,
In response to a control signal input, select the module of M rows and N columns except for the first column from the module of the M rows (N + 1) columns, each module of the selected M rows and N columns, the M rows N An input / output unit adjacent to one side in the row direction and the input / output unit adjacent to the other side in the row direction are connected to the input / output unit adjacent to one side in the row direction via the first switch circuit. A module selector that connects 1: 1 via a second switch circuit ;
Comprising
Each of the first switch circuit and the second switch circuit is
In the case of having a terminal for inputting a signal from the input / output unit and a terminal for outputting a signal to the module and being set to ON by the control signal, the signal input to the input terminal is logically inverted to When output from an output terminal and set to off by the control signal, at least one first inverter circuit that places the output terminal in a high impedance state;
A terminal for inputting a signal from the module and a terminal for outputting a signal to the input / output unit, and when turned on by the control signal, the signal input to the input terminal is logically inverted to When output from an output terminal and set to off by the control signal, at least one second inverter circuit that places the output terminal in a high impedance state;
A semiconductor integrated circuit. The first inverter circuit and the second inverter circuit are:
A first conductivity type first transistor and a second transistor connected in series between a first power supply line and the output terminal;
A second conductive type third transistor and a fourth transistor connected in series between a second power supply line and the output terminal;
In accordance with a signal input to the input terminal, one of the first transistor and the fourth transistor is driven on and the other is turned off.
In response to the control signal, both the second transistor and the third transistor are driven on or both are driven off.
The semiconductor integrated circuit according to claim 1 . A control unit that generates a control signal of the module selection unit so as to select a module of M rows and N columns excluding a column including a failed module from the modules of the M rows (N + 1) columns;
The semiconductor integrated circuit according to claim 1 or 2. N number of input and output sections belonging to the same row are arranged at equal intervals,
Each input / output unit is disposed at a position where the distance to the module adjacent to one side in the row direction is equal to the distance to the module adjacent to the other side in the row direction .
The semiconductor integrated circuit according to claim 3 . A plurality of modules arranged in a matrix of M rows (N + 1) columns (M and N are integers greater than 1), and can be substituted for each other in the same row ;
M rows and N have multiple output section matrix arranged in columns, and a circuit block column of the input-output portion are alternately arranged in columns and rows of the module,
In response to a control signal input, the M rows (N + 1) n-th from the column module (n is from 1 (N + 1) represents an integer of up to) selecting a module M rows and N columns except for the columns of The selected modules of M rows and N columns are connected to the M rows and N columns of the input / output units adjacent to one side in the row direction in a 1: 1 manner via the first switch circuit. Or an input / output unit adjacent to the other side in the row direction and a module selection unit connected to the first switching circuit via the second switch circuit ;
Is inserted into one of the power supply lines provided for each column of the module and (N + 1) pieces of the power switch circuit,
A control unit for outputting N control signals instructing to disconnect the nth column of modules from all input / output units to the N columns of the module selection unit in a ratio of 1: 1;
Comprising
When the control unit instructs to disconnect the nth column of modules from all input / output units,
If n is an integer from 2 to N, the first to (n−1) th control signals to be output to the first to (n−1) th module selector columns are and sets to a value of 1, it sets the n-th said control signal from the n-th output from the n th row of the n th the module selection unit to the second value,
If n is an integer 1, all of the N control signals are set to the second value,
If n is an integer (N + 1), all of the N control signals are set to the first value,
The module selection unit is configured to disconnect the nth column of modules from all input / output units based on the N control signals.
If an integer n is from 2 to N, on the (n-1) -th of said first switching circuit from the first row, the N-th of the first switching circuit from the n-th row together make off, the (n-1) -th of the second switching circuit off, to turn on the n-th of the second switching circuit from the n-th row from the first row,
If n is an integer 1, with causing off all of the first switch circuit turns on all of the second switch circuit,
If n is an integer (N + 1), together with the cause on all of the first switching circuit performs an operation to turn off all of the second switch circuit,
Of the (N + 1) power switch circuits, the power switch circuit inserted in the power supply line of the nth column of the module can disconnect the nth column of the module from all input / output units. off when instructed, the (N + 1) -th power supply switch circuit is inserted in the power supply line of the row of modules, Ru Ofusu when the N-th said control signal is of said first value
Semiconductors integrated circuits. Modules from 1st row to the j-th (j is an integer of from 2 to N) has a first function,
The (j + 1) th to (N + 1) th modules in each row have a second function including the first function,
The control unit selects a module of M rows and N columns excluding any one column from the (j + 1) th column to the (N + 1) th column when all the modules of the M row (N + 1) column operate normally. Generating a control signal for the module selection unit,
The semiconductor integrated circuit according to claim 5 . A plurality of modules arranged in a matrix of M rows (N + 1) columns (M and N are integers greater than 1), and can be substituted for each other in the same row ;
M rows and N have multiple output section matrix arranged in columns, and a circuit block column of the input-output portion are alternately arranged in columns and rows of the module,
In response to a control signal input, select the module of M rows and N columns except for the first column from a plurality of modules of the M rows (N + 1) columns, each module of the selected M rows and N columns, the M Among the input / output units in the row N column, the input / output unit adjacent to one or the other side in the row direction and the module selection unit connected 1: 1 .
A storage unit for storing a signal designating a module of one column to be separated from the input / output unit of M rows and N columns ;
A signal input unit for inputting a signal specifying a module of one column to be separated from the input / output unit of M rows and N columns ;
A control unit that generates a control signal of the module selection unit so as to select a module of M rows and N columns excluding a column including a failed module from the modules of the M rows (N + 1) columns ;
Comprising
When a signal having a predetermined initial value is stored in the storage unit, the control unit generates the control signal according to a signal input to the signal input unit, and the storage unit is different from the initial value. A semiconductor integrated circuit that generates the control signal in accordance with a signal stored in the storage unit when a signal having a value is stored.

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