JP4826352B2 - Frame timing phase difference correction method and apparatus - Google Patents

Description

  The present invention relates to a frame timing phase difference correction method and a frame timing phase difference correction apparatus, and more particularly to a frame timing phase difference correction method for matching the phase of a frame timing of a transmission signal with the phase of a frame timing of a reception signal in a mobile terminal of a mobile radio system. And a frame timing phase difference correction apparatus.

  Conventionally, as a device for adjusting the frame timing of received data to the frame timing in the receiving device, a frame timing obtained by detecting the phase difference between the received frame timing and the reference frame timing in the receiving device and shifting the received frame timing by the phase difference. There is a device for transferring received data to (see Patent Document 1).

  FIG. 1 shows a configuration example of another conventional frame timing phase difference correction apparatus.

  In FIG. 1, 101 indicates a phase difference detection unit, 102 indicates a phase difference detection result storage unit, and 103 indicates a frame timing generation unit.

The phase difference detection unit 101 detects the phase difference between the frame timing input S _in and the frame timing output S _out and stores the detected phase difference in the phase difference detection result storage unit 102. Based on the stored phase difference, the frame timing generation unit 103 delays the signal branched from the frame timing input S _in . This signal processing step is repeated until the output of the phase difference detection unit 101 becomes zero. That is, conventionally, the period for correcting the phase difference of the frame timing output S _out (hereinafter referred to as the correction period) and the number of clocks to be corrected by one correction (hereinafter referred to as the number of corrected clocks) are variable in accordance with the magnitude of the phase difference. The correction process was always performed with a fixed phase difference period and the number of correction clocks.

  FIG. 2 is a time chart showing the timing of conventional frame timing phase difference correction.

At the time <1>, there is no phase difference between the frame timing input S _in and the post-phase correction frame timing output S _out , and the frame timings match.

At time <2>, the frame timing input S _in fluctuates and changes by −2 clocks, so that the phase difference from the post-phase correction frame timing output S _out becomes −2 clocks per basic frame period.

At the time <3>, the post-phase correction frame timing output S _out is corrected by −1 clock, resulting _in a phase difference of −1 clock with respect to the frame timing input S _in .

In time <4>, further is -1 clock correction, phase corrected frame timing output S _out of phase becomes 0 clock to the phase of the frame timing input S _in, the frame timing of the input and output match correction Is completed.
JP-A-9-135236

  The background art of Patent Document 1 described above is the reproduction of the reception frame timing used for the signal processing of the reception unit, and responds as it is even when the reception frame timing changes abnormally greatly. When used as a transmission frame timing, there is a disadvantage that an error occurs in transmission data.

In the frame timing phase difference correction apparatus in the background art shown in FIG. 1, the correction cycle and the number of correction clocks are not changed in accordance with the magnitude of the phase difference, but processing is always performed in a fixed manner. When the phase of the frame timing input S _in changes greatly, there is a problem that it takes time to repeat the process until the phase of the output frame timing output S _out after phase correction matches the phase of S _in . .

  For example, when the correction cycle is 20 msec (corrected every 8 frames with a reference frame cycle of 2.5 msec) and the number of correction clocks is 1, the time until the phase difference correction processing is completed when the phase difference is 50 clocks. Takes 20 msec × (50 ÷ 1) = 1000 msec.

  Accordingly, one of the objects of the present invention is to correct the phase difference of the frame timing of the transmission signal with respect to the frame timing of the received signal at the mobile terminal with an appropriate amount of change, and to reduce the time until the correction is completed. To provide a phase difference correction method and a frame timing phase difference correction apparatus.

    The present invention is not limited to the above-described object, and the effects derived from the respective configurations shown in the best mode for carrying out the invention to be described later and which cannot be obtained by conventional techniques are another object of the present invention. Can be positioned as

(1) In the present invention, there is provided a frame timing phase difference correction method for correcting a phase difference between frame timings of a transmission signal and a reception signal, and a period that is an integral multiple of a frame period is used as the correction period for performing the correction. A plurality of steps corresponding to each other, a step of setting a plurality of clocks corresponding to the phase difference as a correction amount for performing the correction, and the correction cycle corresponding to the phase difference detected for each frame cycle Selecting the correction amount corresponding to the phase difference detected for each frame period, and selecting the frame of the transmission signal based on the selected correction amount for each selected correction period. A frame timing phase difference correction method including a step of correcting a timing phase.
(2) In the present invention, a frame timing phase difference correction apparatus that corrects a phase difference between frame timings of a transmission signal and a reception signal, wherein a period that is an integral multiple of a frame period is set as the phase difference as a correction period for performing the correction. A plurality of correction cycle storage units corresponding to each other, a phase difference detection unit that detects a phase difference between frame timings of the transmission signal and the reception signal for each frame cycle, and a frame cycle based on the detected phase difference A correction cycle selection unit that selects the correction cycle every time, and a frame timing generation unit that corrects and outputs the frame timing phase of the transmission signal with a predetermined correction amount for each of the selected correction cycles. A frame timing phase difference correction apparatus characterized by the above is used.

  Preferably, the phase difference detection unit and the frame timing generation unit have a function capable of setting an operating frame period from the outside, and use the frame timing phase difference correction apparatus according to claim 2.

The frame timing phase difference correction device according to claim 2, wherein the correction cycle storage unit has a function of storing the plurality of correction cycles by controlling from the outside.
(3) Further, the frame timing phase difference correction device may include a correction amount storage unit that stores a plurality of clocks corresponding to the phase difference as the correction amount, and a phase difference detected for each frame period. A correction amount selection unit that selects a correction amount, and a frame timing generation unit that corrects and outputs the frame timing phase of the transmission signal with the selected correction amount for each of the selected correction periods. The frame timing phase difference correction apparatus according to claim 2 is used.
(4) The frame timing phase difference correction apparatus according to claim 3, wherein the correction cycle storage unit has a function of storing the plurality of correction cycles by controlling from the outside.
(5) The frame timing phase difference correction according to claim 3, wherein the phase difference detection unit has a function of invalidating the phase difference when the phase difference exceeds a predetermined value. Use the device.

  4. The frame timing phase difference correction apparatus according to claim 3, wherein the phase difference detection unit has a function of storing a phase difference that invalidates the phase difference from outside.

  According to the present invention, a frame timing phase difference correction method and a frame timing level for correcting a phase difference of a frame timing of a transmission signal with respect to a frame timing of a reception signal with an appropriate change amount in a mobile terminal and shortening a time until the correction is completed. A phase difference correction apparatus can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Example 1
In the first embodiment, the correction period is determined in accordance with the phase difference between the input frame timing and the output frame timing, and the output frame timing phase is corrected.

  FIG. 3 shows the configuration of the frame timing correction apparatus according to the first embodiment, and FIG. 4 shows the detailed configuration of the frame timing correction apparatus.

In FIG. 3, reference numeral 301 denotes a phase difference detection unit, 302 denotes a phase difference detection result storage unit, 303 denotes a phase difference correction control unit, and 304 denotes a frame timing generation unit.
4, 301-1 is a frame counter, 301-2 is a latch, 302-1 is a register, 303-1 is a selector, 304-1 is a correction period counter, 304-2 is a frame counter, and 304-3 is a decoding unit. , 304-4 respectively indicate selectors.

  FIG. 5 shows the timing and data example of each part in the first embodiment.

In FIG. 5, D501 is a frame timing input S _in , D502 is phase difference information a, D503 is an accumulated phase difference amount b, D504 is a correction cycle counter value, D505 is a flag d, D506 is a correction amount e, D507 is positive / negative information, D508 is a select signal f, D509 is a frame timing output S _out after phase difference correction, T _i1 is a frame _in which the frame timing input S _in is changed by −20 clocks with respect to the frame timing output S _out after phase difference correction, and T _i2 Is the frame changed by -30 clocks, t _c1 is the time when the correction cycle counter 304-1 starts counting, t _c2 is the time when the correction cycle counter 304-1 finishes counting one correction cycle, and performs phase correction of -1 clock. _{time, T o1} the phase difference after correction frame timing output _{S out} -1 clocks of the phase corrected received basic frame cycle respectively.

The frame timing input S _in in FIGS. 3 and 4 is a signal obtained by extracting the frame timing from the data signal received by the mobile terminal from the radio base station, and faithfully reproduces the change in the frame timing due to the state of the propagation path. .

  The frame timing of the uplink data signal transmitted from the mobile terminal to the base station is synchronized with the frame timing of the downlink data signal received by the mobile terminal. However, if the received frame timing changes greatly, It is necessary to correct and synchronize with a frame timing phase correction amount that does not cause a data error in the line.

  The outline of the operation in the first embodiment will be described with reference to FIG.

The phase difference correction apparatus according to the first embodiment illustrated in FIG. 3 includes a phase difference detection unit 301 that detects the phase difference between the phase of the frame timing input S _{in and} the phase of the frame timing output S _out , and the detected phase difference. A phase difference detection result storage unit 302 to be stored, a phase difference correction control unit 303 that selects and controls one of a plurality of correction periods according to the magnitude of the phase difference, and a phase difference is corrected at the selected correction period. A frame timing generation unit 304 that selects and outputs the selected frame timing.

Detailed operation of the first embodiment will be described with reference to FIGS.
The frame counter 301-1 in the phase difference detection unit 301 is triggered at the very beginning of the frame timing input S _in and counts a reference clock (not shown) in the mobile terminal, and outputs a frame timing output S after phase difference correction. _The number of clocks “a” latched by the latch 301-2 by “ _out” is output as phase difference information.
When the frame timing input S _in fluctuates, the counter value latched by the latch 301-1 changes, and the counted clock number a changes and is output as phase difference information.

In the frame of T _i1 in D501 in FIG. 5, the phase difference information a is −20 clocks compared to the output frame timing, and in the next frame T _i2 , the phase difference information a is −30 clocks. Is stored in the phase difference detection result storage 302.

  The phase difference information a stored in the phase difference detection result storage unit 302 is calculated by the phase difference amount b accumulated in the register 302-1 and sent to the phase difference correction control unit 303. The phase difference correction control unit 303 selects a correction cycle value c stored in advance in the selector 303-1 based on the received accumulated phase difference amount b. The selector 303-1 stores a plurality of correction cycle values in advance.

  For example, when the accumulated phase difference amount b (hereinafter absolute value) is 1 to 10 clocks, the correction period is 8 frames, when the accumulated phase difference amount b is 11 to 20 clocks, the correction phase is 7 frames, and the accumulated phase difference amount is 10 As the value increases, the correction cycle is decreased by one frame. When the accumulated phase difference amount b is 71 to 80, the correction cycle is set to one frame.

The sign of the accumulated phase difference amount b is provided to the decoding unit 304-3 as positive / negative information.
In the example shown in FIG. 5, since the accumulated phase difference amount b is −50 clocks, the selector 303-1 selects 4 frames as the correction cycle c.

In the frame timing generation unit 304, the correction cycle counter 304-1 is loaded with the value c selected by the selection function of the selector 303-1, and in this case, the correction cycle is set to 4 frames. The correction cycle counter 304-1 starts counting frames from time t _{c1 in} FIG. 5 and in this case, since it is 4 frames, as shown in FIG. 5, c (h), d (h), e (h), f ( h) and counts up the frame, the time t _c2 which completed counting the 4 th frames and the time of the corrected outputs a flag d to the decoding unit 304-3.

  The decoding unit 304-3 uses the positive / negative information and the correction flag d to generate a signal f for selecting a frame timing signal from the frame counter 304-2, and outputs the signal f to the selector 304-4.

Frame counter 304-2 loads the phase difference corrected frame timing output S _out, is successively delayed by a reference clock (not shown), and outputs a plurality of delayed frame timing signal in parallel. The initial value of the frame counter 304-2 is set by loading the frame timing input S _in, the phase of the frame timing of the frame counter 301-1 and correction cycle counter is combined.

In FIG. 4, the frame counter 304-2 outputs a total of nine frame timing signals with different phase delays, which are obtained by delaying the loaded post-phase-difference corrected frame timing output S _out from −4 clock to +4 clock.

  The decoding unit 304-3 designates the values 1 to 9 of the selection signal f corresponding to the correction amount of the frame timing phase difference from -4 clocks to +4 clocks, and f = 1 is the phase difference correction value of -4 clocks. In the following, f is increased to −3 clock, −2 clock,..., And f = 9, and a reference for phase difference correction of +4 clock is provided. The decoding unit 304-3 designates f = 5 when there is no phase difference correction, but in the case of the first embodiment, the correction amount is set to −1 clock, and f = 4 is designated and output to the selector 304-4.

The selector 304-4, from the parallel output of the frame counter 304-2, and select the frame-timed ring signal corresponding to the selection signal f = 4, and outputs a phase difference corrected frame timing output _{S out.}

In FIG. 5, in the first correction at time t _c2 , the accumulated phase difference amount b of D503 is improved from −50 clock to −49 clock, but the phase difference still remains. Repeat until quantity b is zero. The time when the accumulated phase difference amount b becomes 0 is when the phase of the frame timing input S _in and the phase difference corrected frame timing output S _out coincide.

  The frame counter 304-2 is a counter for two basic frame periods because both the plus and minus corrections are required for the basic frame period.

When the phase of the frame timing input S _in is shifted by −50 clocks, the time until the phase difference correction is completed in the conventional technique and the technique of the present invention is compared.

  Assuming that the basic frame period is 2.5 msec and the correction period is every 8 frames, the correction period is 2.5 msec × 8 = 20 msec and the number of phase difference correction clocks is 1. 20 msec × (50 ÷ 1) = 1000 msec. On the other hand, in the present invention according to the first embodiment, since the basic frame period is 2.5 msec and the correction period is selected every 4 frames, the correction period is 2.5 msec × 4 = 10 msec and the number of phase difference correction clocks is 1. The time required to complete the correction of the phase difference is 10 msec × (50 ÷ 1) = 500 msec, which is shortened to ½ compared to the prior art.

  In the above description, the frame period operates with a predetermined fixed value. However, the frame period is variable and can be set from the outside in order to cope with a case where the system is changed. FIG. 6 shows the configuration of a phase difference correction apparatus with variable frame period.

  In FIG. 6, the same components as those in FIG. 3 are given the same numbers. The difference from FIG. 3 is that the frame period setting signal is supplied to the phase difference detection unit 301 and the frame timing generation unit 304, and the phase difference correction device It is set so that it can cope with different frame periods. The phase difference correction apparatus in FIG. 6 operates similarly to the operation described in FIG. 3 when the frame period is set to a predetermined value.

In the selector 303-1 in FIG. 3, one correction cycle is selected from n types, but control may be performed so that the value of the n correction cycles can be set and changed from the outside.
(Example 2)
In the second embodiment, the correction period and the number of correction clocks are determined corresponding to the phase difference between the input frame timing and the output frame timing, and the output frame timing phase is corrected.

  FIG. 7 shows a detailed configuration of the frame timing correction apparatus according to the second embodiment.

  7, the same components as those in FIG. 4 are denoted by the same reference numerals, and 303-2 indicates a selector.

  FIG. 7 differs from FIG. 4 in that a phase difference correction control unit 303 has a selector 303-2 that stores a plurality of correction clock numbers and selects one of them based on the phase difference. In other words, the second embodiment is configured to control the number of correction clocks as variable.

  The operation of the second embodiment shown in FIG. 7 will be described as different from the first embodiment.

  In the second embodiment, one of the correction clock numbers stored in advance in the selector 303-2 corresponding to the accumulated phase difference amount b in FIG. 7 is selected, and the selected correction clock number e is sent to the decoding unit 304-3. Output.

  The decoding unit 304-3 generates a signal f for selecting one of a plurality of frame timing signals output from the frame counter 304-2, using the positive / negative information, the correction flag d, and the correction clock number e. To the selector 304-4.

Frame counter 304-2 loads the phase difference corrected frame timing output S _out, is successively delayed by a reference clock (not shown), and outputs a frame timing signal each delay in parallel. Initial value output of the frame counter 304-2 is set by loading the frame timing input S _in, the phase of the frame timing of the frame counter 301-1 and correction cycle counter is combined.

In FIG. 7, the frame counter 304-2 outputs a total of nine frame timing signals with different phase delays obtained by delaying the loaded phase difference corrected frame timing output S _out from −4 clock to +4 clock.

  The decoding unit 304-3 designates the values 1 to 9 of the selection signal f corresponding to the correction amount of the frame timing phase difference from -4 clocks to +4 clocks, and f = 1 is the phase difference correction value of -4 clocks. In the following, f is increased to −3 clock, −2 clock,..., And f = 9, and a reference for phase difference correction of +4 clock is provided. The decoding unit 304-3 designates f = 5 when there is no phase difference correction.

  In the example shown in FIG. 7, since the accumulated phase difference amount b is −50 clocks in the example shown in FIG. 7, the selector 303-1 selects 4 frames as the correction cycle c according to the same selection criteria as described in the first embodiment. To do.

  In the second embodiment, the number of correction clocks can be made variable in accordance with the accumulated phase difference amount b. In the example shown in FIG. When the accumulated phase difference amount b is reduced, the number of correction clocks is reduced to -2 clocks, so that f = 3 is output to the selector 304-4.

The selector 304-4 selects a frame timing signal corresponding to f input from the parallel outputs of the frame counter 304-2, and outputs it as an output S _out after phase difference correction.

  FIG. 8 shows the timing and data example of each part in the second embodiment.

  In FIG. 8, the same components as those in FIG.

In the first correction in FIG. 8, the accumulated phase difference amount b of D503 is improved from −50 clock to −46 clock at time t _c2 , but the phase difference still remains. The process is repeated until the phase difference b becomes zero. However, as the accumulated phase difference amount b decreases, the correction period is changed according to the selection criterion. Also, at the final stage of the repetition, the number of correction clocks is reduced and set so that the phase difference is exactly zero.

  FIG. 9 shows an example of the number of corrections, the correction cycle, the number of correction clocks, the amount of accumulated phase difference after correction, and the correction time in the second embodiment.

The time when the corrected accumulated phase difference amount b becomes 0 is when the phase difference between the frame timing input S _in and the post-phase difference corrected frame timing output S _out disappears.

When the phase of the frame timing input S _in is shifted by −50 clocks, the time until the phase difference is completely corrected is compared between the conventional technique and the technique of the present invention.

  Assuming that the basic frame period is 2.5 msec and the correction period is every 8 frames, the correction period is 2.5 msec × 8 = 20 msec and the number of phase difference correction clocks is 1. 20 msec × (50 ÷ 1) = 1000 msec. On the other hand, in the present invention according to the second embodiment, as shown in FIG. 9, the correction cycle and the number of correction clocks are controlled according to the accumulated phase difference amount b before correction. As a result, the total correction time is 195 msec, which indicates that the correction time is significantly shortened compared with the conventional technique of 1000 msec.

  In the selector 303-2 of FIG. 7, one correction clock number is selected from n types. However, the value of the n correction clock numbers may be externally set and controlled.

Also, the values of the frame period and the phase correction period may be controlled by changing the setting from the outside as in the first embodiment.
(Example 3)
In the third embodiment, reception is invalidated when the phase difference between the frame timing input S _in and the post-phase-correction frame timing output S _out is equal to or greater than a predetermined phase difference amount, and the abnormal post-phase-correction frame timing output S _out is invalidated. Is to be prevented.

  FIG. 10 shows the configuration of the frame timing correction apparatus according to the third embodiment.

  10, the same components as those in FIG. 3 are denoted by the same reference numerals, and 1001 represents a phase difference detection unit.

FIG. 10 differs from FIG. 3 in that a phase difference detection unit 1001 receives a receivable range input ΔC, and the phase difference detection unit 1001 uses the receivable range input ΔC to invalidate reception. to determine _in.

FIG. 11 shows an example in which the frame timing input S _in falls outside the receivable range _{in the} third embodiment.

In FIG. 11, T ₁ , T ₂ , and T ₃ indicate the time of one basic frame of the frame timing output S _out after phase correction, and the frame timing input S _in is ± ΔC for each of T ₁ , T ₂ , and T _3. The receivable range of the width is set.

D ₁ , D ₂ , and D ₃ indicate frame timing inputs S _in, which are input at times T _a , T _b , and T _c , respectively.

At the time of normal reception, the time of one basic frame of the frame timing output S _out after the phase difference correction has a substantially constant timing period as shown by T ₁ , T ₂ , and T ₃ in FIG.

In the example of FIG. 11, the time T _a and T _b of the frame timing inputs D _{1 and} D ₂ are within the receivable range, but the time T _c of the frame timing input D ₃ is outside the receivable range, so that the phase difference is detected. The unit 1001 determines that reception is invalid. Received for the frame-timed ring input D ₃ that is determined to be invalid, the phase difference information a frame timing is outputted to the phase difference detection result storage section 302 as 0, abnormal phase difference information is removed.

The subsequent operations are the same as those in the second embodiment, and the phase difference correction is performed on the frame timing input S _in within the receivable range until the phase difference from the post-phase correction frame timing output S _out becomes zero. Is called.

  In the above description, the receivable range ΔC is fixed after the initial setting. However, as shown in FIG. 10, the receivable range ΔC may be controlled to be changeable from the outside.

According to the third embodiment, it is possible to prevent the influence of abnormal frame timing reception due to propagation between the radio base station and the mobile terminal. As a result, it is possible to prevent an uplink transmission data error of the mobile terminal using the output of the phase difference correction apparatus.
(Appendix 1)
A frame timing phase difference correction method for correcting a phase difference between frame timings of a transmission signal and a reception signal,
Setting a plurality of periods that are integral multiples of the frame period as the correction period for performing the correction in correspondence with the phase difference;
Setting a plurality of clocks corresponding to the phase difference as a correction amount for performing the correction;
Selecting the correction period corresponding to the phase difference detected for each frame period;
Selecting the correction amount corresponding to the phase difference detected for each frame period;
Correcting the phase of the frame timing of the transmission signal based on the selected correction amount for each selected correction period;
A frame timing phase difference correction method comprising:
(Appendix 2)
A frame timing phase difference correction apparatus that corrects a phase difference between frame timings of a transmission signal and a reception signal,
A correction cycle storage unit that stores a plurality of cycles that are integer multiples of a frame cycle in association with the phase difference as a correction cycle for performing the correction;
For each frame period, a phase difference detection unit that detects a phase difference between frame timings of the transmission signal and the reception signal;
A correction cycle selection unit that selects the correction cycle for each frame cycle based on the detected phase difference;
A frame timing generator for correcting the frame timing phase of the transmission signal with a predetermined correction amount for each selected correction period; and
A frame timing phase difference correction apparatus comprising:
(Appendix 3)
3. The frame timing phase difference correction apparatus according to appendix 2, wherein the phase difference detection unit and the frame timing generation unit have a function of setting an operating frame period from the outside.
(Appendix 4)
3. The frame timing phase difference correction apparatus according to appendix 2, wherein the correction cycle storage unit has a function of storing the plurality of correction cycles by controlling from the outside.
(Appendix 5)
The frame timing phase difference correction device,
A correction amount storage unit that stores a plurality of clock numbers corresponding to the phase difference as the correction amount;
A correction amount selection unit that selects the correction amount based on the phase difference detected for each frame period;
A frame timing generator for correcting and outputting a frame timing phase of a transmission signal with the selected correction amount for each selected correction period;
The frame timing phase difference correction apparatus according to appendix 2, characterized by comprising:
(Appendix 6)
6. The frame timing phase difference correction apparatus according to appendix 5, wherein the correction cycle storage unit has a function of controlling and storing the plurality of correction cycles from the outside.
(Appendix 7)
6. The frame timing phase difference correction apparatus according to claim 5, wherein the phase difference detection unit has a function of invalidating the phase difference when the phase difference exceeds a predetermined value.
(Appendix 8)
6. The frame timing phase difference correction apparatus according to appendix 5, wherein the phase difference detection unit has a function of externally controlling and storing a phase difference that invalidates the phase difference.

It is a figure which shows a phase difference correction apparatus block diagram (conventional example). It is a figure which shows the timing (prior art example) of phase correction. It is a figure which shows phase difference correction apparatus block diagram (Example 1, 2). It is a figure which shows a phase difference correction apparatus detailed block diagram (Example 1). It is a figure which shows the timing of each part which carries out a phase correction, and the example of data (Example 1). It is a figure which shows a phase difference correction apparatus block diagram (Example 1). It is a figure which shows a phase difference correction apparatus detailed block diagram (Example 2). It is a figure which shows the timing of each part which carries out a phase correction, and the example of data (Example 2). Change in accumulated phase difference due to correction and time It is a figure which shows a phase difference correction apparatus block diagram (Example 3). It is a figure which shows the receivable range (Example 3).

Explanation of symbols

101 phase difference detection unit 102 phase difference detection result storage unit 103 frame timing generation unit 301 phase difference detection unit 302 phase difference detection result storage unit 303 phase difference correction control unit 304 frame timing generation unit 301-1 frame counter 301-2 latch 302 -1 register 303-1 selector 303-2 selector 304-1 correction period counter 304-2 frame counter 304-3 decoding unit 304-4 selector 1001 phase difference detection unit

Claims (5)

A frame timing phase difference correction method for correcting a phase difference between frame timings of a transmission signal and a reception signal,
Setting a plurality of periods that are integral multiples of the frame period as the correction period for performing the correction in correspondence with the phase difference;
Setting a plurality of clocks corresponding to the phase difference as a correction amount for performing the correction;
Selecting the correction period corresponding to the phase difference detected for each frame period;
Selecting the correction amount corresponding to the phase difference detected for each frame period;
Correcting the phase of the frame timing of the transmission signal based on the selected correction amount for each selected correction period;
A frame timing phase difference correction method comprising: A frame timing phase difference correction apparatus that corrects a phase difference between frame timings of a transmission signal and a reception signal,
A correction cycle storage unit that stores a plurality of cycles that are integer multiples of a frame cycle in association with the phase difference as a correction cycle for performing the correction;
For each frame period, a phase difference detection unit that detects a phase difference between frame timings of the transmission signal and the reception signal;
A correction cycle selection unit that selects the correction cycle for each frame cycle based on the detected phase difference;
A frame timing generator for correcting the frame timing phase of the transmission signal with a predetermined correction amount for each selected correction period; and
A frame timing phase difference correction apparatus comprising: The frame timing phase difference correction device,
A correction amount storage unit that stores a plurality of clock numbers corresponding to the phase difference as the correction amount;
A correction amount selection unit that selects the correction amount based on the phase difference detected for each frame period;
A frame timing generator for correcting and outputting a frame timing phase of a transmission signal with the selected correction amount for each selected correction period;
The frame timing phase difference correction apparatus according to claim 2, further comprising:   4. The frame timing phase difference correction apparatus according to claim 3, wherein the correction amount storage unit has a function of externally controlling and setting the plurality of correction amounts. 3. The frame timing phase difference correction apparatus according to claim 2, wherein the phase difference detection unit has a function of invalidating the phase difference when the phase difference exceeds a predetermined value.

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