JP4827566B2 - Equal storage / discharge circuit - Google Patents

Description

  The present invention relates to an equal storage / discharge circuit that suppresses a deviation in stored voltage between power storage means by transferring charge energy between a plurality of power storage means connected in series.

  An electric double layer capacitor is considered promising as a power storage means in an electric vehicle, an uninterruptible power supply, a storage device of a power generation facility, etc. (Patent Documents 1 to 3). On the other hand, a large-capacity electric double layer capacitor is difficult to store at a high voltage. For this reason, in order to use a large-capacity electric double layer capacitor at a high voltage, it is necessary to connect a plurality of electric double layer capacitors in series.

  When electricity is stored in the electric double layer capacitors connected in series, each electric double layer capacitor is charged with the same charge. On the other hand, there is a deviation in the capacitance of each electric double layer capacitor. For this reason, a deviation occurs in the stored voltage between the electric double layer capacitors connected in series. Such a deviation in the storage voltage between the electric double layer capacitors may cause the electric double layer capacitor having a relatively small capacity to be stored at a voltage higher than the withstand voltage, causing deterioration or failure of the electric double layer capacitor. . For this reason, in Patent Documents 1 to 3 described above, a configuration is proposed in which charge energy is transferred between capacitors so as to suppress a deviation in stored voltage between capacitors.

JP 2000-308271 A JP 2001-177987 A JP 2004-129455 A

  In the configuration described in Patent Document 1, each capacitor is connected in parallel to the winding when a changeover switch (on / off switching controlled) is turned on, so that charge energy is transferred between the capacitors. The deviation of the stored voltage is suppressed (this is referred to as “averaging process”). However, the configuration described in Patent Document 1, as pointed out in Patent Document 2, is limited to the averaging process because the transfer of charge energy is limited to the period during which the changeover switch is on. There is a problem that it takes time.

  To deal with such a problem, Patent Document 2 averages more rapidly by alternately turning on (push-pull driving) two changeover switches and alternately connecting each capacitor in parallel with two windings. A configuration for processing is proposed. However, since the configuration proposed in Patent Document 2 requires two windings for one capacitor, there is a problem that the configuration becomes large.

  In order to solve the problem related to the long time of the averaging process and the large scale of the configuration as described above, as described in Patent Document 3, the winding may be shared between adjacent capacitors. good. However, the configuration described in Patent Document 3 has room for improvement as follows.

  That is, in the configuration described in Patent Document 3, it is necessary to provide three terminals in two windings provided for each of two capacitors (the number of terminals is 1 when the number of capacitors is N (even number)). However, in general, an electric circuit (not limited to a uniform storage / discharge circuit) has a number of wires corresponding to the number of terminals. For this reason, when the number of terminals is large, the number of capacitors connected in series and the installation space thereof are limited. Therefore, in order to simplify the configuration of the uniform storage / discharge circuit, the smaller the number of terminals, the better. An object of the present invention is to realize an equal storage / discharge circuit that can rapidly perform the process of averaging stored voltage between capacitors and that has a simplified configuration.

  The present invention is an equal storage / discharge circuit that suppresses a deviation in stored voltage between the storage means by transferring charge energy between N storage power means (N is an odd number of 3 or more) connected in series. A power storage unit group including N windings connected in series, a common terminal and first and second switching terminals selectively connected to the common terminal, the common terminals being connected in series N + 1 changeover switches connected to both ends of the power storage unit and the common connection part between the storage means, and the first to Nth storage means from the first to the Nth through each common terminal and each first changeover terminal A first storage / discharge path connected in parallel to the first winding, and a first to Nth power storage means connected in parallel to the Nth to first winding via each common terminal and each second switching terminal. And a storage / discharge path including two storage / discharge paths.

  Another aspect of the present invention is an equal storage / discharge circuit that suppresses a deviation in the storage voltage between the power storage means by transferring charge energy between N power storage means (N is an even number of 4 or more) connected in series. A common path connected to the N windings connected in series and the midpoint of the common connection portion of the power storage means group and the midpoint of the common connection portion of the winding group; A first connection terminal and a second switching terminal selectively connected to the common terminal, and a common connection portion between the both ends of the power storage means group in which the common terminals are connected in series and the power storage means. N switches connected from the first to M−1th (M is N / 2) and M + 1th to N−1th, and 1 through each common terminal and each first switching terminal. A first storage / discharge path connecting the Nth to Nth power storage means in parallel with the first to Nth windings; A storage / discharge path including a second storage / discharge path that connects the first to Nth power storage means in parallel to the Nth to first windings via the common terminal and each second switching terminal. It is characterized by that.

  In the present invention, it is preferable that the equal storage / discharge circuit has a third storage / discharge path for transferring charge energy from the power storage means of another equal storage / discharge circuit to the power storage means connected in series. .

  ADVANTAGE OF THE INVENTION According to this invention, the equalization process of the electrical storage voltage between capacitors can be performed rapidly, and the structure can simplify the equal storage / discharge circuit.

  Hereinafter, first to third embodiments for carrying out the present invention will be described with reference to the drawings. The equal storage / discharge circuit described in the present embodiment uses an electric double layer capacitor as the power storage means, but is another power storage means such as a lead storage battery, a lithium secondary battery, a lithium polymer secondary battery, etc. Alternatively, a configuration in which they are mixed may be used.

“First Embodiment”
First, the configuration and operation of the equal storage / discharge circuit 1a according to the first embodiment will be described with reference to FIG. The equal storage / discharge circuit 1a shown in FIG. 1 has three electric double layer capacitors C1 to C3 connected in series. The number of electric double layer capacitors connected in series may be any number as long as it is an odd number of 3 or more.

  The windings L1 to L3 are wound with substantially the same number of turns and connected in series. Taps T1, T2, T3, and T4 are provided at both ends of each of the series-connected windings L1 to L3 and each common connection portion. The windings L1 to L3 are connected in parallel to the electric double layer capacitors C1 to C3 via the changeover switches SW1 to SW4 connected to these taps T1 to T4, so that the charge energy between the electric double layer capacitors C1 to C3 is obtained. Contributes to the transfer of The number of windings L1 to L3 may be the same as that of the electric double layer capacitor described above (that is, an odd number of 3 or more).

  The change-over switches SW1, SW2, SW3, and SW4 are common terminals 1C, 2C, 3C, and 4C, and first switch terminals 11, 21, 31, and 41 that are selectively connected to the common terminals. And second switching terminals 12, 22, 32, 42. Switching control of these changeover switches SW1 to SW4 is performed in synchronization by a control circuit (not shown). The common terminals 1C, 2C, 3C, and 4C are connected to both ends of the series-connected electric double layer capacitors C1 to C3 and a common connection portion between the electric double layer capacitors C1 to C3.

  Each of the first switching terminals 11, 21, 31, 41 is connected in the order of the above-described taps T1, T2, T3, T4 via the storage / discharge path (first switching terminals 11, 21, 21). 31 and 41 and the taps T1, T2, T3, and T4 are referred to as “first storage and discharge paths”. By this first storage / discharge path, the electric double layer capacitors C1 to C3 are connected in parallel to the windings L1 to L3 via the common terminals 1C to 4C and the first switching terminals 11 to 41, respectively.

  Furthermore, each 2nd switching terminal 12, 22, 32, 42 is connected in order of tap T4, T3, T2, T1 mentioned above via the storage / discharge path (2nd switching terminal 12, 22, 32 and 42 and the taps T4, T3, T2 and T1 are referred to as “second storage / discharge paths”. By this second storage / discharge path, the electric double layer capacitors C1 to C3 are connected in parallel to the windings L3 to L1 via the common terminals 1C to 4C and the second switching terminals 12 to 42, respectively. With the above configuration, it is possible to rapidly perform the process of averaging the storage voltage between the capacitors, and to realize an equal storage / discharge circuit with a simplified configuration.

  Next, the operation of the equal storage / discharge circuit 1a shown in FIG. 1 will be described. When the DC voltage Vcc is applied to both ends of the electric double layer capacitors C1 to C3 connected in series, each capacitor is charged with a voltage corresponding to its capacity. As described above, the electric double layer capacitors C1 to C3 have deviations in their capacities, and deviations also occur in the voltages stored in each. The equal storage / discharge circuit 1a according to the present embodiment operates to suppress the deviation of these stored voltage as follows.

  First, when each of the changeover switches SW1 to SW4 is switched to the first changeover terminals 11 to 41, the electric double layer capacitors C1 to C3 are connected via the common terminals 1C to 4C and the first changeover terminals 11 to 41, respectively. Thus, the windings L1 to L3 are connected in parallel (the voltages applied to the respective taps T1 to T4 drop in the order of T1> T2> T3> T4). At this time, the windings L1 to L3 are magnetized by the voltage across the electric double layer capacitors C1 to C3, and a magnetic flux is generated by adding the magnetic fluxes generated in the windings L1 to L3. The magnetic flux generated in this way causes each of the windings L1 to L3 to generate a voltage corresponding to the ratio of the number of turns.

  As described above, since the windings L1 to L3 are wound in the same number, the same voltage (the electric double layer capacitors C1 to C3) is applied to each of the windings L1 to L3 (assuming there is no magnetic leakage). A voltage obtained by averaging the voltages at both ends is generated. At this time, if there is a potential difference between the voltage generated in the windings L1 to L3 and the voltage across the electric double layer capacitors C1 to C3, charge energy is transferred.

  For example, the electric double layer capacitor (for example, C1) having the higher voltage is discharged, and the electric energy stored by the electric double layer capacitor (C2 or C3) having the lower voltage is stored. By such charge energy transfer, the voltage averaging process between the electric double layer capacitors C1 to C3 is performed.

  Next, when each of the changeover switches SW1 to SW4 is switched to the first changeover terminals 12 to 42, the electric double layer capacitors C1 to C3 are connected to the common terminals 1C to 4C and the second changeover terminals 12 to 42, respectively. (The voltage applied to each of the taps T1 to T4 drops in the order of T4> T3> T2> T1). In the same manner as described above, the windings L1 to L3 are magnetized by the voltage across the electric double layer capacitors C1 to C3, and the magnetic flux generated by adding the magnetic fluxes generated in the windings L1 to L3 is generated. Thus, the same voltage (voltage obtained by averaging the voltage across the electric double layer capacitors C1 to C3) is generated in each of the windings L1 to L3. In the same manner as described above, charge energy is transferred between the electric double layer capacitors C1 to C3, and the deviation of the stored voltage between the capacitors is suppressed.

  Thus, in the equal storage / discharge circuit 1a according to the present embodiment, the switches SW1 to SW4 are connected to the electric double layer capacitors C1 to C3 in the order of the windings L1 to L3 and the windings L3 to L1. Since the charge energy is transferred alternately in this order, the averaging process between the electric double layer capacitors C1 to C3 can be performed rapidly. Moreover, the equal storage / discharge circuit 1a according to the present embodiment can be configured such that the number of terminals taken out of the winding is the number of electric double layer capacitors plus one (that is, when the number of capacitors is N, the number of terminals is Therefore, the configuration can be simplified. Therefore, the storage voltage averaging process between the capacitors can be performed rapidly, and an equivalent storage / discharge circuit with a simplified configuration can be realized. Furthermore, since the voltage is applied to each tap so that the voltage is lowered in sequence, the windings can be configured by one electric wire (for example, one electric wire is tapped at a predetermined number of turns. Therefore, it is possible to reduce the manufacturing cost of the uniform storage / discharge circuit.

“Second Embodiment”
Next, the configuration and operation of the equal storage / discharge circuit 1b according to the second embodiment will be described with reference to FIG. In addition, the same code | symbol shall be attached | subjected to the same or similar structure as 1st Embodiment. The equal storage / discharge circuit 1b shown in FIG. 2 has four electric double layer capacitors C1 to C4 connected in series. The number of electric double layer capacitors connected in series may be any number as long as it is an even number of 4 or more.

  The windings L1 to L4 are wound with substantially the same number of turns and connected in series. Taps T1, T2, T3, T4, and T5 are provided at both ends of each of the series-connected windings L1 to L4 and each common connection portion. The number of windings L1 to L4 may be the same as that of the electric double layer capacitor described above (that is, an even number of 4 or more).

  Further, the midpoint of the common connection portions of the electric double layer capacitors C1 to C4 connected in series and the midpoint (tap T3) of the common connection portions of the series connected windings L1 to L4 are: They are connected without going through change-over switches SW1 to SW4 (to be described later) (lines connecting the midpoints are referred to as “common paths”).

The changeover switches SW1, SW2, SW3, and SW4 are common terminals 1C, 2C, 3C, and 4C, and a first changeover terminal that is selectively connected to any one of the common terminals 1C, 2C, 3C, and 4C. 11, 21, 31, 41 and second switching terminals 12, 22, 32, 42, and the switching control is performed in synchronization by a control circuit (not shown). The common terminals 1C, 2C, 3C, and 4C are connected to both ends of the series of electric double layer capacitors C1 to C4 and common connection portions between the electric double layer capacitors C1 to C4 (counted from one). It is connected to the third No. 1 Me及 beauty.

  Each of the first switching terminals 11, 21, 31, 41 is connected in the order of taps T1, T2 and T4, T5 provided on the windings L1 to L4 via a storage / discharge path (first The storage / discharge path connecting the switching terminals 11 to 41 and the taps T1, T2 and T4, T5 is referred to as “first storage / discharge path”). By this first storage / discharge path, the electric double layer capacitors C1 to C4 are connected in parallel to the windings L1 to L4 via the common terminals 1C to 4C and the first switching terminals 11 to 41, respectively.

  Furthermore, each 2nd switching terminal 12, 22, 32, 42 is connected in order of tap T5, T4 and T2, T1 via the storage / discharge path (the 2nd switching terminal 12-42 and tap T5). , T4 and T2, T1 are referred to as “second storage / discharge paths”). With this second storage / discharge path, the electric double layer capacitors C1 to C4 are connected in parallel to the windings L4 to L1 via the common terminals 1C to 4C and the second switching terminals 12 to 42, respectively. With the above configuration, it is possible to rapidly perform the process of averaging the storage voltage between the capacitors, and to realize an equal storage / discharge circuit with a simplified configuration.

  Next, the operation of the equal storage / discharge circuit 1b shown in FIG. 2 will be described. As described above, when the DC voltage Vcc is applied to both ends of the electric double layer capacitors C1 to C4 connected in series, a deviation occurs in the voltage stored in each due to the deviation in capacitance.

  First, when each of the changeover switches SW1 to SW4 is switched to the first changeover terminals 11 to 41, the electric double layer capacitors C1 to C4 are connected via the common terminals 1C to 4C and the first changeover terminals 11 to 41, respectively. The coils L1 to L4 are connected in parallel. Then, the windings L1 to L4 are generated by magnetizing the windings L1 to L4 by the voltage across the electric double layer capacitors C1 to C4 and adding the magnetic fluxes generated by the windings L1 to L4. The same voltage (voltage obtained by averaging the voltages across the electric double layer capacitors C1 to C4) is generated in each of the two. Then, as described above, charge energy is transferred between the electric double layer capacitors C1 to C4, and the deviation of the stored voltage between the capacitors is suppressed.

  Next, when each of the changeover switches SW1 to SW4 is switched to the second changeover terminals 12 to 42, the electric double layer capacitors C1 to C4 are connected to the common terminals 1C to 4C and the second changeover terminals 12 to 42, respectively. Through the windings L4 to L1. As described above, the windings L1 to L4 are magnetized by the voltage across the electric double layer capacitors C1 to C4, and the magnetic flux generated by adding the magnetic fluxes generated in the windings L1 to L4 is generated. Thus, the same voltage (voltage obtained by averaging the voltages at both ends of the electric double layer capacitors C1 to C4) is generated in each of the windings L1 to L4. Then, as described above, charge energy is transferred between the electric double layer capacitors C1 to C4, and the deviation of the stored voltage between the capacitors is suppressed.

  Therefore, the equal storage / discharge circuit according to the present embodiment can rapidly perform the averaging process between the electric double layer capacitors C1 to C4, and can further simplify the configuration. Similarly, in the equal storage / discharge circuit according to the present embodiment, the winding can be configured by a single electric wire, and the manufacturing cost of the equal storage / discharge circuit can be reduced.

“Third Embodiment”
Next, the configuration and operation of the equal storage / discharge system according to the third embodiment will be described with reference to FIG. As described above, the equal storage / discharge circuit according to the first and second embodiments can simplify the configuration. For this reason, for example, in an electric vehicle or the like, an installation space in which an electric double layer capacitor can be added can be secured.

  As described above, the equal storage / discharge circuit needs to have the same number of windings as the number of electric double layer capacitors. However, as the number of electric double layer capacitors increases, the windings of the equal storage / discharge circuit increase. It is not economical, and it is desirable that the electric double layer capacitor can be easily added without remodeling such as adding a winding.

  On the other hand, if a plurality of equal storage / discharge circuits are provided and each electric double layer capacitor group is simply connected in series, there is a deviation in capacity between each electric double layer capacitor group, so that the storage voltage is also reduced. Deviation occurs. Therefore, in the present embodiment, when the electric double layer capacitor groups of a plurality of equal storage and discharge circuits are connected in series as described below, the equal storage and discharge system that suppresses the deviation of the storage voltage between the electric double layer capacitor groups is as follows. Is realized. In addition, the same code | symbol shall be attached | subjected to the same or similar structure as 1st and 2nd embodiment.

  The equal storage / discharge system shown in FIG. 3 includes equal storage / discharge circuits 1c and 2c. Each of the equal storage / discharge circuits 1c and 2c shown in FIG. 3 has the same configuration as that in which the number of capacitors of the above-described equal storage / discharge circuit 1b is six, and through the third storage / discharge path, The charge energy is transferred between each electric double layer capacitor group.

  Electric double layer capacitors C0 to C15 are connected in parallel to the windings L1C to L15 of the equal storage / discharge circuit 1c via changeover switches SW1C to SW15. Similarly, the electric double layer capacitors C15 to C25 are connected in parallel to the windings L2C to L25 of the equal storage / discharge circuit 2c via the changeover switches SW2C to SW25. Therefore, the equal storage / discharge circuits 1c and 2c are connected so that the electric double layer capacitor C15 is commonly used for each averaging process.

  The operation will be described below. As described above, when a DC voltage Vcc is applied across the electric double layer capacitors C0 to C25 connected in series, the voltage stored in each of the electric double layer capacitors C0 to C15 and C21 to C25 is deviated. Occurs.

  First, in the equal storage / discharge circuit 1c, similarly to the above-described equal storage / discharge circuit 1b, when the changeover switches SW1C to SW15 are switched on / off in synchronization, the storage voltage between the electric double layer capacitors C0 to C15 is changed. Deviation is suppressed. On the other hand, in the equal storage / discharge circuit 2c, similarly, the switches SW2C to SW25 are switched on / off in synchronization, thereby suppressing the deviation of the stored voltage between the electric double layer capacitors C15 to C25. Therefore, the deviation of the storage voltage between all the electric double layer capacitors C0 to C25 is suppressed, and the deviation of the storage voltage between the capacitor groups is also suppressed.

  Further, when further adding the equal storage / discharge circuit, instead of the electric double layer capacitor C0 connected to the equal storage / discharge circuit 1c, the electric double layer connected to another (added) equal storage / discharge circuit. A capacitor may be connected (similar to the electric double layer capacitor C15 described above). By adopting such a configuration, it is possible to realize an equal storage / discharge system in which an electric double layer capacitor can be easily added without modification such as an additional winding.

  In addition, although the switch group in each equal storage / discharge circuit needs to be controlled on / off in synchronization, the switch groups between the equal storage / discharge circuits (1c and 2c) do not need to be synchronized. In addition, although this embodiment demonstrated the structure which connects the equal storage / discharge circuit which has an even number of electric double layer capacitor groups (including a shared capacitor) in series, even if it is an odd number, it can do similarly. Needless to say.

It is a figure showing the equal storage / discharge circuit which concerns on 1st Embodiment. It is a figure showing the equal storage-and-discharge circuit which concerns on 2nd Embodiment. It is a figure showing the equal storage / discharge system which concerns on 3rd Embodiment.

Explanation of symbols

  C1-C3 electric double layer capacitor, L1-L3 winding, SW1-SW4 changeover switch, T1-T4 tap.

Claims (3)

An equal storage / discharge circuit that suppresses a deviation in the storage voltage between the storage means by transferring charge energy between N storage units (N is an odd number of 3 or more) connected in series,
N windings connected in series;
Including a common terminal and first and second switching terminals selectively connected to the common terminal, and a common connection portion between the both ends of the power storage means group in which the common terminals are connected in series and the power storage means N + 1 changeover switches connected to
A first storage / discharge path connecting the first to Nth power storage means in parallel to the first to Nth windings via each common terminal and each first switching terminal; and each common terminal and each second A storage / discharge path including a second storage / discharge path connecting the first to Nth power storage means in parallel to the Nth to first windings via the switching terminal;
An equal storage and discharge circuit comprising: An equal storage and discharge circuit that suppresses a deviation in the storage voltage between the storage means by transferring charge energy between N storage units (N is an even number of 4 or more) connected in series,
N windings connected in series;
A common path connected to a midpoint of the common connection of the power storage means group and a midpoint of the common connection of the winding group;
A common connection portion between the power storage means and both ends of the power storage means group including the common terminal and first and second switching terminals selectively connected to the common terminal, the common terminals being connected in series N switches connected from the first to the M−1th (M is N / 2) and from the M + 1th to the N−1th,
A first storage / discharge path connecting the first to Nth power storage means in parallel to the first to Nth windings via each common terminal and each first switching terminal; and each common terminal and each second A storage / discharge path including a second storage / discharge path connecting the first to Nth power storage means in parallel to the Nth to first windings via the switching terminal;
An equal storage and discharge circuit comprising: An equal storage and discharge system comprising a plurality of equal storage and discharge circuits according to claim 1 or 2,
The equal storage and discharge circuit is:
The equal storage / discharge system characterized by having a third storage / discharge path for transferring charge energy from the storage means of another equal storage / discharge circuit to the storage means connected in series.

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