JP4828306B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A ferroelectric memory (FeRAM) is a non-volatile memory capable of low voltage and high speed operation, and a memory cell can be composed of one transistor / one capacitor (1T / 1C), so that it can be integrated like a DRAM. Therefore, it is expected as a large-capacity nonvolatile memory. For example, Patent Document 1 and Patent Document 2 disclose a tungsten plug and a capacitor in order to prevent oxidation of the tungsten plug, which may deteriorate memory characteristics and reliability in the 1T / 1C type (stacked type) ferroelectric memory device. It is described that a diffusion preventing layer is provided on the contact (contact region) with the electrode and the side wall of the electrode of the capacitor.
JP 2004-172330 A JP 2004-31533 A

  By the way, in a stack type ferroelectric memory device, a capacitor is formed in a region on a substrate including a plug formation region. Therefore, in order to produce a capacitor having good characteristics, a capacitor formation surface (a plug surface and its periphery). The flatness of the surface of the interlayer insulating film is extremely important. For example, Patent Document 1 describes that a CMP (Chemical Mechanical Polishing) process or an etch-back process is performed after forming a tungsten plug for such a planarization process. It is almost unsuitable for mass production. In addition, since the surface of the tungsten plug has large crystal grains, irregularities are likely to occur, and it is difficult to improve the crystal orientation of the layer formed on the surface of the tungsten plug.

  The present invention has been made in view of the above problems of the prior art, and includes a semiconductor device having improved crystal orientation of a device constituent layer in a semiconductor device having a conductive connection structure via a plug, and the crystal An object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the orientation.

The semiconductor device of the present invention is a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, and the plug is placed in the through hole. A plug conductive layer embedded with the first conductive film, and a recess made of a titanium nitride film or a titanium alloy nitride film in the recess formed on the plug conductive layer and having a thickness smaller than the depth of the recess; A base conductive film having a thickness is formed to cover the inner surface of the recess, and a second conductive layer comprising a titanium nitride film containing silicon or a titanium alloy nitride film containing silicon in a region surrounded by the base conductive film. A film is embedded, and a third conductive film made of a titanium nitride film having a (111) orientation is formed on the second conductive film.
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, Forming a through hole in the interlayer insulating film, forming a plug conductive layer by embedding the first conductive film in the through hole, and the interlayer insulation including a recess formed on the plug conductive layer. Forming a base conductive film made of a titanium nitride film or a titanium alloy nitride film on the film in a thickness thinner than the depth of the recess; and a titanium nitride film containing silicon on the base conductive film Alternatively, a step of forming a second conductive film made of a titanium alloy nitride film containing silicon, and a CMP process is performed on the second conductive film and the base conductive film, thereby forming the base in the recess on the plug conductive layer. Conductive film and said first A step of embedding a conductive film, a step of exciting and irradiating plasma of a gas having a molecular structure in which nitrogen and hydrogen are bonded to the upper surface of the second conductive film and the surface of the interlayer insulating film, and the plasma Forming a third conductive film made of a titanium nitride film having a (111) orientation in a region including the upper surface of the second conductive film irradiated with.
In order to solve the above-mentioned problems, the present invention provides a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, wherein the plug includes: A plug conductive layer is formed by embedding a first conductive film in the through hole, and a second conductive film made of a conductive material containing silicon is formed on at least the plug conductive layer. On the two conductive films, a third conductive film made of a conductive material having self-orientation is formed.
According to this configuration, since the second conductive film made of a conductive material containing silicon is provided on the plug conductive layer, surface modification treatment (N—H such as NH ₃ plasma treatment) is performed on the surface of the second conductive film. It is possible to effectively function a surface modification treatment in which a plasma in which a gas having a bond in a molecular structure is excited is irradiated. And since the crystal orientation which was excellent in the 3rd electrically conductive film formed by forming the electrically conductive material which has self-orientation on the 2nd electrically conductive film after the said surface modification process can be obtained, this 3rd electrically conductive film is utilized. If a device such as a capacitor is formed, excellent crystal orientation can be obtained for each layer constituting the device.

In the semiconductor device of the present invention, the second conductive film may be embedded in a recess formed on the plug conductive layer.
According to this configuration, the step at the boundary between the plug surface and the interlayer insulating film surface can be eliminated and flattened, so that it is possible to prevent the crystal orientation of the third conductive film from being lowered due to the step. it can.

  In the semiconductor device of the present invention, the second conductive film may be a titanium nitride film containing silicon, and the second conductive film is a titanium alloy nitride film containing silicon. You can also. If these conductive materials are used, excellent flatness can be obtained particularly in a structure in which the second conductive film is embedded in the recess.

  In the semiconductor device of the present invention, a base conductive film may be formed between the plug conductive layer and the second conductive film. A conductive material containing silicon may have a higher resistance than a conductive material not containing silicon, and depending on the degree, the contact conduction failure of the plug may occur even with a thin film of about several tens of nanometers. is there. Therefore, the film thickness of the second conductive film can be reduced by forming the base conductive film on the plug conductive layer and forming the second conductive film on the base conductive film. In particular, in the structure in which the second conductive film is embedded in the recess, the film thickness of the second conductive film is determined by the depth of the recess. It is effective to reduce the film thickness of the second conductive film.

  In the semiconductor device of the present invention, the base conductive film is preferably a titanium nitride film or a titanium alloy nitride film. By using these materials, a structure having excellent adhesion between the second conductive film and the base conductive film and crystal orientation of the second conductive film can be obtained, which can improve the yield of the semiconductor device and reduce the second conductive film. The structure contributes to resistance and improvement in crystallinity of the third conductive film.

  In the semiconductor device of the present invention, the base conductive film preferably has a thickness of 10 nm or less. The base conductive film does not need to be formed thick. In particular, in the structure in which the second conductive film is embedded in the recess, it is preferable to suppress the thickness to the above-described thickness so that the recess is not buried in the base conductive film.

  In the semiconductor device of the present invention, it is preferable that the third conductive film is a titanium nitride film. With such a configuration, a good self-orientation property on the second conductive film can be obtained, and the plug conductive layer can be effectively prevented from being oxidized.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, Forming a through hole in the interlayer insulating film, forming a plug conductive layer by embedding the first conductive film in the through hole, and a second conductive material containing silicon at least on the plug conductive layer. A step of forming a conductive film, a step of exciting and irradiating plasma of a gas having a molecular structure in which nitrogen and hydrogen are combined on the second conductive film, and a method of manufacturing a semiconductor device according to the present invention, Forming a third conductive film made of a conductive material having self-orientation on the second conductive film irradiated with plasma.
According to this manufacturing method, since the second conductive film made of the conductive material containing silicon is formed on the plug conductive layer, the surface of the plug conductive layer or the second conductive film made of the conductive material not containing silicon is formed on the surface. The effect of the surface modification treatment can be greatly improved as compared with the case of performing the modification treatment. Thereby, favorable crystal orientation can be obtained for the third conductive film formed on the second conductive film.

  In the method of manufacturing a semiconductor device according to the present invention, the second conductive film is formed on the plug conductive layer, and then the second conductive film is subjected to a CMP process, thereby forming the recess formed on the plug conductive layer. The second conductive film is embedded inside. With this manufacturing method, the recess on the plug conductive layer can be flattened, so that the crystal orientation of the third conductive film is lowered due to a step at the boundary between the plug and the interlayer insulating film. Can be prevented, and the functional degradation of the device using the third conductive film can be prevented.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a base conductive film on the interlayer insulating film including the recess prior to the step of forming the second conductive film. By forming the base conductive film in the recess in this way, the second conductive film which may be a high resistance film because of containing silicon can be thinned, and it is possible to effectively prevent a poor contact conduction of the plug. This greatly contributes to improving the yield of semiconductor devices.

  The method for manufacturing a semiconductor device of the present invention includes a step in which the third conductive film is a layer made of titanium, and the titanium layer is converted to a titanium nitride layer by heat treatment in a nitrogen atmosphere after the titanium layer is formed. It is characterized by that. According to this manufacturing method, it is possible to first form a titanium layer on the second conductive film to obtain a good self-orientation effect, and then nitrify the titanium layer to prevent oxidation of the titanium layer. In addition, the structure contributes to prevention of oxidation of the plug conductive layer in the through hole.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Semiconductor device)
FIG. 1 is a cross-sectional view schematically showing a semiconductor device (ferroelectric memory device) 100 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a ferroelectric capacitor 30, a plug 20, and a switching transistor 18 of the ferroelectric capacitor 30. In this embodiment, a 1T / 1C type (1 transistor / 1 capacitor type) memory cell is described. However, the present invention is not limited to a 1T / 1C type memory cell.

  The switching transistor 18 includes a gate insulating film 11, a gate conductive layer 13 provided on the gate insulating film 11, and a first impurity region 17 and a second impurity region 19 which are source / drain regions. The ferroelectric capacitor 30 is formed on the titanium nitride layer 12, the barrier layer 14 formed on the titanium nitride layer 12, the first electrode 32 formed on the barrier layer 14, and the first electrode 32. A ferroelectric layer 34 and a second electrode 36 formed on the ferroelectric layer 34 are provided.

  The plug 20 that electrically connects the switching transistor 18 and the ferroelectric capacitor 30 is formed in a through hole 24 formed through the interlayer insulating film 26 that covers the switching transistor 18. The second impurity region 19 and the titanium nitride layer 12 of the ferroelectric capacitor 30 are interposed. The plug 20 has a first base layer 22a provided in the through hole 24, a second base layer 22b formed on the first base layer 22a, and a hole surrounded by the second base layer 22b, for example, Plug conductive layer 22 formed by filling a first conductive film made of tungsten, molybdenum, tantalum, titanium, nickel or the like, and a second conductive film formed so as to cover the ferroelectric capacitor 30 side of plug conductive layer 22 21. The plug conductive layer 22 is preferably formed using tungsten among the metal materials mentioned above.

  In the semiconductor device according to the present invention, the illustrated upper surface of the plug conductive layer 22 is located on the inner side of the through hole 24 with respect to the surface of the interlayer insulating film 26, and a so-called recess is formed on the plug conductive layer 22. The boundary between the surface of the plug 20 and the surface of the interlayer insulating film 26 is adjusted to be flat by the second conductive film 21 formed in the recess so as to cover the plug conductive layer 22. . The second conductive film 21 is made of a conductive material containing silicon, and is preferably made of titanium nitride added with silicon or titanium alloy nitride added with silicon. In the present invention, by forming the second conductive film using these materials, the surface of the interlayer insulating film 26 in the formation region of the plug 20 can be obtained with good flatness, and the surface of the plug 20 can be modified. The effect of the treatment is enhanced, and the crystal orientation of the titanium nitride layer 12 on the plug 20 can be improved.

  At least a part of the titanium nitride layer (third conductive film) 12 formed in a region on the interlayer insulating film 26 including the second conductive film 21 is provided on the plug 20. The titanium nitride layer 12 is a titanium nitride crystalline film that exhibits self-orientation at the time of film formation, and has a (111) orientation. The titanium nitride layer 12 can be formed by nitriding a Ti film, and can be made of TiN. A method for forming the titanium nitride layer 12 will be described later. The thickness of the titanium nitride layer 12 is preferably 5 nm to 20 nm.

The barrier layer 14 is not particularly limited as long as it is made of a material having conductivity and oxygen barrier properties. Examples of the material for forming the barrier layer 14 include TiAlN, TiAl, TiSiN, TiN, TaN, and TaSiN. Among these, it is more preferable to use TiAlN. When the barrier layer 14 is made of TiAlN, the composition (atomic ratio) of titanium, aluminum, and nitrogen in the barrier layer 14 is 0 <x when the composition of the barrier layer 14 is represented by the chemical formula Ti _(1-x) Al _x N _y. More preferably, ≦ 0.3 and 0 <y.

  The barrier layer 14 is preferably a crystalline thin film, and is preferably a polycrystalline film or a single crystal film having a (111) orientation. By setting the crystal orientation of the barrier layer 14 to the (111) orientation, the first electrode 32 having a crystal orientation ((111) orientation) reflecting the crystal orientation of the barrier layer 14 can be formed on the barrier layer 14. Because it can. The film thickness of the barrier layer 14 is preferably at least 20 nm, and more preferably, for example, 100 to 200 nm. This is because the first electrode 32 having a crystal orientation reflecting the crystal orientation of the barrier layer 14 at the time of film formation is satisfactorily formed on the barrier layer 14.

  The first electrode 32 can be formed using at least one metal material selected from platinum, ruthenium, rhodium, palladium, osmium, and iridium. Further, it is preferably made of platinum or iridium, more preferably made of iridium. The first electrode 32 may be a single layer film of the above metal material or a multilayer film in which a plurality of metal films are stacked. The first electrode 32 is preferably a crystalline thin film epitaxially grown on the barrier layer 14. In addition, the ferroelectric layer 34 formed on the first electrode 32 is preferably epitaxially grown on the first electrode 32.

  For example, when the barrier layer 14 belongs to a cubic system and the crystal orientation is a (111) orientation, or when the barrier layer 14 belongs to a hexagonal system and the crystal orientation is a (001) orientation, the first electrode The crystal orientation of 32 is preferably (111) orientation. According to this configuration, when the ferroelectric layer 34 is formed on the first electrode 32, the crystal orientation of the ferroelectric layer 34 can be easily set to the (111) orientation.

The ferroelectric layer 34 includes a ferroelectric material. This ferroelectric substance preferably has a perovskite crystal structure represented by the general formula of A _{1 -b} B _{1 -a} X _a O ₃ . A may contain Pb, and a part of Pb may be substituted with La. B is Zr or Ti. X is at least one metal element selected from V, Nb, Ta, Cr, Mo, W, Ca, Sr, and Mg. As the ferroelectric substance contained in the ferroelectric layer 34, a known material that can be used as the ferroelectric layer can be used. For example, (Pb (Zr, Ti) O ₃ ) (PZT), SrBi can be used. ₂ Ta ₂ O ₉ (SBT), (Bi, La) ₄ Ti ₃ O ₁₂ (BLT). Among these, the material of the ferroelectric layer 34 is preferably PZT. In this case, the first electrode 32 is more preferably iridium from the viewpoint of device reliability.

  When PZT is used as the ferroelectric layer 34, it is preferable to make the titanium content in the PZT larger than the zirconium content in order to obtain a larger amount of spontaneous polarization. PZT having such a composition belongs to tetragonal crystal, and its spontaneous polarization axis is c-axis. In this case, since an a-axis orientation component orthogonal to the c-axis is present at the same time, when PZT is oriented in the c-axis, the a-axis orientation component does not contribute to polarization reversal, and thus the ferroelectric characteristics may be impaired. . On the other hand, by setting the crystal orientation of PZT used for the ferroelectric layer 34 to the (111) orientation, the a-axis can be oriented in a direction shifted by a certain angle from the substrate normal. That is, since the polarization axis has a component in the substrate normal direction, it can contribute to polarization inversion. Therefore, when the ferroelectric layer 34 is made of PZT and the titanium content in the PZT is larger than the zirconium content, the crystal orientation of the PZT is preferably the (111) orientation in terms of good hysteresis characteristics. .

  The second electrode 36 can be formed of the above-described materials exemplified as materials usable for the first electrode 32, or aluminum, silver, nickel, or the like can be used. The second electrode 36 may be a single layer film of the metal material exemplified above, or may be a multilayer film in which a plurality of metal films are stacked. The second electrode 36 is preferably a single layer film of platinum or a laminated film of an iridium oxide film and an iridium film.

  In the semiconductor device 100 of the present embodiment, the second conductive film 21 is formed on the ferroelectric capacitor 30 side of the plug 20 to flatten the surface of the interlayer insulating film 26 on which the ferroelectric capacitor 30 is formed and the plug 20. Therefore, it is possible to effectively prevent a decrease in crystal orientation of the first electrode 32, the ferroelectric layer 34, and the like due to a step between the plug 20 and the surrounding interlayer insulating film 26, and the crystal orientation Thus, a ferroelectric memory including the high-quality ferroelectric capacitor 30 having excellent properties can be configured.

  Although details will be described later, the crystal structure of the lower plug conductive layer 22 is not reflected by the crystal structure of each layer constituting the upper ferroelectric capacitor 30 by the second conductive film 21 in the plug 20 forming step. Therefore, it is possible to prevent the crystal orientation of the first electrode 32 and the ferroelectric layer 34 from being lowered due to the difference in material between the surface of the plug 20 and the surface of the interlayer insulating film 26. Furthermore, since the first electrode 32 of the ferroelectric capacitor 30 is provided on the plug 20 via the titanium nitride layer 12 and the barrier layer 14, the crystal structure of the lower layer (plug 20) is not reflected better. The first electrode 32 and the ferroelectric layer 34 can be formed.

  A case is assumed in which the first electrode 32 of the ferroelectric capacitor 30 is directly disposed on the plug conductive layer 22 of the plug 20. In this case, when the plug conductive layer 22 is made of a material having high crystallinity, the crystal orientation of the plug conductive layer 22 may affect the crystal orientation of the first electrode 32. For example, when the plug conductive layer 22 of the plug 20 is made of tungsten, since tungsten has high crystallinity, when the first electrode 32 is directly provided on the plug conductive layer 22 made of tungsten, the crystal structure of the plug conductive layer 22 Affects the crystal structure of the first electrode 32, making it difficult to make the first electrode 32 have a desired crystal structure. Furthermore, since the ferroelectric layer 34 is provided on the first electrode 32, the crystal orientation of the first electrode 32 may affect the crystal orientation of the ferroelectric layer 34. Then, since the crystal orientation of the ferroelectric layer 34 reflects the crystal orientation of the first electrode 32, the hysteresis characteristic of the ferroelectric capacitor 30 may be deteriorated as a result of polarization occurring in an undesired direction.

  On the other hand, according to the ferroelectric capacitor 30 of the present embodiment, the second conductive film 21 made of a conductive material containing silicon is provided on the contact portion side of the plug 20 with the ferroelectric capacitor 30. The effect of the surface modification treatment performed on the surface of the second conductive film 21 can be improved. Thereby, the self-orientation of the titanium nitride layer 12 is improved, and the titanium nitride layer 12 having good crystal orientation grown in a preferred orientation direction can be obtained. As a result, a preferable crystal orientation can be obtained also for the barrier layer 14 on the titanium nitride layer 12, and the plug conductive layer 22 for the first electrode 32 and the ferroelectric layer 34 formed on the barrier layer 14. It is possible to obtain a preferred orientation state that is not affected by the crystal orientation. Thereby, the ferroelectric capacitor 30 having excellent hysteresis characteristics can be obtained.

  When the cross-sectional area of the plug 20 is the same, the smaller the planar area of the ferroelectric capacitor 30 is, the smaller the ratio of the planar area of the ferroelectric capacitor 30 to the cross-sectional area of the plug 20 is. Due to this crystal orientation, the problem of crystal orientation extending to the first electrode 32 and the ferroelectric layer 34 becomes more serious. On the other hand, according to the ferroelectric capacitor 30 of the present embodiment, for the reason described above, even when the ferroelectric capacitor 30 is further miniaturized, it is useful in that a decrease in hysteresis characteristics can be prevented. It is.

  Further, according to the ferroelectric capacitor 30 of the present invention, the first electrode 32 is provided on the crystalline barrier layer 14. Thereby, the crystal orientation of the 1st electrode 32 provided on the barrier layer 14 can be improved. As a result, since the ferroelectric layer 34 having excellent crystal orientation can be provided on the first electrode 32, the hysteresis characteristics are excellent.

  In particular, as described above, when the ferroelectric layer 34 is made of PZT and the titanium content in the PZT is greater than the zirconium content, the crystal orientation of the PZT is (111) oriented in that the hysteresis characteristics are good. Is preferred. According to the ferroelectric capacitor 30 of the present embodiment, since the barrier layer 14 having the crystal orientation (111) is provided, the crystal orientation of the first electrode 32 and the ferroelectric layer 34 is (111). ) Easy to align. Thereby, the ferroelectric capacitor 30 of the present embodiment is excellent in hysteresis characteristics.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device according to the embodiment will be described with reference to the drawings.
FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3C are cross-sectional views schematically showing an example of the manufacturing process of the semiconductor device 100 of FIG. 2 and 3, the switching transistor 18 in the semiconductor device 100 of FIG. 1 is shown in a simplified manner.

The manufacturing method of the semiconductor device 100 of the present embodiment includes the following steps S1 to S6.
(S1) A step of forming the through hole 24 in the interlayer insulating film 26 formed on the substrate 10. (S2) The first conductive film is formed on the interlayer insulating film 26 including the inside of the through hole 24, and the plug conductive layer 22 embedded in the through hole 24 by removing the first conductive film on the interlayer insulating film 26. Forming. (S3) A step of forming a second conductive film on the interlayer insulating film 26 including the recess on the plug conductive layer 22. (S4) The second conductive film on the interlayer insulating film 26 is removed by a CMP (Chemical Mechanical Polishing) process, the second conductive film is embedded in the recess on the plug conductive layer 22, and the interlayer insulation including the region where the plug 20 is formed Flattening the upper surface of the film 26; (S5) A step of converting the titanium layer into the titanium nitride layer 12 by forming a titanium layer on the plug 20 and performing heat treatment in an atmosphere containing nitrogen. (S6) A step of laminating the barrier layer 14, the first electrode 32, the ferroelectric layer 34, and the second electrode 36 on the titanium nitride layer 12.

  First, the switching transistor 18 and the like are formed on the semiconductor substrate 10 (see FIG. 1). Next, an oxide film such as TEOS (tetraethylorthosilicate), BPSG (boron phosphorus silicate glass), NSG (non-doped silicate glass) is formed by, for example, atmospheric pressure or low pressure CVD. At this time, if the thickness of the oxide film is about 1 μm or more, the switching transistor 18 can be sufficiently covered. Subsequently, the interlayer insulating film 26 can be formed by planarizing the surface of the oxide film by CMP treatment. Thereafter, the through hole 24 is formed in the interlayer insulating film 26 using, for example, a photolithography method and a dry etching method.

  Next, a titanium film as the first underlayer 22a and a titanium nitride film as the second underlayer 22b are stacked on the interlayer insulating film 26 in which the through holes 24 are formed by using a sputtering method or the like, and further the first A tungsten film is formed as a conductive film. Next, the first base layer 22a, the second base layer 22b, and the first conductive film on the interlayer insulating film 26 are removed by CMP treatment, so that the first base in the through hole 24 as shown in FIG. A plug conductive layer 22 is formed by embedding the first conductive film via the base layer 22a and the second base layer 22b. At this time, a recess 24a made of a recess having a depth of about 30 nm is formed on the plug conductive layer 22 by the CMP process.

Next, as shown in FIG. 2B, a second conductive film 121 made of titanium nitride containing silicon or titanium alloy nitride containing silicon is formed on the interlayer insulating film 26 by sputtering or the like. For example, a titanium nitride film containing several at% of silicon is formed by performing film formation using a Ti target added with several at% of silicon and using Ar—N ₂ mixed gas as a sputtering gas. Can do. Further, if film formation is performed using a silicon-containing TiAl target instead of the silicon-containing Ti target, a titanium alloy nitride film containing several at% of silicon can be formed. Note that the film thickness of the second conductive film 121 during film formation is about 100 nm to 500 nm. In addition, if the amount of silicon added to the Ti target or TiAl target is too large, silicon may agglomerate or segregate during the production of the target, which may cause abnormal discharge, and the silicon content is usually less than 10 at%. .

  Next, the second conductive film 121 on the interlayer insulating film 26 is removed by CMP treatment, and the second conductive film 21 is embedded in the recess 24a as shown in FIG. In this way, the first underlayer 22a, the second underlayer 22b, the plug conductive layer 22 embedded in the through hole 24, and the silicon-containing titanium nitride or silicon-containing titanium alloy nitride embedded in the recess 24a. Thus, the plug 20 including the second conductive film 21 can be formed. By embedding the second conductive film 21 in the recess 24a in this manner, the upper surface of the plug 20 shown in the figure can be flush with the surface of the interlayer insulating film 26, and the ferroelectric capacitor 30 is formed in a subsequent process. A region on the substrate to be formed can be satisfactorily planarized.

Next, as shown in FIG. 2D, NH ₃ plasma treatment is performed on the region on the interlayer insulating film 26 including the plug 20. The NH ₃ plasma treatment is a treatment for modifying the surface of the plug 20 by irradiating the surface of the plug 20 (surface portion 21a) and the surface of the interlayer insulating film 26 with ammonia gas plasma. By performing such surface modification treatment, a self-alignment layer can be formed not only on the interlayer insulating film 26 made of silicon oxide but also on the plug 20 by forming a self-orientation material. In the case of this embodiment, a titanium layer is formed as a self-alignment layer, and this is nitrided to obtain a highly oriented titanium nitride layer 12.
As the NH ₃ plasma treatment conditions in the above process, for example, the flow rate of NH ₃ gas introduced into the chamber is 350 sccm, the pressure in the chamber is 1 Torr, the substrate temperature is 400 ° C., and the high frequency of 13.56 MHz supplied to the substrate. The power of the power source is set to 100 W, the power of the 350 kHz high frequency power source supplied to the plasma generation region is set to 55 W, the distance between the electrode and the semiconductor substrate 10 is set to 350 mils, and the plasma irradiation time is set to 60 seconds.

Next, as shown in FIG. 3A, a titanium layer (self-alignment layer) 12a having a thickness of about 20 nm is formed on the plug 20 and the interlayer insulating film 26 surface-modified by NH ₃ plasma treatment by sputtering or the like. Form. The film thickness of the titanium layer 12a is preferably 5 nm to 20 nm in order to improve the orientation control of the barrier layer 14 formed on the titanium nitride layer 12 formed by nitriding the titanium layer 12a. When the thickness of the titanium layer 12a is less than 5 nm, it is difficult to obtain (002) orientation for controlling the barrier layer 14 to (111) orientation. On the other hand, when the thickness of the titanium layer 12a exceeds 20 nm, nitridation of the titanium layer 12a is difficult to proceed in a process described later.

In the present embodiment, titanium, which is a self-orienting material, is c-axis aligned on the interlayer insulating film 26 and the second conductive film 21 by the previous NH ₃ plasma treatment, and the (002) -oriented titanium layer 12a is formed. Obtainable. By the way, it is known that when the titanium layer is formed without performing the NH ₃ plasma treatment, good (002) orientation cannot be obtained even on the interlayer insulating film 26. This is because titanium is easily bonded to oxygen atoms, and therefore, when the film is formed without any surface modification treatment, it easily bonds to oxygen atoms on the surface of the interlayer insulating film 26, which is a silicon oxide, and the orientation axis of the titanium crystal is c. This is probably because crystal growth occurs in a state deviated from the axis.

On the other hand, by performing the NH ₃ plasma treatment, the (002) -oriented titanium layer 12 a can be easily obtained on the interlayer insulating film 26. This is because the NH ₃ plasma treatment causes NH ₃ groups derived from NH ₃ to bond to oxygen atoms (O) exposed on the surface of the silicon oxide constituting the interlayer insulating film 26, thereby causing interlayer insulation. It is considered that this is because an O—N—H bond is formed on the surface of the film 26. The reactivity between the interlayer insulating film 26 and titanium can be reduced by bonding nitrogen atoms and hydrogen atoms to oxygen atoms on the surface that are easily bonded to titanium, and thereby the titanium that has come to the surface can be reduced. As a result of promoting the migration, it is considered that the c-axis of the titanium crystal can be oriented in a direction perpendicular to the substrate.

As described above, the NH ₃ plasma treatment is extremely effective for orienting titanium or the like on the silicon oxide film. However, in the present embodiment, the second conductive film 21 is a silicon-containing titanium nitride film or silicon-containing film. Since it is made of titanium alloy nitride, the NH ₃ plasma treatment functions effectively also on the surface portion 21 a of the second conductive film 21. Silicon atoms are present on the surface portion 21a of the second conductive film 21 made of a conductive material containing silicon, and NH ₃ groups derived from NH ₃ are easily adsorbed to the silicon atoms. An NHx group is bonded to a silicon atom that is easily formed to form a Si—N—H bond in the surface portion 21a. Therefore, the reactivity between the surface portion 21a and titanium is reduced, and migration of the incoming titanium is promoted. As a result, the c-axis of the titanium crystal can be oriented with respect to the substrate.
Therefore, according to the manufacturing method of the present embodiment, the (002) -oriented titanium layer 12 a can be formed on the entire surface of the interlayer insulating film 26 and the plug 20.

  Next, as shown in FIG. 3B, the titanium layer 12a is nitrided by an RTA (Rapid Thermal Annealing) process in a nitrogen atmosphere to obtain the titanium nitride layer 12. The conditions for the RTA treatment are, for example, 650 ° C. and 2 minutes. This titanium layer is prevented from being oxidized by the heat treatment (recovery annealing treatment) in an oxygen atmosphere after the ferroelectric capacitor 30 is formed by previously nitriding the titanium layer by the RTA treatment in this step. can do.

  Next, as shown in FIG. 3C, the constituent layers of the ferroelectric capacitor 30 are sequentially laminated on the titanium nitride layer 12, and the laminated film is patterned to manufacture the semiconductor device 100 according to the present invention. can do. The manufacturing process after the barrier layer 14 will be briefly described below.

On the titanium nitride layer 12, the barrier layer 14 made of TiAlN or the like described above is formed by sputtering or CVD. In this embodiment, since the titanium nitride layer 12 exhibits good (002) orientation, a TiAlN film epitaxially grown in the (111) orientation can be formed on the barrier layer 14.
Next, an iridium film having a thickness of, for example, 100 nm is formed on the barrier layer 14 using a sputtering method or the like, thereby forming the first electrode 32. In this embodiment, since the barrier layer 14 exhibits a good (111) orientation, an iridium film having a good (111) orientation can also be obtained for the first electrode 32.

  Next, a ferroelectric layer 34 is formed on the first electrode 32 by forming a PZT film having a film thickness of, for example, 100 nm using a spin-on method, a sputtering method, an MOCVD method, or the like. As described above, since the iridium film of the first electrode 32 exhibits a good (111) orientation, a PZT film having a good (111) orientation can also be obtained for the ferroelectric layer 34. When the content of titanium in PZT is larger than the content of zirconium, the crystal orientation of PZT is preferably a (111) orientation in terms of good hysteresis characteristics. Therefore, by setting the crystal orientation of the barrier layer 14 to the (111) orientation, both the first electrode 32 and the ferroelectric layer 34 can be set to the (111) orientation. Therefore, the ferroelectric capacitor 30 having excellent hysteresis characteristics. Can be obtained.

Next, on the ferroelectric layer 34, for example, a second electrode 36 made of a laminated film of an iridium oxide film having a thickness of 100 nm and an iridium film having a thickness of 100 nm is formed. A method of forming the second electrode 36 can be selected as appropriate according to the material of the second electrode 36, and examples thereof include a sputtering method and a CVD method.
When the formation of the above layers is completed, a resist layer having a predetermined pattern is formed on the second electrode 36, and patterning is performed by photolithography using the resist layer R1 as a mask. Thereby, the semiconductor device 100 including the stacked ferroelectric capacitor 30 is obtained (see FIG. 1). The ferroelectric capacitor 30 included in the semiconductor device 100 includes a first electrode 32 provided on the barrier layer 14, a ferroelectric layer 34 provided on the first electrode 32, and the ferroelectric layer 34. And a second electrode 36.

In addition, when the conductive connection structure to the second electrode 36 is further formed in the semiconductor device 100, the following steps may be further performed.
First, a hydrogen barrier film covering the ferroelectric capacitor 30 formed on the substrate 10 is formed by depositing aluminum oxide (AlOx) using a sputtering method or an ALD (Atomic Layer Deposition) method. Next, an interlayer insulating film that covers the hydrogen barrier film is formed by forming a silicon oxide film using PE-TEOS or HDP (high density plasma CVD), and the surface of the formed silicon oxide film is subjected to CMP. Flatten by processing. When the interlayer insulating film is formed, a through hole reaching the second electrode 36 through the interlayer insulating film and the hydrogen barrier film is formed by a photolithography method and a dry etching method. By forming the first base layer, the second base layer, and the plug conductive layer by the same formation method, a plug that contacts the ferroelectric capacitor 30 can be formed.

As described above, according to the manufacturing method of the semiconductor device 100 of this aspect, the following operational effects are obtained.
First, a second conductive film 21 made of a conductive material containing silicon, such as silicon-containing titanium nitride or silicon-containing titanium alloy nitride, is formed on the plug conductive layer 22, and interlayer insulation including the second conductive film 21 is included. Since the NH ₃ plasma treatment is performed on the region on the film 26, the surface modification action by the NH 3 plasma treatment is also performed on the surface portion 21 a of the second conductive film 21 by the action of silicon contained in the second conductive film 21. It can function effectively. Thereby, the titanium layer 12a can be satisfactorily c-axis oriented not only on the surface of the interlayer insulating film 26 made of silicon oxide but also on the surface of the second conductive film 21, and on the titanium nitride layer 12 obtained by nitriding the titanium layer 12a In addition, the barrier layer 14, the first electrode 32, and the ferroelectric layer 34 having preferable crystal orientation can be formed. Thereby, the ferroelectric capacitor 30 having excellent hysteresis characteristics can be formed.

  Further, by embedding the second conductive film 21 in the recess 24a formed when the plug conductive layer 22 is embedded in the through hole 24, the surface on which the titanium nitride layer 12 is formed can be satisfactorily flattened. In addition, it is possible to prevent the crystal orientation of the constituent layer of the ferroelectric capacitor 30 from being lowered due to unevenness on the substrate.

  Further, the titanium layer 12a formed on the plug 20 is subjected to RTA treatment in an atmosphere containing nitrogen to convert the titanium layer 12a to the titanium nitride layer 12. Therefore, the titanium nitride layer 12 has good crystal orientation. Further, the crystal orientation of the barrier layer 14 formed on the titanium nitride layer 12 can also be improved. In addition, since the titanium layer 12a is converted into the titanium nitride layer 12 in advance by the RTA treatment, in a later process (for example, recovery annealing (heat treatment in an oxygen atmosphere) for recovering the characteristics of the ferroelectric layer 34), The titanium nitride layer 12 can be prevented from being oxidized.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 4 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 5 is a cross-sectional process diagram for explaining a manufacturing process of the semiconductor device of this embodiment.
The semiconductor device 200 of this embodiment has the same basic configuration as that of the semiconductor device according to the first embodiment, and has only a difference in the layer configuration on the plug conductive layer 22. Accordingly, in FIG. 4 and FIG. 5, the same components as those shown in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the semiconductor device 200 of this embodiment, as shown in FIG. 4, the plug 20 provided in the through hole 24 is formed with a plug conductive layer 22 and a base conductive film formed in a recess 24 a on the plug conductive layer 22. 23 and a second conductive film 21 formed in a region surrounded by the base conductive film 23. By forming the base conductive film 23, the semiconductor device 200 of the present embodiment can make the conduction between the switching transistor 18 and the ferroelectric capacitor 30 better.

  As described above, the second conductive film 21 is formed of a conductive material containing silicon, for example, silicon-containing titanium nitride (TiN or the like) or silicon-containing titanium alloy nitride (TiAlN or the like). The resistance tends to be higher when compared with no conductive material (TiN, TiAlN) or the like. Therefore, even a thin film of about 30 nm may cause poor contact conduction. Therefore, in the present embodiment, a base conductive film 23 made of a conductive material not containing silicon having a thickness of less than 10 nm (about several nm) is formed between the plug conductive layer 22 and the second conductive film 21, so that the second conductive The recess in which the film 21 is embedded is shallow. Thereby, since the film thickness of the second conductive film 21 can be reduced, the resistance of the second conductive film 21 can be reduced, the occurrence of contact conduction failure can be effectively prevented, and the manufacturing yield of the semiconductor device can be improved. It contributes to the structure.

  The underlying conductive film 23 can be formed of, for example, titanium nitride (TiN or the like) that does not contain silicon or titanium alloy nitride grains (TiAlN or the like). The constituent material of the second conductive film 21 (silicon-containing titanium nitride or silicon) It is preferable to use the same material as that obtained by removing silicon from (containing titanium alloy nitride). For example, when the second conductive film 21 is made of TiN containing silicon, the base conductive film 23 is preferably a conductive film made of TiN. By setting it as such a structure, the adhesiveness and crystal orientation of the base conductive film 23 and the 2nd conductive film 21 can be improved easily.

Next, a method for manufacturing the semiconductor device 200 of this embodiment will be described with reference to FIG.
First, the switching transistor 18 and the like are formed on the semiconductor substrate 10, and the through hole 24 is formed in the interlayer insulating film 26 formed so as to cover the switching transistor 18 and the like. Thereafter, the first base layer 22 a, the second base layer 22 b, and the plug conductive layer 22 are embedded in the through hole 24. Since the above process is the same as that of the manufacturing method according to the first embodiment, details are not described here.

When the plug conductive layer 22 is formed in the through hole 24, a base conductive film 23a made of, for example, titanium nitride (TiN or the like) is formed on the entire surface of the substrate 10 as shown in FIG. The film thickness of the underlying conductive film 23 a is set to a film thickness (for example, several nm) that does not fill the recess 24 a on the plug conductive layer 22.
Next, as shown in FIG. 5B, a second conductive film 121 made of, for example, silicon-containing titanium nitride is formed to a thickness of about 100 nm to 500 nm on the entire surface of the base conductive film 23a.

  Next, the substrate 10 on which the second conductive film 121 and the base conductive film 23a are formed is subjected to a CMP process, whereby the second conductive film 121 and the base conductive film 23a on the interlayer insulating film 26 are removed, and the inside of the recess 24a. The base conductive film 23 and the second conductive film 21 are embedded in the substrate. The surfaces of the interlayer insulating film 26 and the second conductive film 21 that have undergone these steps are extremely flattened.

Next, as shown in FIG. 5D, the surface of the interlayer insulating film 26 and the second conductive film 21 is subjected to NH ₃ plasma treatment. As a result, NH x groups derived from NH ₃ are bonded to the surface of the interlayer insulating film 26 and the surface portion 21 a of the second conductive film 21. After that, as in the first embodiment, if titanium is formed on the interlayer insulating film 26 including the second conductive film 21, the migration of titanium is promoted by the surface modification effect of the NH ₃ plasma treatment. The (002) -oriented titanium layer 12a can be formed (see FIG. 3). Subsequent processes are the same as those in the method for manufacturing the semiconductor device 100 according to the first embodiment, and thus the description thereof is omitted.

  The semiconductor devices (ferroelectric memory devices) 100 and 200 include mobile phones, personal computers, liquid crystal devices, electronic notebooks, pagers, POS terminals, IC cards, minidisc players, liquid crystal projectors, and engineering workstations ( EWS), word processor, television, view finder type or monitor direct view type video tape recorder, electronic desk calculator, car navigation device, device with touch panel, watch, game device, electrophoresis device, etc. Can do.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. Sectional process drawing for demonstrating the manufacturing method of a semiconductor device. Sectional process drawing for demonstrating the manufacturing method of a semiconductor device. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. Sectional process drawing for demonstrating the manufacturing method of a semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Semiconductor device (ferroelectric memory device), 10 Semiconductor substrate, 12 Titanium nitride layer, 14 Barrier layer, 18 Switching transistor, 20 Plug, 21 2nd electrically conductive film, 21a Surface part, 22 Plug electrically conductive layer (1st electrically conductive film) ), 22a First base layer, 22b Second base layer, 23 Base conductive film, 26 Interlayer insulating film, 30 Ferroelectric capacitor, 32 First electrode, 34 Ferroelectric layer, 36 Second electrode

Claims (5)

A semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate,
The plug has a plug conductive layer in which the first conductive film is embedded in the through hole,
In the recess formed on the plug conductive layer, a base conductive film made of a titanium nitride film or a titanium alloy nitride film and having a thickness smaller than the depth of the recess is formed to cover the inner surface of the recess. ,
A second conductive film made of a titanium nitride film containing silicon or a titanium alloy nitride film containing silicon is embedded in a region surrounded by the base conductive film,
A semiconductor device, wherein a third conductive film made of a titanium nitride film having a (111) orientation is formed on the second conductive film.   The semiconductor device according to claim 1, wherein the base conductive film has a composition obtained by removing silicon from the constituent components of the second conductive film.   The semiconductor device according to claim 1, wherein a film thickness of the base conductive film is 10 nm or less. A method of manufacturing a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate,
Forming a through hole in an interlayer insulating film on the substrate;
Forming a plug conductive layer by embedding a first conductive film in the through hole;
Forming a base conductive film made of a titanium nitride film or a titanium alloy nitride film on the interlayer insulating film including the recess formed on the plug conductive layer to a thickness smaller than the depth of the recess; When,
Forming a second conductive film made of a titanium nitride film containing silicon or a titanium alloy nitride film containing silicon on the base conductive film;
Embedding the base conductive film and the second conductive film in a recess on the plug conductive layer by performing a CMP process on the second conductive film and the base conductive film;
Exciting and irradiating plasma of a gas having a molecular structure in which nitrogen and hydrogen are bonded to the upper surface of the second conductive film and the surface of the interlayer insulating film;
Forming a third conductive film made of a titanium nitride film having a (111) orientation in a region including an upper surface of the second conductive film irradiated with the plasma;
A method for manufacturing a semiconductor device, comprising: Forming the third conductive film comprises :
Forming a titanium layer in a region including the upper surface of the second conductive film, a step of converting the titanium layer to titanium nitride layer after the formation of the titanium layer by heat treatment under a nitrogen atmosphere, to have a The method of manufacturing a semiconductor device according to claim 4 , wherein:

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