JP4834372B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to an integrated liquid crystal display device in which signal lines of two liquid crystal panels are controlled by one signal line driving circuit.

  Currently, a liquid crystal display device mounted on a mobile phone terminal or the like has two liquid crystals: a main liquid crystal screen with high resolution and good color, and a small sub-liquid crystal screen that displays limited information such as time and remaining battery power. Those with a screen have become mainstream. In such a configuration, if each of the two liquid crystal panels includes a liquid crystal module such as a signal line dynamic circuit, there is a problem that a mounting area increases.

  On the other hand, in recent years, in a liquid crystal display device, two liquid crystal panels formed on different substrates are combined, and in one liquid crystal panel, a signal line used in common with the other liquid crystal panel is used, A technique for controlling two liquid crystal panels with one signal line driving circuit is disclosed (for example, see Patent Document 1).

  FIG. 6 is a plan view for explaining the configuration of signal lines in a conventional liquid crystal display device in which two liquid crystal panels are combined. As shown in the figure, for example, the liquid crystal display device includes a main liquid crystal panel 1, a sub liquid crystal panel 2, and a signal line driving circuit 6.

  The main liquid crystal panel 1 has 240 main signal lines 7a for each of RGB, for example. The sub liquid crystal panel 2 has, for example, 120 sub signal lines 7b for each of RGB. The sub signal lines 7 b are connected to 120 main signal lines 7 a for each of RGB in the main liquid crystal panel 1.

With this configuration, the signal line driving circuit 6 drives the main signal line 7a when writing a video signal to the main liquid crystal panel 1, and the main signal line 7a when writing a video signal to the sub liquid crystal panel 2. The sub signal line 7b connected to is driven.
JP 2004-61892 A

  However, when the number of signal lines is different between the two liquid crystal panels as in the above configuration, the main signal line 7a may or may not be connected to the sub signal line 7b, and the main signal line 7a. The wiring length is different. Therefore, when halftone video display is performed on the main liquid crystal panel 1, the potential of the video signal written to each pixel fluctuates due to the difference in wiring capacitance caused by different wiring lengths of the main signal line 7a. Unevenness occurs on the display screen.

  On the other hand, for example, a switch is provided at the terminal portion of the main signal line 7a connected to the sub signal line 7b, and when the video signal is written to the main liquid crystal panel 1, the switch is closed to wire the main signal line 7a. There is a way to align the length.

  However, since the sub signal line 7b is in a floating state in the period when the switch is closed, there is a problem that the potential of the sub signal line 7b is likely to fluctuate and the display screen of the sub liquid crystal panel 2 is uneven.

  The present invention has been made in view of the above, and in an integrated liquid crystal display device in which two liquid crystal panels are controlled by one signal line driving circuit, display caused by signal lines commonly used by both panels. It is an object to suppress unevenness.

  A liquid crystal display device according to a first aspect of the present invention includes a first liquid crystal panel having a plurality of first signal lines, a second liquid crystal panel having a plurality of second signal lines, and a common potential supply line to which a common potential is supplied. A first switch for switching between electrically connecting or disconnecting the end of the first signal line and the start of the second signal line, and electrically connecting the end of the second signal line and the common potential supply line When writing a video signal to the first liquid crystal panel, the second switch for switching between connection and disconnection and the end of the first signal line and the start of the second signal line are disconnected by the first switch, and the second switch A signal line for writing the video signal to the first signal line and supplying the common potential to the second signal line through the common potential supply line after the end of the second signal line and the common potential supply line are connected by the switch And a driving circuit.

  In the present invention, when the video signal is written to the first liquid crystal panel, the second signal line is disconnected from the first signal line by the first switch, and the second signal line is made the common potential supply line by the second switch. After the connection, the signal line driver circuit supplies a common potential to the second signal line through the common potential supply line, whereby the potential of the second signal line in the floating state is fixed to the common potential.

  The first signal line in the liquid crystal display device includes two types of signal lines, a connected first signal line connected to the first switch and an unconnected first signal line not connected to the first switch. One signal line and the unconnected first signal line have a uniform length.

  In the present invention, in the first liquid crystal panel, the two types of wiring lengths of the connected first signal line connected to the first switch and the unconnected first signal line not connected to the first switch are uniform. The potential of the video signal written by the signal line driver circuit is prevented from fluctuating due to the wiring capacity of the signal lines having different lengths.

  In the signal line driving circuit in the liquid crystal display device, when the video signal is written to the second liquid crystal panel, the terminal of the connection first signal line and the start of the second signal line are connected by the first switch. After the end of the second signal line and the common potential supply line are disconnected by the switch, the video signal is written to the second signal line via the connected first signal line and the common potential is supplied to the unconnected first signal line. It is characterized by doing.

  In the present invention, when writing a video signal to the second liquid crystal panel, the signal line driving circuit supplies the common potential to the unconnected first signal line that is not connected to the first switch, so that the second liquid crystal panel is in a floating state. The potential of the unconnected first signal line is fixed to the common potential.

  The common potential is within a voltage amplitude range of the video signal. As a result, in the period in which the video signal is not written to the second signal line and the unconnected first signal line, the signal line in the floating state is fixed to the common potential at the same level as the video signal.

  The signal line driver circuit in the display device supplies a common potential for at least one horizontal scanning period. As a result, the second signal line and the unconnected first signal line in a floating state are fixed at a common potential.

  According to the liquid crystal display device of the present invention, it is possible to suppress display unevenness caused by signal lines used in common in two liquid crystal panels controlled by one signal line driving circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a plan view showing a schematic configuration of the liquid crystal display device according to the first embodiment. As shown in the figure, the liquid crystal display device is an active matrix type color liquid crystal display device having a main liquid crystal panel 1 and a sub liquid crystal panel 2. The two liquid crystal panels are connected via a flexible printed circuit board 3 (hereinafter referred to as FPC), and are arranged back to back at the time of mounting with a backlight (not shown) interposed therebetween.

  The main liquid crystal panel 1 is a QVGA liquid crystal display panel having a main display region 4 in which 320 RGB pixels in the vertical direction and 240 RGB pixels in the horizontal direction are arranged in a matrix. The sub liquid crystal panel 2 is a QVGA liquid crystal display panel having a sub display area 5 in which 120 RGB pixels in the vertical direction and 120 RGB pixels in the horizontal direction are arranged in a matrix.

  The signal line driving circuit 6 is mounted on the outside of the main display area 4 of the main liquid crystal panel 1 by the COG (Chip On Glass) technology, and each signal line of the main liquid crystal panel 1 and the sub liquid crystal panel 2 formed on different substrates. Drive.

  Next, a configuration for supplying a common potential to the signal lines of each liquid crystal panel, which is a feature of the present invention, will be described with reference to FIG. FIG. 2 is a plan view schematically showing the configuration of signal lines in each liquid crystal display panel of the liquid crystal display device of FIG.

  As shown in the figure, the liquid crystal display device includes a main liquid crystal panel 1, a sub liquid crystal panel 2, a common potential supply line 8, analog switches 9a and 9b, an analog switch 10, an analog switch 11, and a signal line. It has a drive circuit 6 and a scanning line drive circuit (not shown). Here, for example, the analog switches 9a, 9b, 10, and 11 are formed on each substrate of the liquid crystal panel by polycrystalline silicon thin film transistors.

  The main liquid crystal panel 1 has 240 main signal lines 7a wired in parallel to each other. Here, for example, each main signal line 7a is composed of three signal lines for each of RGB. In the main display area 4, although not shown, pixels are arranged at each intersection of the plurality of main signal lines 7a and the plurality of scanning lines intersecting each other. Here, the main signal line 7a is wired with a uniform length, and there are two types, one connected to the sub signal line 7b by the analog switches 9a and 9b and the other not connected.

  The sub liquid crystal panel 2 has 120 sub signal lines 7b wired in parallel to each other. Here, for example, each sub signal line 7b is composed of three signal lines for each of RGB. In the sub display area 5, although not shown, pixels are arranged at each intersection of the plurality of sub signal lines 7b and the plurality of scanning lines intersecting each other.

  The common potential supply line 8 is connected to the end of the sub signal line 7 b through the analog switch 10, and a common potential is supplied by the signal line driving circuit 6.

  120 analog switches 9a and 9b are arranged corresponding to the signal lines connected to the upper side of the main liquid crystal panel 1 and the lower side of the sub liquid crystal panel 2, respectively, and the end of the main signal line 7a and the start of the sub signal line 7b are connected. Switch between electrical connection and disconnection.

  120 analog switches 10 are arranged on the upper side of the sub liquid crystal panel 2 so as to correspond to the sub signal lines 7b, and the termination of the sub signal lines 7b and the common potential supply line 8 are electrically connected or disconnected. Switch.

  Here, at the time of connection, the analog switch 9a sequentially selects and drives three main signal lines 7a for R, G, and B with respect to the main sub-common wiring 12 by a signal line selection signal from the signal line driving circuit 6.

  Similarly, in the analog switch 9b, at the time of connection, three sub signal lines 7b for each of R, G, and B are sequentially selected and driven with respect to the main sub-common wiring 12 by a signal line selection signal from the signal line driving circuit 6.

  240 analog switches 11 are arranged corresponding to the main signal line 7 a between each output line of the signal line drive circuit 6 and the start end of each main signal line 7 a, and a signal line selection signal from the signal line drive circuit 6. In synchronism with this, three main signal lines 7a for R, G, and B are sequentially selected and driven for the output lines of the signal line driving circuit 6.

  As described above, the signal lines are selectively driven by the analog switches 9a, 9b, and 11 to reduce the number of connection wirings between the liquid crystal panels and to reduce the area occupied by the signal lines in the liquid crystal panel.

  When the video signal is written to the main liquid crystal panel 1, the signal line driving circuit 6 disconnects the end of the main signal line 7a from the start of the sub signal line 7b by the analog switches 9a and 9b, and the sub signal line by the analog switch 10. After the end of 7b is connected to the common potential supply line 8, a video signal is written to the main signal line 7a and a common potential is supplied to the end of the sub signal line 7b via the common potential supply line 8.

  Further, when writing a video signal to the sub liquid crystal panel 2, the end of the main signal line 7a and the start of the sub signal line 7b are connected by the analog switches 9a and 9b, and the end of the sub signal line 7b is shared by the analog switch 10. After the potential supply line 8 is disconnected, a video signal is written to the sub signal line 7b via the main signal line 7a, and a common potential is supplied to the unconnected main signal line 7a. Here, for example, the common potential is a halftone potential.

  Next, an operation of supplying a common potential to the main signal line and the sub signal line will be described with reference to the timing chart of FIG. This figure is a timing chart showing the relationship among the states of each analog switch, signal line, and drive circuit in one frame period. Here, in one frame period, video signal writing to the main liquid crystal panel 1 and video signal writing to the sub liquid crystal panel 2 are sequentially performed. Note that writing to each liquid crystal panel is performed by a horizontal line inversion driving method in which the polarity of the voltage applied to each pixel is inverted for each adjacent scanning line within one frame period.

  At time t1, one frame period is started, and the scanning line driving circuit for driving the main and sub liquid crystal panels is stopped (blanking period). In this period, for example, the potential of the sub signal line 7b of the sub liquid crystal panel 2 is fixed.

  First, in response to a control signal for turning off the analog switch from the signal line driving circuit 6, the analog switches 9a and 9b cut off the end of the main signal line 7a and the start of the sub signal line 7b. On the other hand, the analog switch 10 electrically connects the terminal of the sub signal line 7 b and the common potential supply line 8 by a control signal for turning on the analog switch from the signal line driving circuit 6.

  Then, the signal line driving circuit 6 supplies a common potential to the end of the sub signal line 7 b through the common potential supply line 8. Thereby, the potential of the sub signal line 7b in the floating state is fixed to the common potential.

  At this time, in the main liquid crystal panel 1, the scanning line driving circuit for the main liquid crystal panel is in a stopped state, but the signal line driving circuit 6 sequentially drives the analog switch 11 to select three, and the main signal line 7a is normally driven. Driving the main signal line 7a prevents the main signal line 7a from being in a floating state.

  At time t2, writing to the main liquid crystal panel 1 is started. The scanning lines are sequentially driven by the main liquid crystal panel scanning line driving circuit, and a video signal is written from the signal line driving circuit 6 to the main signal line 7a. At this time, in synchronization with the signal line selection signal from the signal line driving circuit 6, the analog switch 11 sequentially selects three main signal lines 7 a for each of R, G, and B for each output line of the signal line driving circuit 6. To drive.

  Here, since the two types of wiring lengths of the main signal line 7a connected to the analog switch 9a and the main signal line 7a not connected are uniform, the potential of the video signal written by the signal line driving circuit 6 in each pixel. However, fluctuations due to the wiring capacities of signal lines having different lengths are prevented.

  On the other hand, in the sub liquid crystal panel 2, the scanning line drive circuit for the sub liquid crystal panel is maintained in a stopped state, the analog switches 9a and 9b are off, the analog switch 10 is kept on, and the sub signal line 7b The potential remains fixed at the common potential.

  At time t3, the analog switches 9a and 9b connect the end of the main signal line 7a and the start of the sub signal line 7b by a control signal for turning on the analog switch from the signal line driving circuit 6. On the other hand, the analog switch 10 disconnects the terminal of the sub signal line 7b and the common potential supply line 8 by a control signal for turning off the analog switch from the signal line driving circuit 6.

  At time t4, writing to the sub liquid crystal panel 2 is started. The scanning lines are sequentially driven by the scanning line driving circuit for the sub liquid crystal panel, and the video signal is transmitted from the signal line driving circuit 6 via the main signal line 7a connected to the starting end of the sub signal line 7b by the analog switches 9a and 9b. Written. At this time, in synchronization with the signal line selection signal from the signal line drive circuit 6, the analog switches 9a and 9b and the analog switch 11 sequentially select and drive three signal lines for each of RGB.

  On the other hand, the signal line driving circuit 6 supplies a common potential to the main signal line 7a not connected to the analog switches 9a and 9b. Thereby, in the main liquid crystal panel 1, the potential of the main signal line 7a in the floating state is fixed to the common potential.

  At time t5, writing to the sub liquid crystal panel 2 is completed, and the sub liquid crystal panel scan line drive circuit stops operating following the main liquid crystal panel scan line drive circuit, and a blanking period starts. During the blanking period, the potential of the sub signal line 7b of the sub liquid crystal panel 2 is fixed as in the process at time t1. In response to a control signal for turning off the analog switch from the signal line driving circuit 6, the analog switches 9a and 9b disconnect the terminal end of the main signal line 7a and the starting end of the sub signal line 7b. On the other hand, the analog switch 10 electrically connects the terminal of the sub signal line 7b and the common potential supply line 8 by a control signal for turning on the switch from the signal line driving circuit 6.

  Then, a common potential is supplied from the signal line driving circuit 6 to the end of the sub signal line 7 b through the common potential supply line 8. Thereby, the potential of the sub signal line 7b in the floating state is fixed to the common potential.

  Therefore, according to the first embodiment, when the video signal is written to the main liquid crystal panel 1, the sub signal line 7b is disconnected from the main signal line 7a by the analog switches 9a and 9b, and the sub signal line is output by the analog switch 10. After connecting 7b to the common potential supply line 8, the common potential is supplied to the sub signal line 7b through the common potential supply line 8 by the signal line driving circuit 6, so that the sub signal line 7b in the floating state is supplied. Is fixed at a common potential.

  Further, in the main liquid crystal panel 1, the signal line driving circuit 6 makes the two types of wiring lengths of the main signal line 7a connected to the analog switch 9a and the main signal line 7a not connected to the analog switch 9a uniform. It is possible to prevent the potential of the written video signal from fluctuating due to the wiring capacity of the signal lines having different lengths.

  Further, when a video signal is written to the sub liquid crystal panel 2, a common potential is also supplied to the main signal line 7a not connected to the analog switches 9a and 9b by the signal line driving circuit 6 in the main liquid crystal panel 1. The potential of the main signal line 7a in the floating state is fixed to the common potential.

  Therefore, display unevenness caused by signal lines used in common in two liquid crystal panels controlled by one signal line driver circuit can be suppressed.

[Second Embodiment]
The display device according to the second embodiment will be described below.

  The basic configuration of the liquid crystal display device in the second embodiment is the same as that described in the first embodiment. The difference from the first embodiment is that not only the common potential supply line 8b is connected to the sub signal line 7b via the analog switch 10, but also the common potential supply line 8a is connected to the RGB signal via the analog switch 9a. Each point is connected to two of the three main signal lines 7a. Below, it demonstrates centering on a different point from 1st Embodiment, and abbreviate | omits description about the already demonstrated point.

  Next, a configuration for supplying a common potential to the signal lines of each liquid crystal panel, which is a feature of the present invention, will be described with reference to FIG. This figure is a plan view for explaining the configuration of signal lines in each liquid crystal display panel of the liquid crystal display device according to the second embodiment.

  As shown in the figure, the liquid crystal display device includes a main liquid crystal panel 1, a sub liquid crystal panel 2, common potential supply lines 8a and 8b, analog switches 9a and 9b, an analog switch 10, an analog switch 11, And a signal line driver circuit 6. Here, for example, the analog switches 9a, 9b, 10, and 11 are formed of polycrystalline silicon thin film transistors.

  The common potential supply lines 8 a and 8 b are supplied with a common potential from the signal line driving circuit 6. The common potential supply line 8a is connected to two terminal ends of the three main signal lines 7a for R, G, and B through an analog switch 9a. The common potential supply line 8b is connected to the end of the sub signal line 7b through the analog switch 10.

  120 analog switches 9a and 9b are arranged corresponding to the signal lines connected to the upper side of the main liquid crystal panel 1 and the lower side of the sub liquid crystal panel 2, respectively, and the end of the main signal line 7a and the start of the sub signal line 7b are connected. Switch between electrical connection and disconnection.

  120 analog switches 10 are arranged on the upper side of the sub liquid crystal panel 2 so as to correspond to the sub signal lines 7b, and the termination of the sub signal lines 7b and the common potential supply line 8 are electrically connected or disconnected. Switch.

  Here, the analog switch 9a is set so that, for example, an R signal line among the three RGB main signal lines 7a is always selected for the main / sub common line 12 when connected.

  Further, when connected, the analog switch 9b sequentially selects and drives three sub-signal lines 7b for each of R, G, and B with respect to the main sub-common wiring 12 by a signal line selection signal from the signal line driving circuit 6.

  240 analog switches 11 are arranged corresponding to the main signal lines 7a between the output lines of the signal line driving circuit 6 and the start ends of the main signal lines 7a, and at the time of writing to the main liquid crystal panel 1, In synchronization with the signal line selection signal from the signal line driving circuit 6, three main signal lines 7 a for RGB are sequentially selected and driven for each output line of the signal line driving circuit 6. At the time of writing to the sub liquid crystal panel 2, for example, the R signal line among the three RGB main signal lines 7a is always selected.

  When the video signal is written to the main liquid crystal panel 1, the signal line driving circuit 6 disconnects the end of the main signal line 7a from the start of the sub signal line 7b by the analog switches 9a and 9b, and the sub signal line by the analog switch 10. After the end of 7b and the common potential supply line 8 are connected, a video signal is written to the main signal line 7a and a common potential is supplied to the end of the sub signal line 7b via the common potential supply line 8b.

  Further, when writing a video signal to the sub liquid crystal panel 2, the end of the main signal line 7a and the start of the sub signal line 7b are connected by the analog switches 9a and 9b, and the end of the sub signal line 7b is shared by the analog switch 10. After the potential supply line 8 is disconnected, a video signal is written to the sub signal line 7b via the main signal line 7a, and a common potential is supplied to the unconnected main signal line 7a. Here, for example, the common potential is a halftone potential.

  Next, an operation for supplying a common potential to the main signal line and the sub signal line will be described with reference to a timing chart of FIG. This figure is a timing chart showing the relationship among the states of each analog switch, signal line, and drive circuit in one frame period. Here, in one frame period, video signal writing to the main liquid crystal panel 1 and video signal writing to the sub liquid crystal panel 2 are sequentially performed. Note that writing to each liquid crystal panel is performed by a horizontal line inversion driving method in which the polarity of the voltage applied to each pixel is inverted for each adjacent scanning line within one frame period.

  At time t1, one frame period is started, and the scanning line driving circuit for driving the main and sub liquid crystal panels is stopped (blanking period). In this period, for example, the potential of the sub signal line 7b of the sub liquid crystal panel 2 is fixed.

  First, in response to a control signal for turning off the analog switch from the signal line driving circuit 6, the analog switches 9a and 9b cut off the end of the main signal line 7a and the start of the sub signal line 7b. On the other hand, the analog switch 10 electrically connects the terminal of the sub signal line 7b and the common potential supply line 8b by a control signal for turning on the analog switch from the signal line driving circuit 6.

  Then, a common potential is supplied from the signal line driving circuit 6 to the end of the sub signal line 7 b via the common potential supply line 8. Thereby, the potential of the sub signal line 7b in the floating state is fixed to the common potential.

  At this time, in the main liquid crystal panel 1, the scanning line driving circuit for the main liquid crystal panel is in a stopped state, but the signal line driving circuit 6 sequentially drives the analog switch 11 to select three, and the main signal line 7a is normally driven. Driving the main signal line 7a prevents the main signal line 7a from being in a floating state.

  At time t2, writing to the main liquid crystal panel 1 is started. The scanning lines are sequentially driven by the main liquid crystal panel scanning line driving circuit, and a video signal is written from the signal line driving circuit 6 to the main signal line 7a. At this time, in synchronization with the signal line selection signal from the signal line drive circuit 6, the analog switch 11 sequentially selects and drives the three main signal lines 7 a for each of RGB for each output line of the signal line drive circuit 6. To do.

  Here, since the two types of wiring lengths of the main signal line 7a connected to the analog switch 9a and the main signal line 7a not connected are uniform, the potential of the video signal written by the signal line driving circuit 6 in each pixel. However, fluctuations due to the wiring capacities of signal lines having different lengths are prevented.

  On the other hand, in the sub liquid crystal panel 2, the scanning line drive circuit for the sub liquid crystal panel is maintained in a stopped state, the analog switches 9a and 9b are off, the analog switch 10 is kept on, and the sub signal line 7b The potential remains fixed at the common potential.

  At time t3, the analog switches 9a and 9b connect the end of the main signal line 7a and the start of the sub signal line 7b by a control signal for turning on the analog switch from the signal line driving circuit 6. Here, the analog switch 9a is set so that, for example, an R signal line among the three RGB main signal lines 7a is always selected for the main sub-common wiring 12. The analog switch 9b sequentially selects and drives three sub signal lines 7b for R, G, and B for the main sub-common wiring 12 in response to a signal line selection signal from the signal line drive circuit 6.

  Further, the analog switch 11 is set so that, for example, an R signal line is always selected among the three RGB main signal lines 7a.

  On the other hand, the analog switch 10 disconnects the end of the sub signal line 7b and the common potential supply line 8b by a control signal for turning off the switch from the signal line driving circuit 6.

  At time t4, writing to the sub liquid crystal panel 2 is started. The scanning lines are sequentially driven by the scanning line driving circuit for the sub liquid crystal panel, and the video signal is transmitted from the signal line driving circuit 6 via the main signal line 7a connected to the starting end of the sub signal line 7b by the analog switches 9a and 9b. Written.

  At this time, in synchronization with the signal line selection signal from the signal line driving circuit 6, the analog switch 9b sequentially selects and drives three signal lines for each of RGB. The settings of the analog switch 9a and the analog switch 11 are fixed, and the R main signal line 7a is always selected.

  On the other hand, the signal line driving circuit 6 supplies the common potential from the common potential supply line 8a to the two main signal lines 7a corresponding to G and B via the analog switch 9a. Thereby, in the main liquid crystal panel 1, the potential of the main signal line 7a in the floating state is fixed to the common potential.

  At time t5, writing to the sub liquid crystal panel 2 is completed, and the sub liquid crystal panel scan line drive circuit stops operating following the main liquid crystal panel scan line drive circuit, and a blanking period starts. During the blanking period, the potential of the sub signal line 7b of the sub liquid crystal panel 2 is fixed as in the process at time t1. In response to a control signal for turning off the analog switch from the signal line driving circuit 6, the analog switches 9a and 9b disconnect the terminal end of the main signal line 7a and the starting end of the sub signal line 7b. On the other hand, the analog switch 10 electrically connects the terminal of the sub signal line 7b and the common potential supply line 8b by a control signal for turning on the switch from the signal line driving circuit 6.

  Then, a common potential is supplied from the signal line driving circuit 6 to the end of the sub signal line 7b through the common potential supply line 8b. Thereby, the potential of the sub signal line 7b in the floating state is fixed to the common potential.

  Therefore, according to the second embodiment, when the video signal is written in the main liquid crystal panel 1, the sub signal line 7b is disconnected from the main signal line 7a by the analog switches 9a and 9b, and the sub signal line is output by the analog switch 10. After connecting 7b to the common potential supply line 8, the signal line driving circuit 6 supplies a common potential to the sub signal line 7b via the common potential supply line 8b, so that the sub signal line 7b in the floating state is supplied. Is fixed at a common potential.

  Further, in the main liquid crystal panel 1, the signal line driving circuit 6 makes the two types of wiring lengths of the main signal line 7a connected to the analog switch 9a and the main signal line 7a not connected to the analog switch 9a uniform. It is possible to prevent the potential of the written video signal from fluctuating due to the wiring capacity of the signal lines having different lengths.

  Further, when writing a video signal to the sub liquid crystal panel 2, in the main liquid crystal panel 1, the signal line driving circuit 6 causes the signal line driving circuit 6 to connect two lines corresponding to G and B from the common potential supply line 8a via the analog switch 9a. By supplying a common potential to the main signal line 7a, the potential of the main signal line 7a in a floating state is fixed to the common potential.

  Therefore, display unevenness caused by signal lines used in common in two liquid crystal panels controlled by one signal line driver circuit can be suppressed.

  In each of the above embodiments, the common potential is a halftone specific potential. However, the common potential is not limited to this and may be within the range of the voltage amplitude of the video signal. Can be fixed at a specific potential.

  In each of the above embodiments, the period during which the common potential is supplied to the sub signal line is the blanking period during which the sub liquid crystal panel is not driven and the period during which the main liquid crystal panel is written, and the period during which the common potential is supplied to the main signal line. Is a period for writing to the sub liquid crystal panel. However, the present invention is not limited to this. The signal line in the floating state can be fixed to a specific potential by supplying at least a common potential for one horizontal scanning period or more.

  In addition, in each of the above embodiments, the signal line driving circuit is configured to be mounted on the main liquid crystal panel by COG. However, the present invention is not limited to this, and for example, the same process as the signal line, the analog switch, etc. Thus, it may be formed integrally on the same substrate of either one of the liquid crystal panels by a polycrystalline silicon thin film transistor.

  In each of the above embodiments, the signal line driver circuit is configured to supply the common potential to the main signal line and the sub signal line. However, the present invention is not limited to this, and each liquid crystal panel has a dedicated potential. A circuit may be formed and a common potential may be supplied from these circuits.

  Further, in each of the above-described embodiments, the analog switch is configured to sequentially select and drive three signal lines for each of RGB, thereby reducing the number of connection wires between the liquid crystal panels and occupying the signal lines in the liquid crystal panel. Although the area is reduced, the number of signal lines to be selectively driven may be any integer as long as it is an integer equal to or greater than 2. For example, the configuration may be such that six signal lines are selectively driven by analog switches. .

1 is a plan view showing a schematic configuration of a liquid crystal display device according to a first embodiment. FIG. 2 is a plan view schematically illustrating a configuration of signal lines in each liquid crystal display panel of the liquid crystal display device of FIG. 1. 3 is a timing chart showing a relationship among states of analog switches, signal lines, and scanning line driving circuits in one frame period in each liquid crystal panel of FIG. 2. It is the top view which showed the outline for demonstrating the structure of the signal line in each liquid crystal display panel of the liquid crystal display device which concerns on 2nd Embodiment. 5 is a timing chart showing the relationship among the states of analog switches, signal lines, and scanning line driving circuits in one frame period in each liquid crystal panel of FIG. It is a top view for demonstrating the structure of the signal wire | line in the conventional liquid crystal display device which couple | bonded two liquid crystal panels.

Explanation of symbols

1 ... Main liquid crystal panel 2 ... Sub liquid crystal panel 3 ... FPC
4 ... main display area 5 ... sub display area 6 ... signal line drive circuit 7a ... main signal line 7b ... sub signal lines 8, 8a, 8b ... common potential supply lines 9a, 9b, 10, 11 ... analog switch 12 ... main sub Common signal line

Claims (4)

A first liquid crystal panel having a plurality of first signal lines;
A second liquid crystal panel having a plurality of second signal lines;
A common potential supply line to which a common potential is supplied;
A first switch for switching whether to electrically connect or disconnect the terminal end of the first signal line and the terminal end of the second signal line;
A second switch for switching between electrically connecting or disconnecting the terminal of the second signal line and the common potential supply line;
When writing a video signal to the first liquid crystal panel, the end of the first signal line and the start of the second signal line are cut by the first switch, and the end of the second signal line is cut by the second switch. A signal line driving circuit for writing a video signal to the first signal line and supplying a common potential to the second signal line via the common potential supply line, Have
The liquid crystal display device , wherein the common potential is within a voltage amplitude range of a video signal .   The first signal line includes two types of signal lines, a connected first signal line connected to the first switch and an unconnected first signal line not connected to the first switch. The liquid crystal display device according to claim 1, wherein the unconnected first signal line has a uniform length.   In the signal line driving circuit, when writing a video signal to the second liquid crystal panel, the terminal end of the connection first signal line and the start end of the second signal line are connected by the first switch, and the second switch After the termination of the second signal line and the common potential supply line are disconnected, the video signal is written to the second signal line through the connection first signal line, and the unconnected first signal line is written. The liquid crystal display device according to claim 2, wherein a common potential is supplied. The signal line driver circuit, a liquid crystal display device according to any one of claims 1 to 3, characterized in that supplying the common potential at least one horizontal scanning period or more.

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