JP4839490B2 - Automatic data skew correction system - Google Patents

Description

  The present invention relates to an automatic data skew correction system for transferring data from a transmission circuit to a reception circuit.

  During data transfer of high-speed serial communication (especially at the time of LVDS (Low Voltage Differential Signaling) output), there is a deviation in the data output timing with respect to the reference clock due to variation in characteristics when the device is manufactured (process manufacturing variation) appear. Therefore, the electrical characteristics of the device are significantly degraded due to the skew of the data output.

  Here, the literature is introduced.

  Japanese Unexamined Patent Application Publication No. 2002-329789 describes a semiconductor device (Patent Document 1). The semiconductor device monitors a pattern processing variation depending on a manufacturing process variation, receives a detection circuit that generates a detection signal when the pattern processing variation exceeds a predetermined allowable range, and receives the detection signal of the detection circuit. And a characteristic correction circuit for correcting the electrical characteristics of the target circuit.

  Japanese Patent Laying-Open No. 2005-303753 describes a signal transmission system (Patent Document 2). The signal transmission system includes a measuring device that measures an ambient environmental value, a first circuit block that transmits a clock signal and a data signal, and a second circuit that receives the clock signal and the data signal transmitted by the first circuit block. And a circuit block. The second circuit block includes an input circuit that inputs a clock signal, a timing adjustment circuit that inputs a clock signal and outputs a strobe signal, and performs skew correction when the measurement value of the measurement device exceeds a predetermined value; And a latch circuit for latching the data signal using the strobe signal.

  Japanese Patent Application Laid-Open No. 2007-159387 describes a vehicle power generation control device (Patent Document 3). The vehicle power generation control device changes the adjustment voltage of the vehicle power generator based on a signal sent from the external control device. This vehicle power generation control device is configured to adjust the voltage of the output terminal of the vehicle generator so that the voltage of the output terminal of the vehicle generator matches the adjustment voltage, and the frequency of the signal superimposed on the voltage of the output terminal of the vehicle generator. Adjustment voltage changing means for changing the adjustment voltage from the first value to the second value when the frequency of the superimposed signal is higher than the predetermined frequency in comparison with the predetermined frequency. It is said.

JP 2002-329789 A (Claim 1) JP 2005-303753 A (Claim 1) JP 2007-159387 A (Claim 1)

  An object of the present invention is to provide an automatic data skew correction system capable of transferring data from a transmission circuit to a reception circuit with accurate timing.

  The data skew automatic correction system of the present invention includes a transmission circuit, a reception circuit, a detection unit, and a skew correction circuit. The transmission circuit includes a device and outputs data according to a clock signal. The receiving circuit receives data. The detection unit is provided in the transmission circuit. The detection unit generates a detection signal when the value indicating the characteristic of the device does not satisfy the reference value. When the detection signal is generated, the skew correction circuit adjusts the data output timing according to the clock signal.

  In the data skew automatic correction system of the present invention, data can be transferred from the transmitting circuit to the receiving circuit with accurate timing.

  Hereinafter, an automatic data skew correction system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[Constitution]
FIG. 1 shows a configuration of an automatic data skew correction system according to an embodiment of the present invention. This automatic data skew correction system includes a DC power supply circuit 1, a transmission circuit 10, a PVT detection unit 20, a skew correction circuit 31, a reception circuit 32, and a display device (display) 33.

  The DC power supply circuit 1 is provided in the transmission circuit 10 and supplies power to the transmission circuit 10.

  An example of the transmission circuit 10 is SoC (system on chip).

  The transmission circuit 10 includes a high-speed communication system controller (hereinafter referred to as a controller) 12. The controller 12 includes a device (not shown) and a register 13. The device includes, for example, a transistor and a capacitor. Information (value) stored in the register will be described later.

  The transmission circuit 10 further includes a core peripheral circuit (hereinafter referred to as a peripheral circuit) 11. The peripheral circuit 11 is provided around the controller 12 and includes at least one CPU and memory. For example, it is assumed that the peripheral circuit 11 is a CPU (Central Processing Unit). Under the control of the CPU, the controller 12 outputs a clock signal SIG11 that is a reference clock, and outputs data SIG21 according to the clock signal SIG11.

  The PVT detection unit 20 is provided in the transmission circuit 10.

  For example, the output timing of the data SIG21 relative to the clock signal SIG11 due to characteristic variation (manufacturing variation) when the device is manufactured during data transfer of high-speed serial communication (especially, during output of LVDS (Low Voltage Differential Signaling)). Deviation occurs. As a result, the electrical characteristics of the device are significantly deteriorated due to the skew of the data SIG21. Therefore, in the data skew automatic correction system according to the embodiment of the present invention, in order to transfer data from the transmission circuit 10 to the reception circuit 32 at an accurate timing, the PVT detection unit 20 varies the characteristics of the devices in the transmission circuit 10. And a detection signal SIG31 is generated as a detection result. In order to realize this, the PVT detection unit 20 includes a register value comparator 22 described later.

  Further, there may be a case where a deviation occurs in the output timing of the data SIG21 with respect to the clock signal SIG11 due to environmental fluctuations during system operation. Environmental fluctuation is fluctuation caused by PVT (power operating load / voltage / temperature). As a result, the electrical characteristics of the device are significantly deteriorated due to the skew of the data SIG21. Therefore, in the data skew automatic correction system according to the embodiment of the present invention, in order to transfer data from the transmission circuit 10 to the reception circuit 32 with accurate timing, the PVT detection unit 20 detects PVT fluctuations during system operation, As a result of the detection, a detection signal SIG31 is generated. In order to realize this, the PVT detection unit 20 further includes a DC voltage IR drop detection circuit 21, a device temperature rise detection circuit 23, and an operating frequency detection circuit 24 described later.

  The skew correction circuit 31 outputs the clock signal SIG11 and the data SIG21 from the transmission circuit 10 to the reception circuit 32 as the clock signal SIG41 and the data SIG42, respectively.

  Further, when the detection signal SIG31 is generated, the skew correction circuit 31 adjusts the output timing of the data SIG21 according to the clock signal SIG11, and receives the clock signal SIG11 and the data SIG21 as the clock signal SIG41 and the data SIG42, respectively. Output to. That is, the skew of the data SIG21 is automatically corrected, and the automatically corrected data SIG21 is output to the receiving circuit 32 as data SIG42.

  The receiving circuit 32 is connected to the display device 33. The receiving circuit 32 receives a clock signal SIG41 and data SIG42. At this time, the reception circuit 32 receives the data SIG42 at an accurate timing according to the clock signal SIG41. The reception circuit 32 executes a predetermined process on the data SIG 42 and displays the execution result on the display device 33.

[Operation]
FIG. 2 is a flowchart showing operations of the transmission circuits 1, 10, 20 and the skew correction circuit 31 of the automatic data skew correction system according to the embodiment of the present invention.

  Although not shown, a person in charge such as a manufacturer or a designer stores a value indicating the characteristics of the device in the controller 12 (hereinafter, characteristic value) in the register 13 in advance. The characteristic value represents the threshold voltage of the transistor.

  The DC power supply circuit 1 starts supplying power to the transmission circuit 10 in accordance with a user instruction. At this time, power is turned on to the transmission circuit 10 (step S1).

  The register value comparator 22 reads the characteristic value from the register 13 (step S2).

  The register value comparator 22 compares the characteristic value stored in the register 13 with the reference value (step S3). Here, the characteristic value represents the threshold voltage of the transistor. Further, a device that becomes a reference value is set as a reference operation product (a device that becomes a reference threshold voltage is set as a CENTER product). In step S3, the register value comparator 22 determines whether the device whose characteristic value is a low-speed operation product (a device whose threshold voltage is higher than the reference threshold voltage is a SLOW product) or a high-speed operation product (threshold voltage is It is determined whether or not the product is a FAST product.

  As a result, when the characteristic value does not satisfy the reference value, that is, when the device is determined to be a SLOW product (step S3-Yes), the register value comparator 22 generates the detection signal SIG31 (step S10).

  The controller 12 of the transmission circuit 10 outputs a clock signal SIG11 and outputs data SIG21 according to the clock signal SIG11. Therefore, since the detection signal SIG31 is generated, the skew correction circuit 31 adjusts the output timing of the data SIG21 according to the clock signal SIG11. That is, the skew of the data SIG21 is automatically corrected (step S11). The skew correction circuit 31 outputs the clock signal SIG11 and the data SIG21 to the reception circuit 32 as the clock signal SIG41 and the data SIG42, respectively. That is, the automatically corrected data SIG21 is output as data SIG42 to the receiving circuit 32 (step S12). Thereby, the receiving circuit 32 receives the data SIG42 at an accurate timing according to the clock signal SIG41.

  If the power supply to the transmission circuit 10 has not been turned on (No at Step S13), Step S3 and subsequent steps are executed.

  On the other hand, when the characteristic value satisfies the reference value, that is, when the device is not determined to be a SLOW product (step S3-No), the DC voltage IR drop detection circuit 21 drops the voltage with respect to the power supplied to the transmission circuit 10 Is monitored (step S4).

  The DC voltage IR drop detection circuit 21 compares the voltage value Xmv representing the voltage drop and the set value αmv (step S5). As a result, when the voltage value Xmv exceeds the set value αmv (step S5-Yes), the DC voltage IR drop detection circuit 21 generates the detection signal SIG31 (step S10).

  In this case, steps S11 and S12 are executed as described above. If the power supply to the transmission circuit 10 has not been turned on (No at Step S13), Step S3 and subsequent steps are executed.

  On the other hand, when the voltage value Xmv does not exceed the set value αmv (step S5-No), the device temperature rise detection circuit 23 monitors the temperature Y ° C. of the device in the controller 12 (step S6).

  The device temperature rise detection circuit 23 compares the temperature Y ° C. with the set temperature β ° C. (step S7). When the temperature Y ° C. exceeds the set temperature β ° C. (step S7—Yes), the detection signal SIG31 is generated (step S10).

  In this case, steps S11 and S12 are executed as described above. If the power supply to the transmission circuit 10 has not been turned on (No at Step S13), Step S3 and subsequent steps are executed.

  On the other hand, when the temperature Y ° C does not exceed the set temperature β ° C (step S7-No), the operating frequency detection circuit 24 monitors the operating frequency Zmhz of the peripheral circuit 11 (step S8).

  The operating frequency detection circuit 24 compares the operating frequency Zmhz with the set operating frequency γmhz (step S9). When the operating frequency Zmhz exceeds the set operating frequency γmhz (step S9—Yes), the detection signal SIG31 is generated (step S10).

  In this case, steps S11 and S12 are executed as described above. If the power supply to the transmission circuit 10 has not been turned on (No at Step S13), Step S3 and subsequent steps are executed.

  On the other hand, the operating frequency Zmhz does not exceed the set operating frequency γmhz (step S9-No). At this time, when the power supply to the transmission circuit 10 is not finished (step S13-No), step S3 and subsequent steps are executed. Alternatively, the DC power supply circuit 1 ends the supply of power to the transmission circuit 10 in accordance with a user instruction. In this case, power-on to the transmission circuit 10 is completed (step S13—YES).

[effect]
According to the data skew automatic correction system according to the embodiment of the present invention, as a first effect, even if the characteristics of devices in the transmission circuit 10 vary, data is transmitted from the transmission circuit 10 to the reception circuit 32 with accurate timing. Can be transferred.

  According to the data skew automatic correction system according to the embodiment of the present invention, as a second effect, even if there is a PVT (power operation load / voltage / temperature) fluctuation during system operation, the data skew is received from the transmission circuit 10 at an accurate timing. Data can be transferred to the circuit 32.

  According to the data skew automatic correction system according to the modification of the first embodiment of the present invention, when 7-bit data is serially transferred with respect to one clock like LVDS output, the data output timing is determined by the skew for each bit. Even when a deviation occurs, data can be transferred from the transmission circuit 10 to the reception circuit 32 with accurate timing.

(First embodiment)
FIG. 3 shows the configuration of the data skew automatic correction system according to the first embodiment of the present invention. The automatic data skew correction system according to the first embodiment includes a transmission circuit 60, a skew correction circuit 70, and a reception circuit 61. In the first embodiment, only differences from the above-described embodiment will be described.

  The transmission circuit 60 includes the aforementioned DC power supply circuit 1, transmission circuit 10, and PVT detection unit 20. Alternatively, the transmission circuit 60 corresponds to the transmission circuit 10 described above, and although not illustrated, the transmission circuit 60 is provided with the DC power supply circuit 1 and the PVT detection unit 20 described above.

  The receiving circuit 61 includes the receiving circuit 32 and the display device 33 described above. Alternatively, the reception circuit 61 corresponds to the reception circuit 32 described above, and although not illustrated, the reception circuit 61 is provided with the display device 33 described above.

  The skew correction circuit 70 corresponds to the skew correction circuit 31. The skew correction circuit 70 is provided in the transmission circuit 60. Thus, when the detection signal SIG31 is generated, the skew correction circuit 70 automatically corrects the skew of the data SIG21 in accordance with the clock signal SIG11 from the transmission circuit 60. The skew correction circuit 70 outputs the clock signal SIG11 and the data SIG21 at that time as the clock signal SIG41 and the data SIG42 to the receiving circuit 61 via the transmission line, respectively.

  FIG. 4 shows the configuration of the skew correction circuit 70. The skew correction circuit 70 includes, for example, a 7-times multiplication circuit 80, a phase adjustment circuit 81, a multiplexer (MUX) 82, and an AND circuit 83. The skew correction circuit 70 is supplied with the clock signal SIG11, data SIG21, and detection signal SIG31 output from the transmission circuit 60.

  The clock signal SIG11 is supplied to the input of the 7-times multiplication circuit 80. Further, the clock signal SIG11 is output as the clock signal SIG41 to the receiving circuit 61 via the transmission path. The data SIG21 is supplied to the input of the AND circuit 83. Data SIG21 is supplied to the input of MUX. The detection signal SIG31 is supplied to the input of the AND circuit 83. The detection signal SIG31 is supplied to the MUX 82 as a trigger signal. The phase adjustment circuit 81 is connected to the output of the 7-times multiplication circuit 80 and the output of the AND circuit 83. The output of the phase adjustment circuit 81 is connected to the input of the MUX 82. The output of the MUX 82 is output as data SIG42 to the receiving circuit 61 via the transmission path.

  FIG. 5 is a timing chart showing the operation of the skew correction circuit 70. When outputting LVDS (Low Voltage Differential Signaling), 7-bit data is serially output from the transmission circuit 60 in one clock.

  In this case, the 7-times multiplication circuit 80 multiplies 1 clock by 7 with respect to the clock signal SIG11 and outputs the result to the phase adjustment circuit 81. The AND circuit 83 receives the detection signal SIG31 and the data SIG21. Here, it is assumed that the signal level of the data SIG21 represents a high (H) level. Further, when the detection signal SIG31 is generated, the signal level of the detection signal SIG31 represents the H level. Since the signal level of the detection signal SIG31 and the signal level of the data SIG21 are H level, the AND circuit 83 outputs an AND output signal indicating that the signal level is H level to the phase adjustment circuit 81.

  6 and 7 are timing charts showing the operation of the phase adjustment circuit 81. FIG.

  As shown in FIG. 6, the data SIG21 is output from the transmission circuit 60 at a timing faster than the clock signal SIG11. In this case, the phase adjustment circuit 81 executes a phase adjustment process for delaying the phase of the data SIG21 so that the switching timing of the data SIG21 coincides with the rising edge of the clock signal SIG11. By executing this processing, the skew of the data SIG21 is automatically corrected.

  As shown in FIG. 7, the data SIG21 is output from the transmission circuit 60 at a timing later than the clock signal SIG11. In this case, the phase adjustment circuit 81 executes a phase adjustment process for advancing the phase of the data SIG21 so that the switching timing of the data SIG21 coincides with the rising edge of the clock signal SIG11. By executing this processing, the skew of the data SIG21 is automatically corrected.

  The phase adjustment circuit 81 outputs the data SIG21 on which the phase adjustment process has been performed to the MUX 82. The MUX 82 inputs the data SIG 21 from the transmission circuit 60 and the data SIG 21 from the phase adjustment circuit 81.

  When the detection signal SIG31 is not generated (the signal level of the detection signal SIG31 is the low (L) level), the MUX 82 uses the data SIG21 from the transmission circuit 60 as the data SIG42 via the transmission line and the reception circuit 61. Output to. In this case, there is no variation in the characteristics of the devices in the transmission circuit 60 and no PVT (power operation load / voltage / temperature) fluctuation during system operation. Therefore, the data SIG42 is transferred from the transmission circuit 60 to the reception circuit 61 with accurate timing.

  When the detection signal SIG31 is generated (the signal level of the detection signal SIG31 is H level), the MUX 82 outputs the data SIG21 from the phase adjustment circuit 81 as data SIG42 to the reception circuit 61 via the transmission line. In this case, the skew of the data SIG 21 is automatically corrected even if there are variations in the characteristics of the devices in the transmission circuit 60 or there are PVT (power operation load / voltage / temperature) fluctuations during system operation. The data SIG 42 is transferred from the transmission circuit 60 to the reception circuit 61 with accurate timing.

  FIG. 8 shows a modification of the data skew automatic correction system according to the first embodiment of the present invention.

  As described above, in the first embodiment, when 7-bit data is serially output from the transmission circuit 60 in one clock, the phase adjustment circuit 81 causes the rising edge of the clock signal SIG11 at the timing when the detection signal SIG31 is generated. Therefore, the phase adjustment process is executed so that the switching timing of the data SIG21 coincides. That is, the skew of the data SIG21 having only 1 bit is automatically corrected with respect to the rising edge of the clock signal SIG11.

  On the other hand, in the modification of the first embodiment, the minimum value (MIN value) and the maximum value (MAX value) are selected from the skews of the data SIG21 from the first bit to the seventh bit in response to the rising edge of the clock signal SIG11. And the skew of the data SIG21 from the first bit to the seventh bit is automatically corrected. Specifically, the phase adjustment circuit 81 obtains an average value representing the average of the maximum value and the minimum value among the values representing the output timing of the 7-bit data SIG21 in response to the rising edge of the clock signal SIG11. The phase adjustment circuit 81 adjusts the output timing of the 7-bit data SIG21 based on the average value.

  In this modification, as shown in FIG. 8, when periodic high frequency noise occurs, this is an effective method when a deviation occurs in data output timing due to skew for each bit.

  As described above, according to the automatic data skew correction system according to the first embodiment of the present invention, there are variations in the characteristics of the devices in the transmission circuit 60, and there are variations in PVT (power operation load / voltage / temperature) during system operation. Even if there is, data can be transferred from the transmission circuit 60 to the reception circuit 61 with accurate timing. That is, the data skew automatic correction system according to the first embodiment of the present invention realizes the first and second effects described above.

  According to the data skew automatic correction system according to the modification of the first embodiment of the present invention, when 7-bit data is serially transferred with respect to one clock like LVDS output, the data output timing is determined by the skew for each bit. Even when a deviation occurs, data can be transferred from the transmission circuit 10 to the reception circuit 32 with accurate timing.

(Second Embodiment)
FIG. 9 shows the configuration of an automatic data skew correction system according to the second embodiment of the present invention. The data skew automatic correction system according to the second embodiment includes a transmission circuit 60, a skew correction circuit 90, and a reception circuit 61. That is, a skew correction circuit 90 is provided instead of the skew correction circuit 70. In the second embodiment, only differences from the first embodiment will be described.

  The skew correction circuit 90 corresponds to the skew correction circuit 31. The skew correction circuit 90 is provided in the reception circuit 61. The clock signal SIG11 and data SIG21 from the transmission circuit 60 are supplied to the skew correction circuit 90 after passing through the transmission path. Thereby, when the detection signal SIG31 is generated, the skew correction circuit 90 automatically corrects the skew of the data SIG21 in accordance with the clock signal SIG11. The skew correction circuit 90 outputs the clock signal SIG11 and data SIG21 at that time to the reception circuit 61 as the clock signal SIG41 and data SIG42, respectively.

  As described above, the clock signal SIG11 and the data SIG21 from the transmission circuit 60 are supplied to the skew correction circuit 90 after passing through the transmission path. For this reason, what is necessary is just to implement | achieve 1st Embodiment or 2nd Embodiment in consideration of the influence (PCB track | line, a cable, etc.) of a transmission line.

  Fields of application of the present invention include general digital equipment that performs high-speed serial data transfer and LSI (Large-Scale Integrated Circuit) in general.

FIG. 1 shows a configuration of an automatic data skew correction system according to an embodiment of the present invention. FIG. 2 is a flowchart showing operations of the transmission circuits 1, 10, 20 and the skew correction circuit 31 of the automatic data skew correction system according to the embodiment of the present invention. FIG. 3 shows the configuration of the data skew automatic correction system according to the first embodiment of the present invention. FIG. 4 shows the configuration of the skew correction circuit 70 of the data skew automatic correction system according to the first embodiment of the present invention. FIG. 5 is a timing chart showing the operation of the skew correction circuit 70 of the data skew automatic correction system according to the first embodiment of the present invention. FIG. 6 is a timing chart showing the operation of the phase adjustment circuit 81 of the skew correction circuit 70 of the data skew automatic correction system according to the first embodiment of the present invention. FIG. 7 is a timing chart showing the operation of the phase adjustment circuit 81 of the skew correction circuit 70 of the data skew automatic correction system according to the first embodiment of the present invention. FIG. 8 shows a modification of the data skew automatic correction system according to the first embodiment of the present invention. FIG. 9 shows the configuration of an automatic data skew correction system according to the second embodiment of the present invention.

Explanation of symbols

1 DC power circuit,
10 SoC,
11 CPU,
12 controller,
13 registers,
20 PVT detector,
21 DC voltage IR drop detection circuit,
22 register value comparator,
23 device temperature rise detection circuit,
24 operating frequency detection circuit,
31 skew correction circuit,
32 receiver 33 display,
60 transmitter circuit,
61 receiver circuit,
70 skew correction circuit,
80 x7 circuit,
81 phase adjustment circuit,
82 MUX,
83 AND circuit,
90 skew correction circuit,
SIG11 clock signal,
SIG21 data,
SIG31 detection signal,
SIG41 clock signal,
SIG42 data,

Claims (18)

A transmission circuit including a device and outputting data according to a clock signal;
A receiving circuit for receiving the data;
A detection unit that is provided in the transmission circuit and generates a detection signal when a value indicating the characteristics of the device does not satisfy a reference value;
When the detection signal occurs, a skew correction circuit that adjusts the output timing of the data according to the clock signal;
A data skew automatic correction system comprising: The transmission circuit includes:
A register storing values indicating characteristics of the device;
Further comprising
The detector is
A register value comparator that compares the value stored in the register with the reference value and generates the detection signal if the value does not satisfy the reference value;
The data skew automatic correction system according to claim 1, further comprising: The device includes a transistor;
The value represents a threshold voltage of the transistor;
The data skew automatic correction system according to claim 1 or 2. The detector is
A voltage drop that monitors a voltage drop with respect to a power source supplied to the transmission circuit, compares a voltage value representing the voltage drop with a set value, and generates the detection signal when the voltage value exceeds the set value. Detection circuit,
The data skew automatic correction system according to claim 1, further comprising: The detector is
A device temperature rise detection circuit that monitors the temperature of the device, compares the temperature with a set temperature, and generates the detection signal when the temperature exceeds the set temperature;
The data skew automatic correction system according to claim 1, further comprising: The transmission circuit includes:
A peripheral circuit that is provided around the device and includes at least one CPU and memory;
Further comprising
The detector is
An operating frequency detection circuit that monitors an operating frequency of the peripheral circuit, compares the operating frequency with a set operating frequency, and generates the detection signal when the operating frequency exceeds the set operating frequency;
The data skew automatic correction system according to claim 1, further comprising: When the data of a plurality of bits is serially output from the transmission circuit,
When the detection signal is generated, the skew correction circuit obtains an average value of the output timing of the plurality of bits of data according to the clock signal, and outputs the timing of the plurality of bits of data based on the average value. Adjust the
The data skew automatic correction system according to any one of claims 1 to 6. The average value represents an average of the maximum value and the minimum value among the values representing the output timing of the data of the plurality of bits.
The data skew automatic correction system according to claim 7. The skew correction circuit is provided in the transmission circuit or the reception circuit,
The data skew automatic correction system according to any one of claims 1 to 8. The transmission circuit applied to the data skew automatic correction system according to any one of claims 1 to 9,
The skew correction circuit applied to the data skew automatic correction system according to any one of claims 1 to 9,
A transmitter comprising: The skew correction circuit applied to the data skew automatic correction system according to any one of claims 1 to 9,
The receiving circuit applied to the data skew automatic correction system according to any one of claims 1 to 9,
A receiver comprising: A transmission circuit outputting data according to a clock signal;
A receiving circuit receiving the data, wherein the transmitting circuit comprises a device;
Generating a detection signal when a value indicating the characteristic of the device does not satisfy a reference value;
When the detection signal is generated, adjusting the output timing of the data according to the clock signal;
A data skew automatic correction method comprising: Pre-stores the value indicating the characteristics of the device in a register;
Further comprising
If the value does not meet the reference value, generating the detection signal comprises:
Comparing the value stored in the register with the reference value;
The data skew automatic correction method according to claim 12, comprising: Monitoring a voltage drop with respect to a power source input to the transmission circuit;
Comparing a voltage value representing the voltage drop with a set value;
Generating the detection signal when the voltage value exceeds the set value;
The data skew automatic correction method according to claim 12 or 13, further comprising: Monitoring the temperature of the device;
Comparing the temperature with a set temperature;
Generating the detection signal when the temperature exceeds the set temperature;
The data skew automatic correction method according to claim 12, further comprising: Monitoring the operating frequency of a peripheral circuit; and the transmission circuit further comprising a peripheral circuit provided at a periphery of the device and including at least one CPU and memory;
Comparing the operating frequency with a set operating frequency;
Generating the detection signal when the operating frequency exceeds the set operating frequency;
The data skew automatic correction method according to claim 12, further comprising: When the data of a plurality of bits is serially output from the transmission circuit,
The step of adjusting the output timing of the data includes:
When the detection signal is generated, in accordance with the clock signal, obtaining an average value of the output timing of the plurality of bits of data;
Adjusting the output timing of the plurality of bits of data based on the average value;
The data skew automatic correction method according to claim 12, comprising: The average value represents an average of the maximum value and the minimum value among the values representing the output timing of the data of the plurality of bits.
The data skew automatic correction method according to claim 17.

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