JP4841314B2 - Data transfer circuit - Google Patents

Description

  The present invention relates to a data transfer circuit that outputs data received from a writing device to a reading device.

  The data transfer circuit shown in FIG. 4 is proposed as a data transfer circuit configured to latch data received from a writing side device in a temporary storage area in units of data bus width and then read the data to a reading side device of a different clock. (For example, refer to Patent Document 1).

This is because the data received from the network bus 401 side is transferred to the main storage device (not shown) via the internal bus 402 that operates at a clock different from the clock of the network bus 401. The sequencer 403 operating in synchronization with the clock controls the MAC (Media Access Control) unit 404, the memory 405 using the FIFO, and the register file unit 406 to receive 128 bits received from the network bus 401 in units of 8 bits. Is stored in the register file unit 406, and the latch unit 408 and the DMAC (DMA controller) unit 409 are controlled by the sequencer 407 that operates in synchronization with the clock on the internal bus side, so that the data in the latch unit 408 is stored. Internal main note in 8-bit units It is for storing device. The sequencers 403 and 407 perform handshaking.
JP-A-12-172636

  This data transfer circuit functions effectively when a large amount of data is taken into the reading side device in the order received from the writing side device, but does not support random access to the register file unit 406. When there is a data group that needs to be read preferentially, there is a problem that the data group cannot be read without losing consistency.

  For example, when a certain data group is stored in the register file unit 406 as one unit and is to be read out to the internal bus 402 side, part of the data in the register file unit 406 is rewritten during the reading. In such a case, the consistency of the data group read to the internal bus 402 side may be lost.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer circuit that can be randomly accessed and can read a data group without destroying its consistency.

In order to achieve the above object, the invention according to claim 1 is a data transfer circuit for outputting data received from a writing side device to a reading side device, and a plurality of main registers for holding data received from the writing side device has a group, and said plurality of first first temporary register group of one to temporarily hold the data held in the main register group of arbitrarily selected from among the main register group, the write-side When a write request to any of the main register groups is received from a device, the entire data held in the main register group that is the target of the write request is stored in the first temporary register group, and then the write is performed. Writing to the main register group to be requested is started.
According to a second aspect of the present invention, in the first aspect of the present invention, the main device of the target of the write request is received from the read-side device while the write request is being performed on the main register group. When a read request for a register group is received, the data stored in the first temporary register group is read and output.
According to a third aspect of the present invention, in the first aspect of the present invention, any one of the plurality of main register groups is received from the writing side device while reading from the first temporary register group is being performed. When the second write request for the second write request is received, the data of the main register group that is the target of the second write request is not stored in the first temporary register, and the target of the second write request is not stored. Writing to the main register group is characterized.
According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, data held in a second main register group arbitrarily selected from the plurality of main register groups is temporarily held. A second temporary register that receives a read request from any one of the read-side devices while the write request to the main register group is not performed. In this case, the entire data held in the main register group to be read is stored in the second temporary register group, and then read from the second temporary register group and output.
According to a fifth aspect of the present invention, there is provided a data transfer circuit that outputs data received from a writing side device to a reading side device, a plurality of main register groups that hold data received from the writing side device, and the plurality of main registers Each having a first temporary register group and a second temporary register group for temporarily holding data held in first and second register groups arbitrarily selected from the group, from the writing side device, When a write request is received for one of the main register groups and the write request is received while reading from the first temporary register is not performed, the main request target The entire data held in the register group is stored in the first temporary register group, and then writing to the main register group subject to the write request is started. If the data is received while the first temporary register is being read, the data of the main register group to which the write request is made is not stored in the first temporary register. When writing to the main register group that is the target of the write request and receiving a read request for any of the plurality of main register groups from the reading side device, the read request is the main request target main register group. Read data stored in the first temporary register group when it is targeted for the register group and received while the write request is being made to the main register group. In other cases, the entire data held in the main register group subject to the read request is stored in the second temporary register group, and then the second temporary record is stored. And outputs read out from Staphylococcus group.
According to a sixth aspect of the present invention, in the invention according to any one of the first to third aspects, a memory is stored in a corresponding main register group between each of the plurality of main register groups and the first temporary register. A wiring having a bit width capable of simultaneously transferring data of the possible number of bits is provided.
The invention according to claim 7 is the invention according to claim 4 or 5, wherein there is a correspondence between each of the plurality of main register groups and each of the first and second temporary register groups. The main register group is provided with a wiring having a bit width capable of simultaneously transferring data of the number of bits that can be stored.

According to the present invention, since a plurality of main register groups are provided, random access for writing and reading is possible. In addition, when data is written to the first main register group, the data of the first main register group is saved in the first temporary register group and then the data is written to the first main register group. When a data read request for the first main register group is received, the immediately preceding data can be read from the first temporary register group without losing consistency. Further, when data is read from the second main register group, the data of the second main register group is saved in the second temporary register group, and then the data is read from the second temporary register group. When a write request for data in the second main register group is received, the immediately preceding data can be read from the second temporary register group without losing consistency.

  FIG. 1 is a block diagram showing a configuration of a data transfer circuit according to one embodiment of the present invention. Reference numeral 100 denotes a writing side device, and 101 denotes an output bus connected to the device 100. Reference numeral 200 denotes a reading side device, and 201 denotes an input bus connected to the device 200.

  Reference numeral 300 denotes a transfer circuit, and 32 bits are fetched from the output bus 101 by a MAC (Media Access Control) unit 301. 302 to 305 are selectors, 306 and 307 are sequencers, 310 to 31m are main register groups, and 320 and 321 are temporary register groups.

  Each of the main register groups 310 to 31m has a plurality of parallel 32-bit input / output registers. For example, the main register group 310 has n0 + 1 registers, the main register group 311 has n1 + 1 registers,..., And the main register group 31m has nm + 1 registers. Data writing to the registers of the main register groups 310 to 31m is performed in units of 32 bits in parallel in synchronization with the clock of the writing side device 100. For reading, the main register group 310 is in parallel 32 × (n0 + 1) bit units, the main register group 311 is in parallel 32 × (n1 + 1) bit units,..., And the main register group 31m is in parallel 32 × (nm + 1) bit units Each is performed in one clock.

  The temporary register groups 320 and 321 have the same number of registers as the number of registers (nmax + 1) of the register group having the most registers among the main register groups 310 to 31m. Data read from the main register groups 310 to 31 m can be written to the temporary register groups 320 and 321 via the selectors 303 or 304. The data transfer from the main register group 310, 311,..., 31m to the temporary register group 320 or 321 is 32 × (n0 + 1), 32 × (n1 + 1),. It can be done in 1 clock in bit units. Between the main register groups 310 to 31m and the temporary register groups 320 and 321, a wiring having a data width that enables such data transfer in one clock is provided. That is, 32 × (n0 + 1), 32 × (n1 + 1),..., 32 × (nm + 1) bits between the main register groups 310, 311,..., 31m and the selectors 303 and 304, respectively. A width of wiring is provided. In addition, a wiring of 32 × (nmax + 1) bit width is provided between the selectors 303 and 304 and the temporary register groups 320 and 321.

  As will be described later, data transfer from the main register group 310 to 31m to the temporary register groups 320 and 321 is performed according to a request from the writing side device 100 and a case where it is performed according to a request from the reading side device 200. There is. In the case of a request from the writing device 100, data transfer is performed with one clock in synchronization with the clock of the writing device 100. In the case of a request from the reading side device 200, data transfer is performed with one clock in synchronization with the clock of the reading side device 200.

  On the other hand, data reading from the temporary register groups 320 and 321 is performed in units of 32 bits in synchronization with the clock of the reading-side device 200 and is output to the input bus 201 via the selector 305.

  The sequencer 306 operates with the clock of the writing device 100 to control the MAC unit 301, the selector 302, and the main register groups 310 to 31m. The sequencer 307 operates with the clock of the reading-side device 200 and controls the selectors 303 to 305 and the temporary register groups 320 and 321. In addition, the sequencers 306 and 307 communicate with each other to adjust between the operations of the main register groups 310 to 31m and the operations of the selectors 303 and 304 and the temporary register groups 320 and 321. The sequencer 306 notifies the sequencer 307 of writing to the main register group.

  Data groups stored in the main register groups 310 to 31m include (1) AVI InfoFrame data group including video data information such as image size, and (2) audio data information such as audio data sampling frequency. There are audio InfoFrame data group including, (3) SPD (Source Product Description) InfoFrame data group including product information, and others. “InfoFrame” is defined in the standard.

  The number of bits of these data groups is different. The AVI InfoFrame data group is 13 bytes, the Audio InfoFrame data group is 5 bytes, and the SPD InfoFrame data group is 25 bytes. If the main register groups 310 to 31m are configured with 32-bit (4-byte) registers as in this embodiment, four, two, and seven registers are required, respectively. Since these data groups have different data capacities, the main register groups 310 to 31m are provided as dedicated register groups for respective uses.

  When there is a change in the InfoFrame information as described above, the writing device 100 transfers the changed InfoFrame data to the reading device 200. For this purpose, the data of the corresponding main register group in the main register groups 310 to 31m is updated, and the reading side device 200 is notified of the update. On the other hand, when there is a notification from the writing device 100, the reading device 200 issues a read request. In addition to this, a read request is made (for example, when it is necessary at the time of startup or the like). In the above embodiment, since the dedicated main register group 310 to 31m for holding each InfoFrame data is provided, the write and read requests generated from the write side device 100 and the read side device 200 are the main requests. The target main register group in the register groups 310 to 31m is specified. This writing and reading are performed asynchronously (at different clock frequencies). Even in such a case, the two temporary register groups 320, 320, so as not to cause data inconsistency (reading from the main register group being updated results in reading of data in which information before and after the update is mixed). 321 is provided and the following processing is performed.

  FIG. 2 is a flowchart of an operation resulting from a request from the writing side 100. When a write request to any one of the main register groups 310 to 31m is received from the writing side device 100 (S12-YES), data is read from the temporary register group 320 by a request made before that. Is determined to be continued (S13). Here, the write request is a request designating a specific main register group corresponding to the type of data to be written. However, since there is only one temporary register group 320, it is determined whether or not the same temporary register group 320 is currently being read regardless of which main register group has a write request.

  If not being read (S13-NO), the data of the main register group to be written is stored in the temporary register group 320 from (S14) (in this embodiment, this operation is completed in one clock), Writing of new data to the main register group requested to write is started (S15).

  In this embodiment, when the data of the main register group is stored in the temporary register group 320 in this way and then writing to the main register group is started, a read request for the main register group occurs during the writing. As described later, by reading from the temporary register group 320, it is possible to prevent the occurrence of data mismatch. While writing to the main register group, it may be considered that the reading side device 200 performs control to wait for data reading. However, in this embodiment, if there is a read or write request without performing such control of the read side or write side device, it is possible to respond to the request at that time, and data inconsistency Prevent the occurrence of

  After the time dependent on the data transfer rate from the writing device 100 has elapsed, when the writing is completed, the reading device 200 is notified that writing has been performed (corresponding InfoFrame data has been updated) ( (S16) (As will be described later, in response to this notification, the reading-side device 200 issues a read request), and returns to the Idle state (S11).

  When there is a write request to a specific main register group (S12-YES), if data is being read from the temporary register group 320 (S13-YES), the data is not stored in the temporary register group 320. New data is written to the main register group to be written (S17). As described above, since data is not stored in the temporary register group 320 during reading, inconsistent data is prevented from being read from the temporary register group 320.

  In this case, since data is not stored in the temporary register group 320, if a read request for the same main register group occurs before the writing to the main register group to be written is completed, Data stored in the temporary register group 320 (different from the target one) is read out. However, in reality, the possibility of such occurrences is considered extremely low. Even if such a case occurs, the reading-side device 200 can determine that the requested data is different from the requested data and make a request again.

  Then, after the writing to the main register group is completed, the reading side device 200 is notified that writing has been performed (corresponding InfoFrame data has been updated) (S18). When the side device 200 issues a read request), it returns to the idle state (S11). Note that the system returns to the Idle state when the system is reset.

  FIG. 3 is a flowchart of an operation caused by a request from the reading side device 200. It is designated when receiving a read request (designating which register group is to be read) from any one of the main register groups 310 to 31m from the reading side device 200 (YES in S22). Then, it is determined whether or not writing to the main register group has been performed (writing started by a request made before that is not yet finished) (S23).

  If writing is not in progress (S23-NO), the current data of the main register group to be read is stored in the temporary register group 321 (S26), and then reading is performed from the temporary register group 321 (S27). As a result, even when a write request to the same main register group occurs before the reading is completed, it is possible to prevent the occurrence of data mismatch.

  For example, when the main register group is updated in response to a request from the writing side device 100, the reading side device 200 is notified when the update (writing) is completed, and when the notification is received, the reading side device is received. 200 issues a read request to the updated main register group. When this read request is issued, writing to the target main register group is completed, so that storage to the temporary register group 321 and reading from the temporary register group 321 are performed.

  On the other hand, for example, when the update of the main register group is not received but due to the necessity of the reading-side device 200, a read request may be issued during writing to the target main register group (S23-YES). . In this case, the data is read from the temporary register group 320 that stores the data of the target main register group before the start of writing (S24). Thus, it is possible to prevent the occurrence of data inconsistency that occurs when reading from the main register group in the middle of writing.

  Here, since the data is being read from the temporary register group 320 when the write request is generated, the data before the update cannot be stored, the main register group is written, and before the writing is completed. If a read request is generated for the same main register group, data stored in the temporary register group 320 at that time (different from the target one) is read. However, in reality, the possibility of such occurrences is considered extremely low. Even if such a case occurs, the reading-side device 200 can determine that the requested data is different from the requested data and make a request again. In any case, when reading is completed, the state returns to the idle state (S21).

  In the flowchart of FIG. 3, the state returns to the idle state (S21) at the end of reading. In this case, no response can be made if the next read request (for the same or different main register group) occurs before the reading from any temporary register (by a read request for a certain main register group) is completed.

  To cope with this, it may be possible to return to the idle state (S21) at the time when data reading from the temporary register group 320 (S24) or data reading from the temporary register group 321 (S27) is started. As a result, when a read request with higher importance occurs before the reading is completed, it is possible to stop the reading that has not been completed yet and perform the reading based on the request generated later. it can.

It is a block diagram which shows the structure of the data transfer circuit of the Example of this invention. 2 is a flowchart of an operation as viewed from a writing side device of the data transfer circuit of FIG. 1. 2 is a flowchart of an operation as viewed from a reading side device of the data transfer circuit of FIG. 1. It is a block diagram which shows the structure of the conventional data transfer circuit.

Explanation of symbols

100: Write side device, 101: Output bus 200: Read side device, 201: Input bus 300: Transfer circuit, 301: MAC unit, 302 to 305: Selector, 306, 307: Sequencer, 310 to 31m: Main register group, 320, 321: Temporary registers

Claims (7)

In the data transfer circuit that outputs the data received from the writing device to the reading device,
A plurality of main register groups for holding data received from the writing side device;
Wherein a plurality of the first and one of the first temporary register group for temporarily holding the data held in the main register group arbitrarily selected from among the main registers,
When a write request for any of the main register groups is received from the writing side device, the entire data held in the main register group that is the target of the write request is stored in the first temporary register group. A data transfer circuit which starts writing to a main register group which is a target of the write request.   The first temporary register when a read request for the write request target main register group is received from the read side device while the write request target main register group is being written. 2. The data transfer circuit according to claim 1, wherein the data stored in the group is read and output.   If a second write request for any of the plurality of main register groups is received from the writing side device while reading from the first temporary register group is being performed, the second 3. The write to the main register group subject to the second write request is performed without storing the data of the main register group subject to the write request in the first temporary register. Data transfer circuit. A second temporary register that temporarily holds data held in a second main register group arbitrarily selected from the plurality of main register groups;
When a read request for any of the main register groups is received from the read side device while writing to the main register group that is the target of the read request is not performed, the main register that is the target of the read request 4. The data transfer according to claim 1, wherein after the entire data held in the group is stored in the second temporary register group, the data is read out from the second temporary register group and output. circuit. In the data transfer circuit that outputs the data received from the writing device to the reading device,
A plurality of main register groups for holding data received from the writing side device;
Each having a first and a second temporary register group for temporarily holding data held in first and second register groups arbitrarily selected from the plurality of main register groups,
When a write request is received from any one of the main register groups from the writing side device, if the write request is received while reading from the first temporary register is not performed, The entire data held in the main register group subject to the write request is stored in the first temporary register group, and then writing to the main register group subject to the write request is started.
If received while reading from the first temporary register, the write request is made without storing the data of the target main register group of the write request in the first temporary register. To the target main register group,
When a read request for any of the plurality of main register groups is received from the read side device, the read request is for the main register group that is the target of the write request, and the write If received during the write to the main register group to be requested, the data stored in the first temporary register group is read and output,
In other cases, the entire data held in the main register group subject to the read request is stored in the second temporary register group, and then read from the second temporary register group and output. A data transfer circuit.   Between each of the plurality of main register groups and the first temporary register, a wiring having a bit width capable of simultaneously transferring data having the number of bits that can be stored in the corresponding main register group is provided. The data transfer circuit according to claim 1.   Between each of the plurality of main register groups and each of the first and second temporary register groups, a wiring having a bit width capable of simultaneously transferring data of the number of bits that can be stored in the corresponding main register group is provided. 6. The data transfer circuit according to claim 4, wherein the data transfer circuit is provided.

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