JP4844274B2 - A / D conversion circuit - Google Patents

Description

  The present invention relates to an A / D conversion circuit, and more particularly to a parallel type A / D conversion circuit.

  Conventionally, a parallel A / D conversion circuit (hereinafter referred to as “folding ADC”) using a folding amplifier and an interpolation circuit is known (for example, see Non-Patent Document 1). ).

  The folding ADC is composed of a reference voltage generation unit that generates a plurality of reference voltages of different levels and their inverted voltages, and a positive phase signal and an opposite phase signal of these reference voltages, their inverted voltages, and analog input signals, respectively. A plurality of folding amplifiers that generate differential signals (hereinafter referred to as “folding signals”), an interpolation circuit that interpolates the folding signals output from these folding amplifiers, and this interpolation It comprises a plurality of comparators for inputting a plurality of interpolation signals generated by the circuit, and an encoder circuit for encoding the output from these comparators.

  The folding ADC can thus realize a high-speed analog-digital conversion operation by arranging a plurality of comparators in parallel and operating them simultaneously.

  Incidentally, the interpolation circuit of the folding ADC includes a plurality of resistors that generate a plurality of interpolation signals from a plurality of folding signals output from the folding amplifier. That is, interpolation is performed by a plurality of resistors (hereinafter, such interpolation is referred to as “resistance interpolation”).

  In the resistance interpolation, an interpolation signal is generated by combining a positive phase signal and a negative phase signal of two signals. That is, as described in Non-Patent Document 1, an interpolation signal is generated by combining a normal phase signal and a negative phase signal that are folding signals output from two folding amplifiers.

  As shown in FIG. 13, by using the positive-phase signals Q and I of two folding signals (here, sine waves that are ideal signal waveforms) and their opposite-phase signals XQ and XI, they are indicated by dotted lines. The interpolated signal is obtained from the two folding signals by using the positive phase signals Q and I and the opposite phase XQ and XI.

  The interpolation signal shown in FIG. 13 can be obtained by an interpolation circuit 101 as shown in FIG.

  That is, the interpolation circuit 101 is connected in series between the resistors R101 to R104 connected in series between the positive phase signal Q and the negative phase signal XI, and between the negative phase signal XQ and the positive phase signal I. Resistors R111 to R114, resistors R121 to R124 connected in series between the positive phase signal Q and the positive phase signal I, and resistors R131 connected in series between the negative signal XQ and the negative phase signal XI. To R134. Then, the voltages (V1 to V6, XV1 to XV6) between the resistors, the positive phase signals Q and I, and the negative phase signals XQ and XI are output from the interpolation circuit 101 as interpolation signals.

  Thus, the interpolation circuit 101 can obtain a quadruple interpolation signal from the normal phase signals Q and I of the two folding signals and the negative phase signals XQ and XI.

  However, in the interpolation circuit 101 shown in FIG. 14, the connection line between the resistor R104 and the negative phase signal XI and the connection line between the resistor R114 and the negative phase signal XI are longer than the other connection lines. End up.

  Therefore, the parasitic components (resistance component Rp1, capacitance component Cp1) for the positive phase signal I and its negative phase signal XI are the parasitic components for the positive phase signal Q, its negative phase signal XQ and the interpolation signals V1 to V6, XV1 to XV6 ( The resistance component Rp2 and the capacitance component Cp2) become extremely large.

  As shown in FIG. 15, the parasitic components (resistance component Rp1, capacitance component Cp1) are equal in number to the number of folding amplifiers 110-1 to 110-Namp in the folder block 100 and the resistance block 111 between the folding amplifier outputs. It depends on the number of resistors Nint (in this case, 4) in .about.114. That is, the number of folding amplifiers Namp is increased in proportion to the number (Namp × Nint) obtained by multiplying the number of resistances Nint in the resistance block.

  Thus, when large parasitic components (resistance component Rp1, capacitance component Cp1) are generated, the distortion of the signal output from the interpolation circuit 101 increases, and as a result, the accuracy of the folding ADC deteriorates. Will end up.

  In addition, as described in Non-Patent Document 2 and Non-Patent Document 3, an attempt is made to increase the speed and accuracy by cascading folder / interpolation blocks made up of folder blocks and interpolation circuits in two stages. However, in such a folding ADC, a large parasitic component (resistance component Rp1, capacitance component Cp1) is generated as described above, and the accuracy of the folding ADC is further deteriorated.

  Therefore, as shown in FIG. 16, the A / D conversion in which the resistance and the resistance wiring are arranged in consideration of the resistance component associated with the wiring between the resistors in the interpolation circuit (hereinafter referred to as “resistance wiring”). A circuit has been proposed (see Patent Document 1).

  In the A / D conversion circuit described in Patent Document 1, the resistance wiring is arranged so that not only the resistance component but also the capacitance component is equal among the parasitic components due to the resistance wiring.

Thus, in the A / D conversion circuit using the interpolation circuit of Patent Document 1, the accuracy of the A / D conversion circuit is improved by arranging the parasitic components due to the resistance wiring to be equal. I have to.
Outside AAAbidi, “A 10-b, 75-MHz Two-Stage Pipelined Bipolar AD Converter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO.12, DECEMBER 1993, pp1187-1197 Pieter VorenKamp, “A 12-b, 60-MSample / s Cascaded Folding and Interpolating ADC” IEEE Journal of Solid-State Circuits, 1997 Klaas Bult et al., “An Embedded 240-mW 10-b 50-MS / s CMOS ADC in 1-mm2”, IEEE Journal of Solid-State Circuits, 1997 JP 2001-7701 A

  However, the A / D conversion circuit described in Patent Document 1 has the following problems.

  First, as shown in FIG. 16, in the A / D conversion circuit described in Patent Document 1, resistances in the interpolation circuit are connected by a plurality of bent resistance wires. Will become longer.

  Moreover, as shown in FIG. 17, in the A / D conversion circuit described in Patent Document 1, since there are many portions where different resistance wirings are close to each other, many coupling capacitances are generated. Accordingly, the accuracy of the folding ADC cannot be sufficiently improved.

  Secondly, in the A / D conversion circuit described in Patent Document 1, as shown in FIG. 16, since the left and right are substantially symmetrical wiring structures, the A / D conversion circuit is manufactured by a CMOS process. Sometimes the variation becomes large. This occurs because impurities are introduced into the source / drain regions by oblique ion implantation in the CMOS process.

  The problem to be solved by the present invention is as described above, and in order to solve such a problem, the invention described in claim 1 is directed to a normal-phase and reverse-phase folding signal based on different reference voltages and analog input signals, respectively. A plurality of folding amplifiers that generate and output, an interpolation circuit that has a plurality of resistors and generates a plurality of in-phase and anti-phase interpolation signals from the output of the folding amplifier, and generated by this interpolation circuit In an A / D conversion circuit including a plurality of comparators that input interpolation signals to be input and an encoder circuit that encodes outputs from these comparators, the interpolation circuit sets the plurality of resistors for each predetermined number. Separately, a plurality of resistor rows in which the predetermined number of resistors are connected in series on a straight line are arranged in parallel. The resistors at one end are connected to each other in every two columns, and the resistors at the other end of each resistor column are connected to every two columns in a combination different from the combination of the two columns. Are connected in a ring shape.

  According to a second aspect of the present invention, in the first aspect of the invention, the plurality of comparators are input signals to the A / D conversion circuit, and are input from a low reference voltage to a high reference voltage. Corresponding to each of the signals, and sequentially from the comparator corresponding to the input signal of the low reference voltage to the comparator corresponding to the input signal intermediate between the low reference voltage and the high reference voltage in the predetermined direction along the resistor string. The comparators are arranged in the order opposite to the predetermined direction from the comparator corresponding to the intermediate input signal to the comparator corresponding to the input signal of the high reference voltage.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the plurality of folding amplifiers each include a reference voltage for each predetermined voltage interval between a low reference voltage and a high reference voltage. And the analog input signal to generate a positive-phase folding signal, and generate a negative-phase folding signal from the negative-phase voltage of the reference voltage and the negative-phase signal of the analog input signal for each predetermined voltage interval. The second folding amplifier includes a first folding amplifier in which the start position of the predetermined voltage interval is the low-order reference voltage, and a second position in which the start position is shifted to the high-order side in order from the first folding amplifier. To the Nth folding amplifier, the first folding amplifier From the N / 2 + 1th folding amplifier to the Nth folding amplifier in order in the reverse direction to the predetermined direction. Features.

  According to a fourth aspect of the present invention, there are provided a plurality of first folding amplifiers for generating and outputting positive and negative phase folding signals based on different reference voltages and analog input signals, respectively, and a plurality of first resistors. And a plurality of first interpolation circuits that generate a plurality of in-phase and anti-phase first interpolation signals from the output of the first folding amplifier, and a plurality of first-phase interpolation signals that are different from each other in normal phase and anti-phase. A plurality of second folding amplifiers that generate and output a second folding signal; and a plurality of second resistors that generate a plurality of in-phase and anti-phase second interpolation signals from the output of the second folding amplifier. A second interpolation circuit, a plurality of comparators for inputting the second interpolation signal, and outputs from these comparators. In the A / D conversion circuit including the encoder circuit, the first interpolation circuit divides the plurality of first resistors into a predetermined number, and the predetermined number of the first resistors are arranged on a straight line. A plurality of first resistance rows connected in series are arranged in parallel, the first resistors at one end of each first resistor row are connected to each other every two rows, and the first resistor at the other end of each first resistor row is connected. The plurality of first resistors are connected in series in a meandering manner, and the second interpolation circuit is connected to the plurality of second lines. The resistors are divided into predetermined numbers, and a plurality of second resistor rows in which the predetermined number of second resistors are connected in series on a straight line are arranged in parallel, and two second resistors at one end of each second resistor row are connected to each other. Each column is connected, and the second resistors at the other end of each second resistor column are connected to each other. Characterized in that said plurality of second resistors respectively connected to every two columns of different combinations were connected in a loop of the combination of.

  According to the first aspect of the present invention, in the interpolation circuit, a plurality of resistors are divided into a predetermined number, and a plurality of resistor rows in which the predetermined number of resistors are connected in series on a straight line are arranged in parallel. Resistors at one end of the resistor string are connected to each other every two columns, and resistors at the other end of each resistor string are connected to each other every two columns in a combination different from the combination of the two columns. Since the plurality of resistors are connected in a ring shape, the bent connection between the resistors in the interpolation circuit can be minimized, and the wiring length between the resistors can be shortened. In addition, the coupling capacitance is generated only between the adjacent wirings, and the parasitic capacitance is not increased.

  Further, since it does not become a mirror wiring, even when the A / D conversion circuit is manufactured by a CMOS process, the manufacturing variation does not increase. That is, in the CMOS process in which the impurity introduction into the source / drain regions is oblique ion implantation, if the mirror wiring is used, manufacturing variation increases, but the above configuration does not result in the mirror wiring.

  According to the second aspect of the invention, the comparator corresponding to the intermediate input signal between the low reference voltage (VRB) and the high reference voltage (VRT) is changed from the comparator corresponding to the input signal of the low reference voltage (VRB). In order from the comparator corresponding to the intermediate input signal to the comparator corresponding to the input signal of the high-level reference voltage (VRT), the array is arranged in the reverse direction to the predetermined direction. The connection from the interpolation circuit to the plurality of comparators can be made without bending.

  According to the third aspect of the present invention, a positive-phase folding signal is generated based on the reference voltage and the analog input signal for each predetermined voltage interval between the lower reference voltage and the higher reference voltage, and the predetermined voltage interval is set. A reverse-phase folding signal is generated from the negative-phase voltage of each reference voltage and the negative-phase signal of the analog input signal, and a plurality of folding amplifiers are set to a low-level reference voltage at the start position of a predetermined voltage interval. The first folding amplifier and the second to Nth folding amplifiers whose start positions are shifted in order from the first folding amplifier in order, and N / 2 from the first folding amplifier. The first and second folding amplifiers are sequentially arranged in a predetermined direction along the resistor string, and the N / 2 + 1th Since the O Lumpur Funding amplifier arranged side by side in the predetermined direction and the opposite direction in order toward the N-th folding amplifier, it is possible to perform without bending the connection from the interpolation circuit to a plurality of comparators.

  According to a fourth aspect of the present invention, in the first interpolation circuit, the plurality of first resistors are divided into predetermined numbers, and the predetermined number of first resistors are connected in series on a straight line. A plurality of one resistor rows are arranged in parallel, the first resistors at one end of each first resistor row are connected to each other every two rows, and the first resistors at the other end of each first resistor row are connected to the two Since a plurality of first resistors are connected in series in a meandering manner to each of two columns in a combination different from the combination of columns, the connection from the plurality of first folding amplifiers to the second folding amplifier in the subsequent stage is bent. Since the connection to the second folding amplifier in the subsequent stage becomes extremely short, the parasitic capacitance can be reduced. In the second interpolation circuit, a plurality of second resistors are divided into a predetermined number, and a plurality of second resistor rows in which the predetermined number of second resistors are connected in series on a straight line are arranged in parallel. Two columns in one combination of the two resistance columns are connected to each other every two columns, and the second resistors in the other end of each second resistor column are connected in two columns different from the combination of the two columns. Since the plurality of second resistors are connected in a ring shape each time, the bending connection between the resistors in the second interpolation circuit can be suppressed to a minimum, and the wiring length between the resistors can be shortened. Can do. In addition, the coupling capacitance is generated only between the adjacent wirings, and the parasitic capacitance is not increased. Further, since it does not become a mirror wiring, even when the A / D conversion circuit is manufactured by a CMOS process, the manufacturing variation does not increase. That is, in the CMOS process in which the impurity introduction into the source / drain regions is oblique ion implantation, if the mirror wiring is used, manufacturing variation increases, but the above configuration does not result in the mirror wiring.

  The A / D conversion circuit according to the embodiment of the present invention includes a plurality of folding amplifiers that generate and output a positive-phase and a negative-phase folding signal based on different reference voltages and analog input signals, and a plurality of resistors. An interpolation circuit that generates multiple in-phase and anti-phase interpolation signals from the output of the folding amplifier, a plurality of comparators that input the interpolation signals generated by the interpolation circuit, and an output from these comparators And an encoder circuit.

  In addition, the interpolation circuit divides a plurality of resistors into predetermined numbers, and provides a plurality of resistor rows in which the predetermined number of resistors are connected in series on a straight line, and two resistors at one end of each resistor row are connected to each other. Each column (each combination of the first column) is connected to each other, and the resistance at the other end of each resistor column is different from the combination of the first column for every two columns (each combination of the second column) And a plurality of resistors are connected in series in a ring.

  Therefore, the bent connection between the resistors in the interpolation circuit can be minimized, and the wiring length between the resistors can be shortened. In addition, the coupling capacitance is generated only between the adjacent wirings, and the parasitic capacitance is not increased.

  Further, since it does not become a mirror wiring, even when the A / D conversion circuit is manufactured by a CMOS process, the manufacturing variation does not increase. That is, in the CMOS process in which the impurity introduction into the source / drain regions is oblique ion implantation, if the mirror wiring is used, manufacturing variation increases, but the above configuration does not result in the mirror wiring.

  The plurality of comparators are input signals to the A / D conversion circuit and correspond to input signals from a low-level reference voltage to a high-level reference voltage, respectively, and from the comparators corresponding to the low-level reference voltage input signals. Arranged in the specified direction along the resistor string in order through the comparator corresponding to the intermediate input signal between the low reference voltage and the high reference voltage, and sequentially from the comparator corresponding to the intermediate input signal to the comparator corresponding to the input signal of the high reference voltage. They are arranged side by side in the direction opposite to the predetermined direction.

  As a result, the connection from the interpolation circuit to the plurality of comparators can be made without bending.

  Each of the plurality of folding amplifiers generates a positive-phase folding signal based on the reference voltage and the analog input signal for each predetermined voltage interval between the lower reference voltage and the higher reference voltage, and reverses the reference voltage for each predetermined voltage interval. A phase-folding signal is generated based on the phase voltage and the negative-phase signal of the analog input signal, and a plurality of folding amplifiers, a first folding amplifier having a low-level reference voltage at the start position of the predetermined voltage interval, The first folding amplifier is composed of second to Nth folding amplifiers whose start positions are shifted in order from the first folding amplifier, and the resistors are sequentially applied from the first folding amplifier to the N / 2nd folding amplifier. N / 2 + 1 fall Are arranged side by side in a direction reverse to the predetermined direction in order toward the N-th folding amplifiers from Inguanpu.

  As a result, the connection from the plurality of folding amplifiers to the interpolation circuit can be performed without bending.

  Further, another A / D conversion circuit according to the embodiment of the present invention includes a plurality of first folding amplifiers that generate and output a positive-phase and a negative-phase folding signal based on different reference voltages and analog input signals, and a plurality of first folding amplifiers. A plurality of first interpolation circuits that generate a plurality of in-phase and anti-phase first interpolation signals from the output of the first folding amplifier, and different positive phases from the plurality of first interpolation signals, respectively. And a plurality of second folding amplifiers that generate and output a second folding signal having a negative phase and a plurality of second resistors, and a plurality of second interpolation signals having the same phase and a negative phase are output from the output of the second folding amplifier. A plurality of second interpolation circuits to be generated, a plurality of comparators for inputting the second interpolation signal, and outputs from these comparators And an encoder circuit for encoding.

  The first interpolation circuit divides the plurality of first resistors into a predetermined number and arranges a plurality of first resistor rows in which the predetermined number of first resistors are connected in series on a straight line. First resistances at one end of one resistance row are connected to each other every two rows (every combination of third rows), and first resistances at the other end of each first resistance row are connected to each other in the two rows. The plurality of first resistors are connected in series in a meandering manner by being connected to every two columns (each combination of the fourth column) of a combination different from the combination.

  As a result, it is possible to connect the plurality of first folding amplifiers to the second folding amplifier in the subsequent stage without bending, and the connection to the second folding amplifier in the subsequent stage becomes extremely short, thereby reducing the parasitic capacitance. be able to.

  The second interpolation circuit divides a plurality of second resistors into a predetermined number and arranges a plurality of second resistor rows in which the predetermined number of second resistors are connected in series on a straight line. The second resistors at one end of the two resistor rows are connected to each other every two rows (every combination of the fifth row), and the second resistors at the other end of each second resistor row are connected to each other in the two rows. Each of the plurality of second resistors is connected in a ring by connecting to every two columns (for each combination of the sixth column) of a combination different from the combination.

  Therefore, the bent connection between the resistors in the second interpolation circuit can be minimized, and the wiring length between the resistors can be shortened. In addition, the coupling capacitance is generated only between the adjacent wirings, and the parasitic capacitance is not increased. Further, since it does not become a mirror wiring, even when the A / D conversion circuit is manufactured by a CMOS process, the manufacturing variation does not increase. That is, in the CMOS process in which the impurity introduction into the source / drain regions is oblique ion implantation, if the mirror wiring is used, manufacturing variation increases, but the above configuration does not result in the mirror wiring.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an outline of an A / D conversion circuit 1 according to the first embodiment of the present invention. In the first embodiment, the folding ADC of upper 3 bits and lower 4 bits will be described as an example.

  As shown in FIG. 1, the A / D conversion circuit 1 includes a reference voltage generation unit 2 that generates positive phase reference voltages Vr1 to Vr64 and reverse phase reference voltages XVr1 to XVr64, and a signal corresponding to the upper 3 bits. A high-order bit conversion unit 3 for outputting a signal, an encoder circuit 4 for encoding a signal output from the high-order bit conversion unit 3, a low-order bit conversion unit 5 for outputting a signal corresponding to the low-order 4 bits, And an encoder circuit 6 that encodes a signal output from the bit converter 5.

  The lower bit converter 5 includes a folder block 10 having a plurality of folding amplifiers, an interpolation circuit 11 having a plurality of resistors, and a plurality of comparators (comparators) 13a to 13p.

  Here, the upper 3 bits are a well-known conversion unit and encoder circuit, and are not a characteristic part of the present invention, so detailed description thereof will be omitted, and portions relating to the lower 4 bits will be described in detail below.

  The lower 4 bits are converted by the folder block 10 and the interpolation circuit 11. In order to perform 4-bit conversion, 15 zero-cross signals are required. FIG. 2 shows the number of folding amplifiers Namp and the number of interpolations Nint necessary to generate 15 zero-cross signals.

  As shown in FIG. 2, in the lower 4 bits conversion, there are a plurality of combinations of the number of folding amplifiers Namp and the number of interpolations Nint, but in the first embodiment, the number of folding amplifiers Namp is 8, The configuration will be specifically described with reference to FIG. 3 as a combination in which the number of adjustments Nint is two.

  As shown in FIG. 3, the folder block 10 receives different reference voltages and normal-phase and negative-phase analog input signals, respectively, and generates a folding signal composed of a positive-phase signal and a negative-phase signal having different phases. And a plurality of folding amplifiers 14a to 14h for output.

  As shown in FIG. 4A, the reference voltage generator 2 includes 63 resistors R10 connected in series between a low reference voltage (VRB) and a high reference voltage (VRT). Positive-phase reference voltages Vr1 to Vr64 are generated by the tap voltage drawn from between R10, the low-order reference voltage (VRB), and the high-order reference voltage (VRT). With this configuration, the positive-phase reference voltages Vr1 to Vr64 are voltages that increase in voltage from the low-level reference voltage (VRB) Vr1 to the high-level reference voltage (VRT) Vr64 in order at equal intervals. .

  In addition, as shown in FIG. 4B, the reference voltage generator 2 has 63 resistors R10 connected in series between a low reference voltage (VRB) and a high reference voltage (VRT). The reference voltages XVr64 to XVr1 having opposite phases are generated by the tap voltage drawn from between the resistors R10, the low reference voltage (VRB), and the high reference voltage (VRT). Because of this configuration, the negative-phase reference voltages XVr1 to XVr64 are voltages whose voltage decreases at equal intervals from XVr1 that is the higher reference voltage (VRT) to XVr64 that is the lower reference voltage (VRB) in order. .

  As described above, the reference voltage generation unit 2 is configured so that the positive phase reference voltages Vr1 to Vr64 whose voltages increase at equal intervals from the low level reference voltage (VRB) to the high level reference voltage (VRT) and the inverse of these reference voltages Vr1 to Vr64. Phase reference voltages XVr1 to XVr64 are generated and output to a plurality of folding amplifiers 14a to 14h.

  The plurality of folding amplifiers 14a to 14h are respectively provided with reference voltages Vr (8N + 1) / XVr (8N + 1), Vr (8N + 2) / XVr (8N + 2), Vr (8N + 3) / XVr (8N + 3), Vr (8N + 4) / XVr (8N + 4). ), Vr (8N + 5) / XVr (8N + 5), Vr (8N + 6) / XVr (8N + 6), Vr (8N + 7) / XVr (8N + 7), Vr (8N + 8) / XVr (8N + 8). Here, N is an integer from 0 to 7. Each of the folding amplifiers 14a to 14h adds the result of comparing the reference voltage of N = 0, 2, 4, 6 and the input voltage Vip (Vin), and the reference voltage of N = 1, 3, 5, 7 And the input voltage Vip (Vin) are subtracted to generate and output folding signals VFA1 / XVFA1 to VFA8 / XVFA8 (see FIG. 5).

  In this way, each of the folding amplifiers 14a to 14h has a first predetermined voltage interval between the low reference voltage VRB and the high reference voltage VRT (here, the potential difference between the high reference voltage VRT and the low reference voltage VRB is 8). The normal-phase folding signals FA1 to VFA8 are generated by the reference voltage and the analog input signal Vip, and the negative-phase voltage of the reference voltage at the first predetermined voltage interval and the negative-phase analog input signal Vin Folding signals XVFA1 to XVFA8 are generated, and a plurality of folding amplifiers 14a to 14h are used as a first folding amplifier having a low reference voltage VRB as a start position of a predetermined voltage interval, and the first folding amplifier 14a. The second position where the start position is shifted by one reference voltage to the higher position in order from To 8th folding amplifiers 14b to 14h.

  The interpolation circuit 11 includes a plurality of resistors R1 to R16, R1 'to R16'.

  This interpolation circuit 11 has a plurality of resistors R1 to R16, R1 ′ to R16 ′ (a number obtained by multiplying the number of folding amplifiers Namp by the number of interpolations Nint divided by 2; Namp × Nint / 2. A plurality of resistor rows in which the predetermined number of resistors are connected in series on a straight line are arranged in parallel, and the resistors at one end of each resistor row are arranged in two rows (each combination of the first row). Are connected to each other, and the resistors at the other end of each resistor row are respectively connected to every two rows (each combination of the second row) of a combination different from the combination of the first row, and the plurality of resistors are connected. They are connected in series in a circular shape.

  That is, a total of 32 resistors R1 to R16 and R1 ′ to R16 ′ connected in series are divided into 8 pieces to form a plurality of rows, and both ends are folded so that the eighth and ninth pieces are folded back. Further, both ends are connected so that the 16th and 17th folds are folded back, and both ends are connected so that the 24th and 25th folds are folded back. Here, there are a total of four resistance rows R1 to R8, R9 to R16, R1 'to R8', R9 'to R16'.

  Thus, when interpolating between outputs of Namp folder blocks 10 by Nint times, (Namp × Nint × 2) resistors are connected in series. These series resistors are (Namp × Nint / By folding back every 2), the bent connection between the resistors in the interpolation circuit 11 can be suppressed to a minimum, and the wiring length between the resistors can be shortened. In addition, the coupling capacitance is generated only between the adjacent wirings, and the parasitic capacitance is not increased.

  Further, since it does not become a mirror wiring, even when the A / D conversion circuit is manufactured by a CMOS process, the manufacturing variation does not increase. That is, in the CMOS process in which the impurity introduction into the source / drain regions is oblique ion implantation, if the mirror wiring is used, manufacturing variation increases, but the above configuration does not result in the mirror wiring.

The plurality of comparators 13a to 13p correspond to the input signals of the A / D conversion circuit 1 from the low level reference voltage VRB to the high level reference voltage VRT, respectively, and from the comparators 13a corresponding to the input signals of the low level reference voltage VRB. The comparator 13h corresponding to the intermediate input signal between the low reference voltage VRB and the high reference voltage VRT is sequentially arranged in a predetermined direction along the resistor string, and the comparator 13i corresponding to the intermediate input signal is changed to the input signal of the high reference voltage VRT. The corresponding comparators 13p are arranged in order in the opposite direction to the predetermined direction.

As a result, the connection from the interpolation circuit 11 to the plurality of comparators 13a to 13p can be performed without bending.

  In FIG. 3, the comparator 13p is connected in order to equalize the load like the other signal lines. However, if it is not used for digital conversion, it is not necessary to connect to the encoder circuit 6.

  Each of the plurality of folding amplifiers 14a to 14h generates a positive-phase folding signal based on a reference voltage and a positive-phase analog input signal Vip for each predetermined voltage interval from the low-level reference voltage VRB to the high-level reference voltage VRT. , A negative-phase folding signal is generated from the negative-phase voltage of the reference voltage and the negative-phase signal Vin of the negative-phase analog input signal Vip at predetermined voltage intervals, and the plurality of folding amplifiers 14a to 14h are The first folding amplifier 14a having the start position of the interval as a low reference voltage, and the second to eighth folding amplifiers 14b to 14b, whose start positions are shifted in order from the first folding amplifier 14a to the high order side. 14h, 4 from the first folding amplifier Arranged in a predetermined direction toward the eyes of the folding amplifiers along the resistor string in the order, they are arranged side by side in a direction reverse to the predetermined direction in order from the 5 th folding amplifiers toward the eighth folding amplifiers.

  As a result, the connection from the plurality of folding amplifiers 14a to 14h to the interpolation circuit 11 can be performed without bending.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. In the first embodiment, a one-stage folder / interpolation configuration has been described. In the second embodiment, a two-stage folder / interpolation configuration will be described. FIG. 6 is a block diagram showing an outline of the A / D conversion circuit 20 according to the second embodiment of the present invention, and FIG. 7 is a block diagram showing a part of the A / D conversion circuit 20 of the second embodiment. In the second embodiment, an upper 3 bits and lower 4 bits folding ADC will be described as an example.

  As shown in FIG. 6, the A / D conversion circuit 20 includes a reference voltage generation unit 30 that generates reference voltages Vr1 to Vr9, an upper bit conversion unit 31 that outputs a signal corresponding to upper 3 bits, An encoder circuit 33 that encodes a signal output from the bit conversion unit 3, a lower bit conversion unit 32 for outputting a signal corresponding to the lower 4 bits, and an encoder that encodes a signal output from the lower bit conversion unit 32 34.

  The lower bit conversion unit 32 includes a first folder interpolation circuit including a first folder block 42 having a plurality of first folding amplifiers and a first interpolation circuit 43 having a plurality of first resistors. 40. Further, a second folder interpolation circuit 41 including a second folder block 44 having a plurality of second folding amplifiers and a second interpolation circuit 45 having a plurality of second resistors, and a plurality of comparators (comparators). ) 52a to 52p.

  Here, since the upper 3 bits, the folding signal needs to be folded eight times. When the folding signal folding signal is performed by two-stage folder interpolation, as shown in FIG. 7, the first folder interpolation circuit 40 having three sets of first folding amplifiers 50a to 50c in the previous stage is provided in the subsequent stage. Are provided with a second folder interpolation circuit 41 having four sets of second folding amplifiers 51a to 51d, and these are cascaded to obtain a folded signal that is folded eight times as shown in FIG. Can do.

  The reference voltage generator 30 divides the input normal phase signal Vip and its negative phase signal Vin from the VRB side, which is a voltage range that can be digitally converted, from the VRB side at equal intervals, so that the positive phase reference voltages Vr1 to Vr9 and The reference voltages XVr1 to XVr9 having opposite phases are output.

  In the first folder interpolation circuit 40 in the first stage, the reference voltages are (Vr1 / XVr1, Vr4 / XVr4, Vr7 / XVr7), (Vr2 / XVr2, Vr5 / XVr5, Vr8 / XVr8), (Vr3 / The outputs (VO1 / XVO1, VO5 / XVO5, VO9 / XVO9) of the three sets of the first folding amplifiers 50a to 50c, which are XVr3, Vr6 / XVr6, Vr9 / XVr9), are folded three times by four-fold resistance interpolation. Four zero cross signals are obtained.

  Next, in the second folder / interpolation circuit 41 at the subsequent stage, in order to obtain eight folding signals, folding signals (3 × 4 = 12) output from the first folder / interpolation circuit 40 at the first stage. VO1 / XVO1 to VO12 / XVO12) from the VRB side (VO1 / XVO1, VO5 / XVO5, VO9 / XVO9), (VO2 / XVO2, VO6 / XVO6, VO10 / XVO10), (VO3 / XVO3, VO7 / XVO7, VO11 / XVO11), (VO4 / XVO4, VO8 / XVO8, VO12 / XVO12) are used in four sets of folding amplifiers. Furthermore, the four folding signals (VA1 / XVA1 to VA4 / XVA4) output from the four sets of folding amplifiers are converted into 16 zero cross signals by quadruple resistance interpolation, and are determined using the comparators 52a to 52p. A / D conversion of the lower 4 bits is possible.

  A more specific configuration of the A / D conversion circuit 20 configured as described above will be described with reference to FIG.

  As shown in FIG. 7, the reference voltage generator 30 includes positive phase reference voltages Vr <b> 1 to Vr <b> 9 equally divided from an input low reference voltage VRB and a high reference voltage VRT from a low reference voltage VRB to a high reference voltage VRT. The negative phase reference voltages XVr <b> 1 to XVr <b> 9 are generated and output to the first folder block 42. The A / D conversion circuit 20 converts an input signal in the range of voltages VRB to VRT into a digital signal as described above.

  The first folder block 42 includes a plurality of first folding amplifiers 50a to 50c.

  The first folding amplifier 50a includes an amplifier 61a that compares the positive-phase input signal Vip (see FIG. 8D) and the reference voltage Vr1, and an amplifier 61b that compares the positive-phase input signal Vip and the reference voltage Vr4. , An amplifier 61c that compares the positive phase input signal Vip and the reference voltage Vr7, adds the outputs of the amplifier 61a and the amplifier 61c, subtracts the output of the amplifier 61b, and outputs the positive phase signal VO1. The positive phase signal VO1 output in this way has zero cross points in the reference voltages Vr1, Vr4, Vr7 as shown in FIG. 8C.

  In addition, the first folding amplifier 50a includes an amplifier 61a that compares the input signal Vin of the opposite phase with the reference voltage XVr1, an amplifier 61b that compares the input signal Vin of the opposite phase and the reference voltage XVr4, and an input signal of the opposite phase. An amplifier 61c that compares Vin with the reference voltage XVr7 is provided. The outputs of the amplifier 61a and the amplifier 61c are added, and the output of the amplifier 61b is subtracted to obtain a negative phase signal XVO1 that is opposite in phase to the positive phase signal VO1. Output.

  The first folding amplifier 50b includes an amplifier 62a that compares the positive phase input signal Vip and the reference voltage Vr2, an amplifier 62b that compares the positive phase input signal Vip and the reference voltage Vr5, and a positive phase input signal Vip. An amplifier 62c for comparing with the reference voltage Vr8 is provided. The outputs of the amplifier 62a and the amplifier 62c are added, and the output of the amplifier 62b is subtracted to output a positive phase signal VO5. The positive phase signal VO5 output in this way has zero cross points in the reference voltages Vr2, Vr5, Vr8 as shown in FIG. 8B.

  The first folding amplifier 50b includes an amplifier 62a that compares the negative-phase input signal Vin and the reference voltage XVr2, an amplifier 62b that compares the negative-phase input signal Vin and the reference voltage XVr5, and a negative-phase input signal. An amplifier 62c that compares Vin with the reference voltage XVr8 is provided. The outputs of the amplifier 62a and the amplifier 62c are added, and the output of the amplifier 62b is subtracted to obtain a negative phase signal XVO5 that is opposite in phase to the positive phase signal VO5. Output.

  The first folding amplifier 50c includes an amplifier 63a that compares the positive phase input signal Vip and the reference voltage Vr3, an amplifier 63b that compares the positive phase input signal Vip and the reference voltage Vr6, and a positive phase input signal Vip. An amplifier 63c for comparing with the reference voltage Vr9 is provided. The outputs of the amplifier 63a and the amplifier 63c are added, and the output of the amplifier 63b is subtracted to output a normal phase signal VO9. The positive phase signal VO9 output in this way has zero cross points in the reference voltages Vr3, Vr6, and Vr9, as shown in FIG.

  The first folding amplifier 50c includes an amplifier 63a that compares the negative-phase input signal Vin and the reference voltage XVr3, an amplifier 63b that compares the negative-phase input signal Vin and the reference voltage XVr6, and a negative-phase input signal. An amplifier 63c that compares Vin with the reference voltage XVr9 is provided. The outputs of the amplifier 63a and the amplifier 63c are added, and the output of the amplifier 63b is subtracted to obtain a negative-phase signal XVO9 that is opposite in phase to the positive-phase signal VO9. Output.

  The first interpolation circuit 43 includes first resistors Ra1 to Ra12, Rb1 to Rb12. Interpolation signals VO1 to VO12 are generated by these first resistors, and as shown in FIG. A folding waveform can be acquired.

  The first interpolation circuit 43 divides a plurality of first resistors Ra1 to Ra12 and Rb1 to Rb12 into a predetermined number, and arranges a plurality of resistor strings in which the predetermined number of first resistors are connected in series on a straight line. The first resistors at one end of each resistor row are connected to each other every two rows (each combination of third rows), and the first resistors at the other end of each resistor row are connected to the third row. A plurality of first resistors Ra1 to Ra12 and Rb1 to Rb12 are connected in series in a meandering manner, each connected to every two columns (each combination of the fourth column) of a combination different from the above combination.

  Here, if the number of folding amplifiers in the first interpolation circuit 43 is Namp2, the number of interpolations is Nint2, and the second folder interpolation circuit 41 in the subsequent stage needs a folding signal Nf12 times, The predetermined number is (Namp2 × Nint2) / (Nf12 × Nint2 / 2).

  Here, since Namp2 = 4, Nint2 = 4, and Nf12 = 4, the predetermined number is 2. Therefore, as shown in FIG. 7, a plurality of first resistors Ra1 to Ra12 and Rb1 to Rb12 connected in series are divided into a total of 24 first resistors to form a plurality of rows. 3rd, 4th and 5th, 6th and 7th, 8th and 9th, 10th and 11th, 12th and 13th, 14th and 15th Connect the both ends so that the eyes, the 16th and 17th, the 18th and 19th, the 20th and 21st, the 22nd and 23rd, and the 1st and 24th, respectively. Connect the eyes.

  In this way, when interpolating between the outputs of the Namp first folding amplifiers 50a to 50c by Nint times, Namp × Nint × 2 resistors are connected in series, and these series resistors are {(Namp2 It is possible to perform the connection from the plurality of first folding amplifiers 50a to 50c to the second folder block 44 in the subsequent stage without bending by folding back at every × Nint2) / (Nf12 × Nint2 / 2)}. Since the connection to the second folder block 44 is extremely short, the parasitic capacitance can be reduced.

  That is, in the prior art, the reference voltages are (Vr1 / XVr1, Vr4 / XVr4, Vr7 / XVr7), (Vr2 / XVr2, Vr5 / XVr5, Vr8 / XVr8), (Vr3 / XVr3, Vr6 / XVr6, Vr9 / XVr9). The three folding amplifiers 50a ′, 50c ′, and 50b ′ are arranged in order to form the second interpolation circuit as shown in FIG. 11, but now the second folder block 44 is moved to the subsequent stage. As a result, a large number of couplings occur and the parasitic capacitance increases. As a result, the accuracy of the folding ADC has deteriorated.

  Therefore, in the A / D conversion circuit 20 of the second embodiment, the first folding amplifiers 50a to 50c and the first resistors of the first interpolation circuit 43 are arranged as described above (see FIG. 12). The connection to the second folder block 44 becomes extremely short, and the parasitic capacitance can be reduced.

  The second folder block 44 is composed of a plurality of second folding amplifiers 51a to 51d, and these are the positive phase signals VO1 to VO12 output from the first folder interpolation circuit 40 in the previous stage and their opposite phases. A folding signal composed of signals XVO1 to XVO12 is input, and a folding signal composed of positive phase signals VA1 to VA4 having different phases and their reverse phase signals XVA1 to XVA4 are generated and output.

  The second folding amplifier 51a includes an amplifier 64a that compares the positive phase signal VO1 with a predetermined voltage, an amplifier 64b that compares the positive phase signal VO5 with a predetermined voltage, and an amplifier 64c that compares the positive phase signal VO9 with a predetermined voltage. And outputs the positive phase signal VA1 by adding the outputs of the amplifier 64a and the amplifier 64c and subtracting the output of the amplifier 64b. The positive-phase signal VA1 output in this way is a folding signal that has been folded eight times (hereinafter also referred to as an “eightfold folding signal”), as shown in FIG.

  The second folding amplifier 51a compares the negative phase signal XVO1 with a predetermined voltage, the amplifier 64a that compares the negative phase signal XVO5 with a predetermined voltage, and the negative phase signal XVO9 with a predetermined voltage. The amplifier 64c is provided, the outputs of the amplifier 64a and the amplifier 64c are added, and the output of the amplifier 64b is subtracted to output the negative phase signal XVA1.

  The second folding amplifier 51b includes an amplifier 65a that compares the positive phase signal VO2 with a predetermined voltage, an amplifier 65b that compares the positive phase signal VO6 with a predetermined voltage, and an amplifier 65c that compares the positive phase signal VO10 with a predetermined voltage. The outputs of the amplifier 65a and the amplifier 65c are added, and the output of the amplifier 65b is subtracted to output the positive phase signal VA2. The positive phase signal VA2 output in this way is shown in FIG.

  Further, the second folding amplifier 51b compares the negative phase signal XVO2 with the predetermined voltage, the amplifier 65a that compares the negative phase signal XVO6 with the predetermined voltage, and the negative phase signal XVO10 with the predetermined voltage. The amplifier 66c is provided, the outputs of the amplifier 65a and the amplifier 66c are added, and the output of the amplifier 66b is subtracted to output the negative phase signal XVA2.

  The second folding amplifier 51c includes an amplifier 66a that compares the positive phase signal VO3 with a predetermined voltage, an amplifier 66b that compares the positive phase signal VO7 with a predetermined voltage, and an amplifier 66c that compares the positive phase signal VO11 with a predetermined voltage. And outputs the positive phase signal VA3 by adding the outputs of the amplifier 66a and the amplifier 66c and subtracting the output of the amplifier 66b. The positive phase signal VA3 output in this way is shown in FIG.

  The second folding amplifier 51c compares the negative phase signal XVO3 with a predetermined voltage, the amplifier 66a that compares the negative phase signal XVO7 with a predetermined voltage, and the negative phase signal XVO11 with a predetermined voltage. The amplifier 66c is provided, the outputs of the amplifier 66a and the amplifier 66c are added, and the output of the amplifier 66b is subtracted to output the negative phase signal XVA3.

  The second folding amplifier 51d includes an amplifier 67a that compares the positive phase signal VO4 with a predetermined voltage, an amplifier 67b that compares the positive phase signal VO8 with a predetermined voltage, and an amplifier 67c that compares the positive phase signal VO12 with a predetermined voltage. And outputs the positive phase signal VA4 by adding the outputs of the amplifier 67a and the amplifier 67c and subtracting the output of the amplifier 67b. The positive phase signal VA4 output in this way is shown in FIG.

  The second folding amplifier 51d compares the amplifier 67a that compares the negative phase signal XVO4 with a predetermined voltage, the amplifier 67b that compares the negative phase signal XVO8 with a predetermined voltage, and compares the negative phase signal XVO12 with a predetermined voltage. The amplifier 67c is provided, the outputs of the amplifier 67a and the amplifier 67c are added, and the output of the amplifier 67b is subtracted to output the negative phase signal XVA4.

  The second interpolation circuit 45 includes a plurality of second resistors Rc1 to Rc16, Rd1 to Rd16.

  As in the case of the first embodiment, the second interpolation circuit 45 divides the plurality of second resistors Rc1 to Rc16, Rd1 to Rd16 into a predetermined number (Namp × Nint / 2), and the predetermined number. A plurality of resistor rows in which the second resistors are connected in series on a straight line are provided, and the second resistors at one end of each resistor row are connected to each other every two rows (each combination of the fifth row), and each resistor A plurality of second resistors are connected in series in a ring by connecting the second resistors at the other end of the column to each of two columns (for each combination of the sixth column) of a combination different from the combination of the first column. is doing.

  That is, a total of 32 resistors, ie, a plurality of second resistors Rc1 to Rc16 and Rd1 to Rd16 connected in series, are divided into 8 pieces to form a plurality of rows, and both ends are folded so that the 8th and 9th pieces are folded back. Further, both ends are connected so that the 16th and 17th folds are folded back, and both ends are connected so that the 24th and 25th folds are folded back. The resistor strings here are R16 and Rc1 to Rc7, Rc8 to Rc15, Rc16 and Rd1 to Rd7, and Rd8 to Rd15.

  Thus, when interpolating between the outputs of the four second folder blocks 44 four times, 4 (Namp) × 4 (Nint) × 2 resistors are connected in series. Is folded every (Namp × Nint / 2), the bent connection between the resistors in the interpolation circuit can be suppressed to a minimum, and the wiring length between the resistors can be shortened. In addition, the coupling capacitance is generated only between the adjacent wirings, and the parasitic capacitance is not increased.

  Further, since it does not become a mirror wiring, even when the A / D conversion circuit is manufactured by a CMOS process, the manufacturing variation does not increase. That is, in the CMOS process in which the impurity introduction into the source / drain regions is oblique ion implantation, if the mirror wiring is used, manufacturing variation increases, but the above configuration does not result in the mirror wiring.

  Further, the plurality of comparators 52a to 52p respectively correspond to the input signal Vip (Vin) to the A / D conversion circuit 1 from the low level reference voltage VRB to the high level reference voltage VRT. From the comparator 52a corresponding to the input signal of the reference voltage VRB to the comparator 52h corresponding to the intermediate input signal between the low-level reference voltage VRB and the high-level reference voltage VRT, they are sequentially arranged in a predetermined direction, and the low-level reference voltage VRB and the high-level reference voltage VRT are From the comparator corresponding to the input signal of the intermediate 52i to the comparator 52p corresponding to the input signal of the high level reference voltage VRT, they are arranged in order in the direction opposite to the predetermined direction.

  As a result, the connection from the second interpolation circuit 45 to the plurality of comparators 52a to 52p can be made without bending.

  Here, each of the plurality of first folding amplifiers 50a to 50c includes a positive-phase folding signal VO1 based on the reference voltage and the analog input signal Vip for each first predetermined voltage interval between the low level reference voltage VRB and the high level reference voltage VRT. , VO4, VO8, and VO12, and negative-phase folding signals XVO1, XVO4, XVO8, and XVO12 based on the negative-phase voltage of the reference voltage and the negative-phase signal Vin of the analog input signal Vip for each first predetermined voltage interval. Then, the first folding amplifier 50a having a low reference voltage at the start position of the first predetermined voltage interval, and the second to second shifts the start position from the first first folding amplifier 50b in order from the first. It is composed of up to third folding amplifiers 50b and 50c. Based on the positive-phase and negative-phase folding signals VO1 / XVO1, VO4 / XVO4, VO8 / XVO8, and VO12 / XVO12 generated by the first folding amplifiers 50a to 50c, the first interpolation circuit 43 performs a positive-phase interpolation signal. Interpolation signals XVO1 to XVO12 having phases opposite to those of VO1 to VO12 are generated.

  The plurality of second folding amplifiers 51a to 51d divides the interpolation signals from VO1 / XVO1 to VO12 / XVO12 into interpolation signal groups at predetermined intervals, and the first interpolation signal groups (VO1 / XVO1, VO5 / XVO5, VO9 / The first second folding amplifier 51a that inputs the XVO9) and outputs the folding signal VA1 / XVA1 and the second interpolated signal group (VO2 / XVO2, VO6 / XVO6, VO10 / XVO10) and the folding signal A second second folding amplifier 51b that outputs VA2 / XVA2 and a third interpolation signal group (VO3 / XVO3, VO7 / XVO7, VO11 / XVO11) are input to output a folding signal VA3 / XVA3. A second second folding amplifier 51c; Comprising a fourth second folding amplifier 51d which outputs a folding signal VA4 / XVA4 enter a second interpolation signal group (VO4 / XVO4, VO8 / XVO8, VO12 / XVO12).

  Then, the first second folding amplifier 51a to the second second folding amplifier 51b are sequentially arranged in a predetermined direction along the resistor string, and then the third second folding amplifier 51c to the fourth second folding amplifier 51d. Are arranged in order in the direction opposite to the predetermined direction.

  As a result, the connection from the plurality of second folding amplifiers 51a to 51d to the second interpolation circuit 45 can be performed without bending.

  As described above, in the first embodiment, the one-stage folder / interpolation configuration has been described. In the second embodiment, the two-stage folder / interpolation configuration has been described, but the number of folding amplifiers Namp, The value of Namp2 and the number of interpolations Nint and Nint2 are not limited to the examples given in the above embodiment.

It is a block diagram which shows the outline of the A / D conversion circuit of 1st Embodiment. It is a figure which shows the example of a combination of the number of folding amplifiers, and the number of interpolations. It is a block diagram which shows a part of A / D conversion circuit of 1st Embodiment. It is a block diagram of the reference voltage generation part of 1st Embodiment. It is a figure which shows the characteristic of the folding signal output from each folding amplifier of 1st Embodiment. It is a block diagram which shows the outline of the A / D conversion circuit of 2nd Embodiment. It is a block diagram which shows a part of A / D conversion circuit of 2nd Embodiment. It is a figure which shows the example of the output signal of the 1st folding amplifier in 2nd Embodiment. It is a figure which shows the example of the output signal of the 1st interpolation circuit in 2nd Embodiment. It is a figure which shows the example of the output signal of the 2nd interpolation circuit in 2nd Embodiment. It is a figure for demonstrating the predominance of the 1st interpolation circuit in 2nd Embodiment. It is a figure for demonstrating the predominance of the 1st interpolation circuit in 2nd Embodiment. It is a figure for demonstrating producing | generating four interpolation signals from two folding signals. It is a figure which shows the prior art example of the interpolation circuit comprised by resistance. It is a figure which shows the relationship between a folding amplifier and an interpolation circuit. It is a figure which shows an example of a structure of the conventional interpolation circuit. It is a figure which shows an example of a structure of the conventional interpolation circuit.

Explanation of symbols

1,20 A / D conversion circuit 2,30 Reference voltage generation unit 3,31 Upper bit conversion unit 4,33 Encoder 5,32 Lower bit conversion unit 6,34 Encoder 10,44 Folder block 11,45 Interpolation circuit 13a ~ 13p, 52a ~ 52p Comparator (Comparator)
14a-14h Folding amplifier 40 Second folder interpolation circuit 41 Folder interpolation circuit 42 Second folder block 43 Second interpolation circuit 46 Comparator blocks 50a-50c First folding amplifiers 51a-51d Second folding amplifier R1-R16, R1′-R16 ′ Resistors Ra1-Ra12, Rb1-Rb12 First resistors Rc1-Rc16, Rd1-Rd16 Second resistors

Claims (4)

A plurality of folding amplifiers that generate and output positive and negative phase folding signals based on different reference voltages and analog input signals, respectively, and a plurality of resistors, and a plurality of in-phase and negative phase outputs from the folding amplifier output. An A / D conversion circuit comprising an interpolation circuit for generating an interpolation signal, a plurality of comparators for inputting the interpolation signal generated by the interpolation circuit, and an encoder circuit for encoding the output from these comparators In
The interpolation circuit is
Dividing the plurality of resistors into predetermined numbers, arranging a plurality of resistor rows in which the predetermined number of resistors are connected in series on a straight line, and connecting the resistors at one end of each resistor row to every two rows A / D is characterized in that the resistors at the other end of each resistor row are connected to each other every two rows in a combination different from the combination of the two rows, and the plurality of resistors are connected in a ring shape. Conversion circuit.   The plurality of comparators are input signals to the A / D conversion circuit and correspond to input signals from a low-level reference voltage to a high-level reference voltage, respectively, and from the comparators corresponding to the input signals of the low-level reference voltage A comparator corresponding to an intermediate input signal between the low reference voltage and the high reference voltage is sequentially arranged in a predetermined direction along the resistor string, and the comparator corresponding to the intermediate input signal is changed to an input signal of the high reference voltage. 2. The A / D conversion circuit according to claim 1, wherein the A / D conversion circuits are arranged in order opposite to the predetermined direction over the corresponding comparators.   Each of the plurality of folding amplifiers generates a positive-phase folding signal based on a reference voltage for each predetermined voltage interval between a lower reference voltage and a higher reference voltage and the analog input signal, and a reference voltage for each predetermined voltage interval. Of the analog input signal and a negative-phase signal of the analog input signal to generate a negative-phase folding signal, and the plurality of folding amplifiers are set to a first reference voltage at a start position of the predetermined voltage interval. A first folding amplifier, and second to Nth folding amplifiers whose start positions are shifted in order from the first folding amplifier to the N / F folding amplifier. Predetermined along the resistor string in order through the second folding amplifier 3. The A / D conversion according to claim 1, wherein the A / D conversion is arranged in the direction opposite to the predetermined direction in order from the N / 2 + 1th folding amplifier to the Nth folding amplifier. circuit. A plurality of first folding amplifiers that generate and output positive and negative phase folding signals based on different reference voltages and analog input signals, respectively, and a plurality of first resistors. A plurality of first interpolation circuits that generate first in-phase and opposite-phase first interpolation signals, and a plurality of first-phase interpolation signals that generate different positive-phase and opposite-phase second folding signals from the plurality of first interpolation signals. A second folding amplifier, a plurality of second resistors, and a plurality of second interpolation circuits for generating a plurality of in-phase and anti-phase second interpolation signals from the output of the second folding amplifier, 2Equipped with a plurality of comparators that input interpolation signals and an encoder circuit that encodes the outputs from these comparators In the A / D converter circuit,
The first interpolation circuit includes:
The plurality of first resistors are divided into a predetermined number, and a plurality of first resistor rows in which the predetermined number of first resistors are connected in series on a straight line are arranged in parallel. The resistors are connected to each other every two columns, and the first resistors at the other end of each first resistor column are connected to each other every two columns in a combination different from the combination of the two columns. The first resistor is connected in series in a serpentine shape,
The second interpolation circuit includes:
The plurality of second resistors are divided into a predetermined number, and a plurality of second resistor rows in which the predetermined number of second resistors are connected in series on a straight line are arranged in parallel. The resistors are connected to each other in every two columns, and the second resistors at the other end of each second resistor column are connected to each other in every two columns in a combination different from the combination of the two columns. The A / D conversion circuit according to claim 2, wherein the second resistor is connected in a ring shape.