JP4845351B2 - Data transfer control device, data processing device, and control method for data transfer control device - Google Patents

Description

The present invention relates to a data transfer control device applicable to image processing , a data processing device, and a control method for the data transfer control device .

  In recent years, with the development of semiconductor processes and the evolution of architecture, the processing speed of processors mounted on various devices has been greatly increased. As a result, some of the processes that have been realized by dedicated hardware without software intervention can be realized by software on the processor.

  Processors have improved performance by increasing their operating frequency. On the other hand, the operating frequency of the memory is less improved than that of the processor, and the difference between the operating frequency of the processor and the memory has become an obstacle to improving the performance of the processor.

  Therefore, the processor has a cache that can be accessed with low latency between the processor and the main memory in order to reduce the latency (delay time from the data transfer request to the actual transfer of data) during memory access. In many cases, a memory is arranged (see, for example, Patent Document 1). The cache memory uses the locality of data access that data of the same address is often accessed repeatedly, and many processes executed by the processor can be accelerated by the cache memory.

  Even in image processing, processing has become complicated and diversified in order to achieve high image quality, and there has been a demand for processing more flexibly by a processor than by simple and fixed processing by hardware. .

  However, in image processing, the data capacity of the image to be processed is large, and the processor often accesses the main memory in order from the end of the address range where the data is arranged. The locality of is very low. Therefore, the effect of speeding up the processing by the cache memory is low. Instead, if the access pattern to the main memory has high regularity and the contents of image processing are known in advance, it is relatively easy to predict processor access.

Therefore, in general, not only a cache memory but also a local memory that can be freely read / written by the processor and accessible with a low latency is arranged between the processor and the main memory. Process. This local memory is connected to a DMA (Direct Memory Access) control device, and in parallel with the processing of the processor, the data required for the next processing is transferred from the main memory to the local memory, and the processing result Are written back from the local memory to the main memory. As a result, the access latency to the main memory can be concealed, and the processing speed is increased.
JP-A-6-12328

  However, if it is intended to increase the processing speed by the above-described method, it is necessary to use a faster processor. However, depending on the product on which the processor is mounted, there is a demand for low power consumption, low heat generation, low cost, etc. Exists. In such a case, it may be necessary to reduce the processing capacity of the processor to some extent. Therefore, for example, when a processor used for image processing does not satisfy the required performance, hardware having a dedicated function for assisting a specific image processing must be added.

  However, by performing image processing with a processor, it is possible to implement an image processing algorithm by software, and the flexibility of realizing multiple image processing algorithms despite using the same hardware. Although it should be possible to obtain, there is a problem that flexibility is reduced by adding hardware having a dedicated function.

  Further, since the image processing on the processor side is performed on a small-capacity local memory, the image data to be processed is divided into several parts, the data is transferred between the main memory and the local memory, and the processing is divided into several times. There is a need to do. This data transfer is controlled by the DMA controller, but the DMA controller itself is DMA-dedicated hardware and can only perform a predetermined data transfer procedure. In other words, if a new image processing content is to be realized later and the data transfer procedure not supported by the DMA controller must be used, the new image processing content cannot be realized later. Or there is a problem that the processing speed is significantly reduced.

An object of the present invention is to enable high-speed image processing and flexibility in processing contents, and in particular, it is possible to efficiently process image data with image processing means according to the result of the transfer device . A data transfer control device , a data processing device, and a control method for the data transfer control device are provided.

To achieve the above object, a data transfer controller according to the present invention, holding means for holding instruction string which is output from the image processing unit, according to the interpretation of the instruction sequence to retain the holding means, the image processing In parallel with the image processing performed by the means, a value for determining the content of the image processing of the image processing means is acquired from a part of the image processing target image data stored in the first storage means, and the image Transfer means for transferring a part of the data and the value to the second storage means is provided.

According to the present invention, without additional hardware having a dedicated function like a traditional (while using the same hardware configuration), the data transfer control device, the contents of the plurality of image processing in the image processing apparatus Data transfer suitable for each of them and processing for assisting image processing on the image processing apparatus side can be performed, and it is possible to realize high-speed image processing and flexibility in processing contents. In particular, by partially transferring the image data and extracting a value that determines the image processing to be applied to a part of the image data, the image processing means efficiently outputs the image data according to the result of the transfer device. Can be processed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the data processing apparatus according to the first embodiment of the present invention.

  1, the data processing apparatus includes a processor 1, a DMA processor 2, a local memory 3, a local memory 4, a memory controller 5, a main memory 6, a DMA processor interface 7, and an address bus / data bus 8.

  The processor 1 performs image processing on image data on a local memory connected to the address / data bus 8. The DMA processor 2 can change the processing content according to the content of the image processing performed by the processor 1, reads the instruction sequence held in the built-in instruction memory, interprets and executes the instruction sequence. The DMA processor 2 also performs data processing between the local memories 3 and 4 connected to the address / data bus 8 and the main memory 6 via the memory controller 5 in parallel with the image processing performed by the processor. Perform the transfer. The instruction memory can store an instruction sequence of 128 words with 32 bits as one word. Addresses 0 to 127 are assigned to individual words, and instruction sequences are basically executed in order from address 0.

  Further, the DMA processor 2 sorts the image data to be processed into a format convenient for the processing on the processor side according to the contents of the image processing performed by the processor 1, and the main memory to be processed by the processor 1 A part of the upper image data is transferred to the local memory 3 (or 4), and a part of the image data on the main memory to be processed by the processor 1 is transferred to the local memory 3 while performing processing to assist the processing on the processor side. Transfer to (or 4).

  Further, the DMA processor 2 converts image data existing in a format convenient for image processing on the processor side into a format convenient for subsequent image processing according to the contents of image processing performed by the processor 1. The image data on the local memory that the processor 1 has completed the image processing is transferred to the main memory 6 and the image data on the local memory that the processor 1 has completed the image processing while performing the processing to assist the image processing on the processor side. Is transferred to the main memory 6.

  The DMA processor interface 7 is connected to the DMA processor 2 and includes a plurality of registers (FIG. 3) capable of reading and writing from the processor 1 via the address / data bus 8. By rewriting the register of the DMA processor interface 7 by the processor 1, the reset state of the DMA processor 2 and the instruction memory in the DMA processor 2 can be rewritten.

  The local memories 3 and 4 are composed of SRAM (Static RAM) that can be accessed with low latency. The memory controller 5 performs control when the main memory 6 is accessed from the processor 1 and the DMA processor 2 via the address / data bus 8. The main memory 6 is composed of DRAM (Dynamic RAM) that requires a lot of latency for access but can be increased in capacity. The processor 1, the DMA processor 2, the local memories 3 and 4, and the memory controller 5 are crossbar-connected. If the access request destinations of the processor 1 and the DMA processor 2 are not the same, the local memories 3 and 4 and the main memory 6 can be accessed in parallel in time.

  FIG. 2 is a diagram showing an address map 21 of the main memory 6, the local memories 3 and 4, and the registers of the DMA processor interface 7 effective in the processor 1 and the DMA processor 2.

  In FIG. 2, the main memory 6 has a range of 0x00000000 to 0x03ffffff and a capacity of 64 Mbytes. The local memory 3 has a range of 0xc0000000 to 0xc0001fff and a capacity of 8 Kbytes. The local memory 4 has a range of 0xc0002000 to 0xc0003fff and a capacity of 8 Kbytes. The registers of the DMA processor interface 7 are in the range of 0xe0000000 to 0xefffffff. The range from 0xf0000000 to 0xffffffff is a ROM area for booting the processor 1 and storing programs.

  FIG. 3 is a diagram showing a register map 31 of the DMA processor interface 7 accessible from the processor 1.

  In FIG. 3, the address 0xe0000000 is the reset register 32. When the processor 1 writes 1 to the reset register 32, the DMA processor 2 enters the reset state, and when the processor 1 writes 0 to the reset register 32, the DMA processor 2 enters the reset release state. The initial value of the reset register 32 is 1.

  The address 0xe0000004 is a trigger emit register 33. When the processor 1 writes 1 to the trigger emit register 33, the DMA processor 2 can generate a trigger event. The DMA processor 2 can detect the trigger event by a dedicated instruction.

  The address 0xe0000008 is the trigger status register 34. When the processor 1 reads the trigger status register 34 after the DMA processor 2 executes the trigger emit instruction, 1 is obtained as a value. If the DMA processor 2 has not previously executed the trigger emit instruction and the processor 1 reads the trigger status register 34, 0 is obtained as a value. When the processor 1 writes 0 in the trigger status register 34, the value held in the trigger status register 34 is reset, and 0 can be read. The initial value of the trigger status register 34 is 0.

  The address 0xe000000c is the mode register 35. When the processor 1 writes 1 to the mode register 35, the DMA processor 2 enters a stop state in which the instruction memory can be rewritten. When the processor 1 writes 0 to the mode register 35, the DMA processor 2 enters an instruction execution state. The initial value of the mode register 35 is 0.

  The 0xe0000010 address is the IMEM Address register 36. When the DMA processor 2 is in a stop state where the instruction memory can be rewritten, the processor 1 designates the instruction memory by rewriting the address to be rewritten to the IMEM Address register 36.

  The 0xe0000014 address is the IMEM Data register 37. When the DMA processor 2 is in a stop state where the instruction memory can be rewritten, the processor 1 writes a value in the IMEM Data register 37 to write it as an instruction of the DMA processor 2 at the address specified by the IMEM Address register 36 of the instruction memory. Can do.

  Next, an operation example in image processing of the data processing apparatus according to the present embodiment having the above-described configuration will be described with reference to FIGS.

  FIG. 4 is a diagram showing image data to be subjected to image processing.

  In FIG. 4, the image data is composed of 2048 pixels wide and 1536 pixels vertically. One pixel exists in one byte of 256 gradations. The processor 1 divides the image data into 1-line 2 Kbytes units of 2048 pixels in width, and performs image processing for conversion into a binary image by an error diffusion method.

  In the binarization by the error diffusion method, when the value of the pixel of interest is 0 to 127, 0 is output as the result, and when it is 128 to 255, 1 is output as the result. At the same time, if 0 is output as the result, the pixel value is set as an error value, and if 1 is output as the result, a value obtained by subtracting 127 from the pixel value is set as an error value and added to the pixel value to be processed later. If the coordinates of the target pixel are (x, y), the distribution of the addition is 1/2 of the error value to the pixel of coordinates (x + 1, y) and the pixel of coordinates (x-1, y + 1) The error value is 1/4, the pixel of coordinates (x, y + 1) is the remainder of dividing the error value of 1/8 and the error value by 8, and the pixel of coordinates (x + 1, y + 1) is the error value. 1/8.

  Here, in the case where image data to be subjected to image processing includes a single horizontal line that is white, it is possible to simplify the binarization processing by the error diffusion method. . For example, when image data in which characters are displayed horizontally on a white background is an image processing target, the upper and lower margins and line spacing of the characters are white lines.

  Therefore, when the DMA processor 2 transfers one horizontal line as a processing unit from the main memory 6 to the local memory 3 (or 4), the DMA processor 2 determines the minimum of the transferred image data in units of 1 byte. Find the value at the same time. When the minimum value calculated by the DMA processor 2 is larger than the predetermined value, the processor 1 sets all the output results to 1 without reading the image data from the local memory side, and sets the error value to the next line to 0. Simplify processing. This leads to faster image processing. The image processing related to the minimum value in the processor 1 will be described in detail in the following operation description.

  FIG. 5 shows a DMA processor program.

  In FIG. 5, the DMA processor program runs on the DMA processor 2 and transfers data between the main memory 6 and the local memory 3 (or 4) and calculates the minimum value of each data. The process shown in the flowchart of FIG. 7 is executed. The ar0, ar1, ar7, lp0, ofst0, gpr0, and gpr1 registers in FIG. 5 are registers in the DMA processor 2.

  First, in order to write a DMA processor program to the instruction memory of the DMA processor 2, the processor 1 accesses the register (FIG. 3) of the DMA processor interface 7 and performs the following processing.

  (1) Write 1 to the address 0xe000000c, which is the mode register of the DMA processor interface 7, so that the DMA processor 2 can be rewritten to the instruction memory.

  (2) Write 0 to address 0xe0000000, which is a reset register, and release the reset of the DMA processor 2.

  (3) The address in the instruction memory corresponding to the instruction of FIG. 5 is written to the address 0xe0000010 which is the IMEM Address register.

  (4) Write the operation code of FIG. 5 specified in (3) to address 0xe0000014 which is the IMEM Data register.

  (5) Repeat (3) to (4) for the number of instructions in FIG.

  (6) Write 0 to address 0xe000000c, which is the mode register, to place the DMA processor 2 in the instruction execution state.

  Through the above processing, the DMA processor 2 executes instructions in order from address 0 of the instruction memory, and obtains the transfer of image data and the minimum value of each image data.

  FIG. 6 is a diagram showing a detailed address map on the local memory side.

  In FIG. 6, the address map shows the data arrangement when performing image processing on the nth line of the image data. The processor 1 first performs the following process to start the data transfer operation of the DMA processor 2 before starting the image processing of the nth line.

  Processor 1 writes 0xc0000900 to address 0xc0000000, which is the reset register of DMA processor interface 7, writes 0x02000400 to address 0xc0000004, which is the trigger emit register, and 0x00000100 to address 0xc0000008, which is the trigger status register. Is designated from the local memory 3 (or 4) to the main memory 6. Furthermore, the processor 1 writes 0x01002000 at address 0xc0000010, 0xc0000100 at address 0xc0000014, and 0x00000800 at address 0xc0000018, and transfers the next image processing target image data from the main memory 6 to the local memory 3 (or 4). Specify the address range to be used.

  Next, the processor 1 reads the minimum value calculated by the DMA processor 2 from address 0xc0000020 simultaneously with the data transfer of the nth line. Then, the processor 1 transmits a trigger event to the DMA processor 2 by writing 1 to the address 0xe0000004, and the execution of the instruction temporarily suspended by the “WAIT” instruction at the address 2 of the instruction memory of the DMA processor 2 is performed 3 Resume from the street address.

  FIG. 7 is a flowchart showing the processing of the DMA processor 2.

  In FIG. 7, the DMA processor 2 is an address for transferring the image data of the (n−1) th line for which image processing has been completed from the local memory 3 (or 4) to the main memory 6 at addresses 3 to 5 of the instruction memory. The range and the transfer size are obtained, and data transfer is performed by repeating addresses 8 to 9 for the transfer size (step S1).

  When the processing is completed, the DMA processor 2 transfers the image data to be processed in the (n + 1) th line from the main memory 6 to the local memory 3 (or 4) at addresses 0xa to 0xc in the instruction memory. Data is transferred and the minimum value is calculated by obtaining the range and repeating addresses 0x10 to 0x12 for the transfer size (step S2).

  When the processing is completed, the DMA processor 2 writes the minimum value calculated at the address 0x13 in the instruction memory to the address 0xc0000020 in the local memory 3 (or 4), and notifies the processor 1 of a trigger event as a signal of the completion of the processing. Then, the program jumps to address 2 at address 0x15 in the instruction memory and waits for the next transfer instruction (step S3).

  While the DMA processor 2 is executing the above processing, the processor 1 first checks the minimum value of the nth line image data calculated by the DMA processor 2. When the minimum value is 0xf0 or more, the processor 1 determines that all the n lines are white lines, and writes the determination results at addresses 0xc0002900 to 0xc0002a00 in the local memory 3 (or 4). When the minimum value is smaller than 0xf0, the processor 1 reads the image data of the nth line from 0xc0002100 to 0xc00028ff in the local memory 3 (or 4), performs image processing by the error diffusion method, and performs local processing on the local memory 3 ( Alternatively, the image processing result is written in addresses 0xc0002900 to 0xc0002a00 in 4).

  The processor 1 reads the address 0xe0000008 that is the trigger status register of the DMA processor interface 7 after the above image processing is completed. If 1 can be read, the processor 1 waits until 1 can be read. If 1 is read, the processor 1 writes 0 at address 0xe0000008 to clear the trigger event and completes the processing of the nth line.

  The processor 1 performs the above-described processing for the vertical 1536 lines of the image data, and finally completes the image processing of the image data including the horizontal 2048 pixels and the vertical 1536 pixels.

  As described above, according to the present embodiment, the processor 1 selects an instruction according to the type of target image processing from among a plurality of instruction sequences for the DMA processor, and the instruction of the DMA processor 2. Write to the memory and start image processing. The DMA processor 2 transfers, in parallel with the image processing of the processor 1 in time, a group of image data to be processed from the main memory 6 to the local memory 3 (or 4). The above image processed image data is transferred to the main memory 6. The processor 1 performs image processing on the image data on the local memory while using the auxiliary processing performed by the DMA processor 2.

  As a result, the DMA processor 2 can perform DMA transfer suitable for each of a plurality of image processing contents on the processor side without adding hardware having a dedicated function as in the past (using the same hardware configuration). Thus, it is possible to perform processing to assist the image processing on the processor side, and it is possible to realize high-speed image processing and flexibility in processing contents.

[Second Embodiment]
The second embodiment of the present invention is different from the first embodiment described above in the image data to be processed and the operation of the DMA processor 2 in the following points. The other elements of the present embodiment are the same as the corresponding ones of the above-described first embodiment (FIGS. 1 to 3), and thus description thereof is omitted.

  Next, an operation example in image processing of the data processing apparatus according to the present embodiment having the above-described configuration will be described with reference to FIGS.

  FIG. 8 is a diagram showing image data to be subjected to image processing.

  In FIG. 8, the image data is composed of 2048 pixels wide and 1536 pixels vertically. One pixel is composed of 3 bytes of 256 tones for each color of RGB, and exists on the main memory 6 in the order of RGBRGBRGB. The processor 1 performs image processing that divides image data into 2048-pixel horizontal lines in units of 6 Kbytes and converts them into a binary image by an error diffusion method.

  9 and 10 are diagrams showing a DMA processor program.

  9 and 10, the DMA processor program runs on the DMA processor 2 and executes the processing shown in the flowchart of FIG. The DMA processor program is divided into FIGS. 9 and 10 for the sake of illustration.

  FIG. 11 is a flowchart showing the processing of the DMA processor 2.

  In FIG. 11, when the image processing target is the image data shown in FIG. 8, the DMA processor 2 performs data transfer between the main memory and the local memory in order to assist the image processing of the processor 1 (step S11). . At the same time, the DMA processor 2 calculates the minimum value for each color data of RGB (step S12), and creates a 1-byte space every 3 bytes for one pixel in units of 3 bytes. Conversion to a byte unit format (step S13).

  As in the first embodiment, the processor 1 writes the DMA processor program into the instruction memory of the DMA processor 2 using the DMA processor interface 7 so that the DMA processor 2 can start the above-described operation. .

  As described above, according to the present embodiment, similarly to the first embodiment, it is possible to add hardware having a dedicated function as in the past (using the same hardware configuration). The DMA processor 2 can perform DMA transfer suitable for each of the image processing contents on the processor side and processing to assist the image processing on the processor side, realizing high-speed image processing and flexibility in processing contents It becomes possible to do.

[Other embodiments]
In the first and second embodiments, the single data processing apparatus having the configuration shown in FIG. 1 has been described. However, the present invention is not limited to application only to the single data processing apparatus. The present invention can be applied to various image forming apparatuses (printers, copiers, multifunction machines, facsimiles, etc.) equipped with the apparatus.

  In the first and second embodiments, the configuration in which the DMA processor interface 7 is connected to the DMA processor 2 has been described as an example. However, the present invention is not limited to this, and the DMA processor 2 includes the DMA processor. It is good also as a structure which incorporates the function of an interface.

  The present invention supplies a software program (flowcharts in FIGS. 7 and 11) for realizing the functions of the above-described embodiments to a computer or CPU, and the computer or CPU reads and executes the supplied program. Can be achieved.

  In this case, the program is directly supplied from a storage medium storing the program, or downloaded from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like. Supplied.

  The form of the program may be in the form of object code, program code executed by an interpreter, script data supplied to an OS (operating system), and the like.

  The present invention also supplies a computer or CPU with a storage medium storing a software program that implements the functions of the above-described embodiments, and the computer or CPU reads and executes the program stored in the storage medium. Can also be achieved.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for storing the program code, for example, ROM, RAM, NV-RAM, floppy (registered trademark) disk, hard disk, optical disk (registered trademark), magneto-optical disk, CD-ROM, MO, CD-R, CD -RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW, magnetic tape, nonvolatile memory card, etc.

  The function of the above-described embodiment is not only by executing the program code read from the computer, but the OS or the like running on the computer performs part or all of the actual processing based on the instruction of the program code. Can also be realized.

It is a block diagram which shows the structure of the data processor which concerns on the 1st Embodiment of this invention. It is a figure which shows the address map of the register | resistor of the main memory, local memory, and DMA processor interface effective in a processor and a DMA processor. It is a figure which shows the register map of the DMA processor interface accessible from a processor. It is a figure which shows the image data used as the object of an image process. It is a figure which shows the program for DMA processors. It is a figure which shows the detailed address map by the side of a local memory. It is a flowchart which shows the process of a DMA processor. It is a figure which shows the image data used as the object of the image process which concerns on the 2nd Embodiment of this invention. It is a figure which shows the program for DMA processors. It is a continuation of FIG. It is a flowchart which shows the process of a DMA processor.

Explanation of symbols

1 processor <br/> 2 DMA processor <br/> 3, 4 local memory 6 main memory 7 DMA processor interface

Claims (13)

Holding means for holding instruction string which is output from the image processing unit,
Accordance interpretation of the instruction sequence to retain the holding means, said image processing image processing temporally parallel to means performs the said image processing means from a portion of the image data of the stored image processing target in the first storage means image processing Gets a value that determines the contents of the data transfer control device, characterized in that it comprises a transfer means for transferring said value as part of the image data in the second storage means.   The transfer means stores image data stored in the second storage means after the image processing is performed by the image processing means in parallel with the image processing performed by the image processing means in the first storage. The data transfer control device according to claim 1, wherein the data transfer control device transfers the data to a means.   3. The data transfer control device according to claim 1, wherein the second storage unit operates with a latency lower than that of the first storage unit.   The second storage means has a smaller capacity than the first storage means;
  The transfer means transfers the image processing target image data held by the first storage means to the second storage means while dividing the image data into predetermined units,
  4. The transfer device according to claim 1, wherein the transfer unit acquires a value that determines the content of the image processing of the image processing unit for each predetermined unit and transfers the acquired value to the second storage unit. 5. The data transfer control device according to 1.   5. The image processing unit according to claim 1, wherein the image processing unit performs image processing on the image data transferred to the second storage unit by the transfer unit and writes the image data back to the second storage unit. 2. A data transfer control device according to item 1.   The data transfer control device according to claim 1, wherein the image processing unit can rewrite a command sequence held by the holding unit.   The transfer means transfers the predetermined unit of image data processed by the processing means from the second storage means to the first storage means based on the instruction sequence indicated by the holding means, and then the first storage means. 7. The data transfer control device according to claim 1, wherein the divided image data to be processed held by the storage unit is transferred to the second storage unit. 8.   The data transfer control device according to claim 1, wherein the transfer unit divides the image data into units of lines and acquires values used by the image processing unit for each line. . Comprising the data transfer control device as defined in any one of 請 Motomeko 1 to 8, said image processing means, said first memory means and said second storage means,
The image processing unit executes image processing determined according to the value acquired by the transfer unit, on a part of the image data transferred by the transfer unit to the second storage unit. Data processing device. Incorporates the image processing unit accessible from registers, and further comprising an interface means for enabling rewritten contents held in said holding means of said data transfer control device by rewriting the register according to said image processing means The data processing apparatus according to claim 9 .   The value that determines the content of the image processing of the image processing means acquired by the transfer means is a value that indicates whether or not the divided image data is white.
  11. The data processing apparatus according to claim 9, wherein the image processing means simplifies the binarization processing when the image data obtained by dividing the value indicates that the color is white.   The image processing unit executes binarization processing by an error diffusion method, and determines that the divided image data is a single white color based on the value acquired from the transfer unit. The data processing apparatus according to claim 11, wherein an error value for image data to be processed next is set to zero. A control method for a data transfer control device having holding means for holding a command sequence output from an image processing means ,
Accordance interpretation of the instruction sequence to retain the holding means, said image processing image processing temporally parallel to means performs, the image data of the first image processing which is stored in the storage means is divided, the divided images Gets a value that determines the contents of the image processing of the image processing unit from the data, wherein the to that control method further comprising a transfer step of transferring the said value and the divided image data in the second storage means .

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