JP4848385B2 - Symbol allocation and symbol assembly circuit in high-speed serial data communication - Google Patents

Description

  The present invention relates to a symbol allocation and symbol assembly circuit in high-speed serial data communication data communication that has a plurality of lanes, sets symbol allocation for each lane, and sets symbol assembly from each lane.

  “PCI Express” is a serial transfer interface for personal computers that was developed by the PCI-SIG in 2002 and replaces the PCI bus. The lane which is the minimum configuration transmission line used in “PCI Express” is capable of full duplex communication of 2.5 Gbps in one direction and 5.0 Gbps in both directions. Note that 10 bits plus 2 bits such as a clock signal are used to send 8 bits of data, so the effective data transfer rate is 2.0 Gbps (250 MB / s) in one direction and 4.0 Gbps (500 MB / s) in both directions. .

  The actual PCI Express port is often configured by bundling multiple lanes. The PCI Express port consisting of 1 lane is called "PCI Express x1", the 2 lane port is called "x2", etc. To do. Products such as x2, x4, x8, x12, x16, x32 are now available.

  In such a PCI Express standard, data to be transmitted is transmitted and received in units of packets. By the way, when the communication link has a plurality of lanes, the packet data is distributed to the lanes and transmitted / received in order for each symbol constituting the packet. This is called “byte stripe”.

  FIG. 13 is a diagram schematically showing how packet data is byte-stripe. In the port shown in FIG. 13, four logical lanes (lane 0, lane 1, lane 2, lane 3) are set.

  First, in the byte stripe shown in FIG. 13, symbols are assigned in order from logical lane numbers 0 to 3. However, in the conventional technology using PCI Express, only two types of ascending order or descending order are allowed for allocation of physical lane numbers to logical lane numbers, as shown in FIG. That is, there are only two types of symbol allocation for physical lanes. Then, if the transmission path is monitored using a protocol analyzer that can be easily obtained in the market, there is a possibility that the communication contents can be easily analyzed.

  This may lead to decryption of communication contents by a third party. Even when PCI Express is used as a local interface in a device, it can be said that there is a risk of leakage of internal information unique to the device.

In addition, the following patent documents 1 and 2 and nonpatent literature 1 are mentioned as a prior art considered to be related to this application.
JP 2005-182485 A JP 2005-332372 A PCI-SIG “PCI Express Base Specification Revision 2.0”, PCI-SIG December 2006

  An object of the present invention is to prevent information leakage from the transmission path as described above in a serial transmission system using PCI Express.

The present invention has been made to achieve the above object. According to the first aspect of the present invention, there is provided a semiconductor integrated circuit.
In a semiconductor integrated circuit including a data transmission / reception unit in the physical layer of high-speed serial communication,
The data transmission / reception unit includes a transmission unit and a reception unit,
The transmission unit includes a symbol distribution circuit, an 8B10B conversion circuit, a parallel serial (P2S) conversion circuit, and a first symbol counter.
The receiver is composed of a symbol assembly circuit, a 10B8B conversion circuit, a serial parallel (S2P) conversion circuit, and a symbol counter.
In addition, a symbol allocation reference table is included in the storage unit of the common part of the transmission unit and the reception unit,
The symbol distribution reference table is set by negotiation with the communication partner,
The symbol distribution circuit of the transmission unit refers to the symbol distribution reference table, determines a symbol distribution lane based on the count value from the first symbol counter, and the symbol assembly circuit of the reception unit performs symbol distribution The data from the lane is symbol-assembled based on the counter value from the second symbol counter with reference to the reference table.

A semiconductor integrated circuit according to claim 2 of the present invention is
Instead of the above symbol distribution reference table,
A mode selection register for holding data indicating which of a plurality of preset symbol distribution rules to select;
The symbol distribution circuit of the transmission unit refers to a mode selection register, determines a symbol distribution lane based on data held in the mode selection register and a count value from the first symbol counter, and the reception unit The symbol assembling circuit refers to a mode selection register and symbol-assembles data from the lane based on data held in the mode selection register and a counter value from the second symbol counter. A semiconductor integrated circuit according to claim 1.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
2. The semiconductor integrated circuit according to claim 1, wherein when a first symbol of a packet and a final symbol of a packet are included in one time cycle, a symbol distribution rule is temporarily fixed in a forward direction with respect to the lane. It is a circuit.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit according to the present invention.
In the storage unit of the transmission unit and the storage unit of the reception unit, a transmission symbol allocation reference table and a reception symbol allocation reference table are separately provided,
The symbol distribution circuit of the transmission unit refers to the transmission symbol distribution reference table, determines a symbol distribution lane based on the count value from the first symbol counter, and the symbol assembly circuit of the reception unit includes: 2. The semiconductor integrated circuit according to claim 1, wherein data from the lane is symbol-assembled based on the counter value from the second symbol counter with reference to the reception symbol allocation reference table.

A semiconductor integrated circuit according to claim 5 of the present invention is
Information related to the symbol distribution reference table is allocated in advance in the configuration register area,
The above negotiation is
2. The semiconductor integrated circuit according to claim 1, wherein after the link is established as PCI express, the information relating to the symbol allocation reference table is achieved by writing and reading by a Configuration Write / Read transaction. .

A semiconductor integrated circuit according to claim 6 of the present invention is
6. The semiconductor integrated circuit according to claim 5, wherein the symbol distribution reference table is set only for a lane in which a link is established.

The serial transmission system according to claim 7 according to the present invention,
A serial transmission system comprising at least the semiconductor integrated circuit according to any one of claims 1 to 6.

  By using the present invention, in data transmission / reception in the physical layer of high-speed serial communication, it is possible to set symbol allocation for a plurality of lanes and symbol assembly from the plurality of lanes after negotiation with a communication partner. Therefore, even if an external communication line using the present invention is monitored using a protocol analyzer or the like that is easily obtained in the market, analysis of communication contents becomes impossible and security is improved.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram of a data transmission / reception unit in the physical layer of high-speed serial communication in the semiconductor integrated circuit according to the first embodiment of the present invention.

  The data transmission / reception unit according to the first embodiment includes a transmission unit 2 and a reception unit 4. The transmitter 2 includes a symbol distribution circuit 6, an 8B10B conversion circuit 16, a parallel-serial (P2S) conversion circuit 20, and a first symbol counter 10. The receiving unit 4 includes a symbol assembly circuit 8, a 10B8B conversion circuit 18, a serial / parallel (S2P) conversion circuit 22, and a second symbol counter 12. Further, the symbol allocation reference table 14 is stored in the storage unit common to the transmission unit 2 and the reception unit 4.

  First, transmission data is input to the transmission unit 2 in symbol units (one or more). The first symbol counter 10 counts the number of symbols of the input data and outputs the count value to the symbol distribution circuit 6. The first symbol counter 10 is reset when the head of the packet comes or when the counter value reaches the reference table size. For example, in the symbol distribution reference table shown in FIG. 2, the reference table size is “16”.

  Note that the second symbol counter 12 included in the receiving unit 4 described later also performs the same operation as the first symbol counter 10.

  The symbol distribution circuit 6 of the transmitter 2 refers to the symbol distribution reference table 14 and determines the symbol distribution lane (logical lane) based on the count value from the first symbol counter 10. In the example of the symbol allocation reference table shown in FIG. 2, the first symbol (that is, the symbol whose counter value of the first symbol counter is “0”) is the lane 3 and the next symbol (that is, the first symbol counter). The symbol whose counter value is “1”) is distributed to lane 1.

  The table size and the reference value of the symbol allocation reference table as shown in FIG. 2 are determined by negotiation with the communication partner, and are set from an upper layer (such as a CPU) after the determination. Alternatively, it can be set by using “Configuration Write transaction” from the communication partner, which is a function provided in the PCI Express standard.

  The data distributed for each lane by the symbol distribution circuit 6 of the transmission unit 2 is converted into 10-bit data by the 8B10B conversion circuit 16 and input to the transmission differential signal driver 24 as serial data by the parallel-serial conversion circuit 20. It is transmitted as a motion signal.

  On the other hand, in the receiving unit 4, the differential signal is received by the reception differential signal receiver 26, converted to 10-bit data by the serial / parallel conversion circuit 22, and converted to 8-bit data by the 10B8B conversion circuit 18, and the symbol assembly circuit. 8 is input.

  Note that the 8B10B conversion circuit and the 10B8B conversion circuit are described in Non-Patent Document 1 and will not be described in detail in this specification.

  The symbol assembling circuit 8 of the receiving unit 4 refers to the symbol allocation reference table 14 and assembles data from the logical lane based on the counter value from the second symbol counter 12. FIG. 3 is a diagram schematically showing how data is assembled from logical lanes assembled by the symbol assembly circuit 8. As clearly shown in FIG. 1, the symbol allocation rule reference table 14 used from the receiving unit 4 is the same as that used from the transmitting unit 2.

  Since the symbol allocation reference table 14 can be set by negotiation with the communication partner, various symbol allocation / symbol assembly becomes possible. In the description relating to the data transmission / reception unit of the first embodiment, the case where the number of lanes is “4” is shown, but the present invention can be applied even if the number of lanes is 1, 2, 8, 16 or 32, etc. Is possible.

  Also, for example, in the reference table shown in FIG. 2 (1), the table size in the time cycle direction (vertical direction) is “4” in the logical lane, and loops once every four cycles from the beginning of the reference table. As will be referred to, the table size in the time cycle direction can also be set by negotiation.

[Second Embodiment]
FIG. 4 is a block diagram of a data transmission / reception unit in the physical layer of high-speed serial communication in the semiconductor integrated circuit according to the second embodiment of the present invention. The data transmission / reception unit of the semiconductor integrated circuit according to the second embodiment is substantially the same as the data transmission / reception unit of the semiconductor integrated circuit according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences between the two will be mainly described.

  The data transmission / reception unit according to the second embodiment shown in FIG. 4 is a symbol allocation reference table included in the data transmission / reception unit according to the first embodiment in the storage unit of the common part of the transmission unit 2 ′ and the reception unit 4 ′. Instead, a mode selection register 30 is provided.

The mode selection register 30 is a register that holds data indicating which one of a plurality of preset symbol distribution rules is selected. The “several symbol distribution rules set in advance” here are, for example, as shown in FIG.
(A) Forward rule as shown in FIG. 13 (FIG. 5 (1)),
(A) Reverse rule that is the reverse of the forward rule (FIG. 5 (2)),
(C) A forward / reverse alternating rule (FIG. 5 (3)) in which a forward direction rule and a reverse direction rule appear alternately,
(D) Rotation rule in which lanes are shifted one by one for each time cycle while using forward rules as a rule (Fig. 5 (4))
Etc. The data held in the mode selection register 30 is data indicating which one of (A) to (D) is selected, for example.

  The symbol distribution circuit 6 ′ of the transmission unit 2 ′ refers to the mode selection register 30, and based on the data held in the mode selection register 30 and the count value from the first symbol counter 10, the symbol distribution lane ( Logical lane). The symbol assembling circuit 8 ′ of the receiving unit 4 ′ also refers to the mode selection register 30, and based on the data held in the mode selection register 30 and the counter value from the second symbol counter 12, outputs from the logical lane. Assemble data with symbols.

  Compared with the data transmitter / receiver according to the first embodiment, the data transmitter / receiver according to the second embodiment has a circuit scale substantially reduced by the symbol allocation reference table.

[Third Embodiment]
The data transmission / reception unit in the physical layer of the high-speed serial communication in the semiconductor integrated circuit according to the third embodiment of the present invention has basically the same configuration as the data transmission / reception unit according to the first embodiment. However, it differs in the following points.

  In the data transmission / reception unit according to the third embodiment, when the first symbol of the packet and the last symbol of the packet are included in one time cycle, the symbol distribution rule is temporarily fixed in the forward direction with respect to the lane ( (Refer to Drawing 6 (1) (2)).

  By doing so, the size of the symbol allocation reference table 14 can be reduced. Further, since the first symbol of the packet is allocated to (logical) lane 0 and the final symbol of the packet is allocated to (logical) lane 3 (however, when the number of lanes is 4) (see FIG. 7), the packet on the external transmission path Unit recognition is possible. Even at this time, it is difficult to analyze the communication content by an external monitor. However, most of the packet data is rearranged according to the symbol allocation reference table 14.

[Fourth Embodiment]
FIG. 8 is a block diagram of a data transmission / reception unit in the physical layer of high-speed serial communication in a semiconductor integrated circuit according to the fourth embodiment of the present invention. The data transmitter / receiver of the semiconductor integrated circuit according to the fourth embodiment is substantially the same as the data transmitter / receiver of the semiconductor integrated circuit according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals, description thereof will be omitted, and differences between the two will be mainly described.

  In the data transmitter / receiver according to the fourth embodiment, a symbol allocation reference table is provided separately for transmission and reception in the storage unit of the transmission unit 2 ″ and the storage unit of the reception unit 4 ″ (symbol transmission reference table for transmission). 32, symbol allocation reference table for reception 34).

  That is, the symbol distribution circuit 6 ″ of the transmission unit 2 ″ refers to the transmission symbol distribution reference table 32 and determines the symbol distribution lane (logical lane) based on the count value from the first symbol counter 10. . The symbol assembly circuit 8 ″ of the reception unit 4 ″ refers to the reception symbol allocation reference table 34 and assembles data from the logical lane based on the counter value from the second symbol counter 12.

  Thus, the security of communication is improved by making the symbol allocation rule and the symbol assembly rule different between the transmission unit 2 ″ and the reception unit 4 ″ of one data transmission / reception unit.

[Negotiation Flowchart (1)]
FIG. 9 is a flowchart of negotiation used in the data transmission / reception unit of the physical layer for high-speed serial communication in the semiconductor integrated circuit according to the present invention, that is, the table size and reference value of the symbol allocation reference table are determined. It is a flowchart of negotiation.

  In the flowchart shown in FIG. 9, first, a link is established as PCI Express (S02, S52). Next, basically, the presence or absence of the symbol allocation reference table is confirmed from the upstream component (component closer to the root complex) to the communication partner (downstream component) (S04, S54).

  If there is a symbol allocation reference table, information related to the symbol allocation reference table is allocated in advance in the configuration register area (defined in the PCI Express standard), and Configuration Write / Information related to the symbol allocation reference table is written / read by Read transaction (Configuration Read transaction is also a function provided in the PCI Express standard).

  If a table is provided (there is a symbol allocation setting function / symbol assembly setting function) (S06 / YES, S56 / YES), the table is set (S08, S58). If not (S06 / NO, S56 / NO), communication is performed as a normal PCI Express Link (S80).

  After that, the upstream component writes the symbol distribution function enable register of the partner (downstream component) to the enabled state (S10, S60), reads as a confirmation operation to confirm that it is in the enabled state (S12, S62), and communicates again. The end of the negotiation is notified by writing the symbol distribution function enable register of the other party (Downstream Component) to the enabled state (S14, S64, S16, S66). Thereafter, the downstream component starts communication with the symbol distribution function (S70). Further, in the upstream component, immediately after the symbol allocation function enable register write (S16) of the communication partner (downstream component) is performed, the own symbol allocation function enable register is written to the enabled state (S18), and communication is started by the symbol allocation function. (S20).

[Negotiation Flowchart (2)]
FIG. 10 shows another form of the negotiation flowchart used in the data transmission / reception unit in the physical layer of the high-speed serial communication in the semiconductor integrated circuit according to the present invention.

  The negotiation flowchart shown in FIG. 10 is for the case where symbols are allocated only to the lane where the link is established. For example, as shown in FIG. 11, it is assumed that connection cannot be established between logical lane 0 and logical lane 3. In this case, communication using only lane 1 and lane 2 becomes possible by setting a symbol allocation reference table using only logical lane 1 and logical lane 2 as shown in FIG.

  In the flowchart shown in FIG. 10, first, a link is established only in some lanes as PCI Express (S02 (2), S52 (2)). Next, basically, the presence or absence of the symbol allocation reference table is confirmed from the upstream component (component closer to the root complex) to the communication partner (downstream component) (S04, S54).

  If the symbol allocation reference table table is not provided (S06 / NO, S56 / NO), communication is performed as a normal PCI Express Link (S80).

When a symbol distribution reference table is provided (with a symbol distribution setting function) (S06 YES, S56 YES), the table is set by configuration write only for the lane where the link is established (S08 (2 ), S58 (2)).
Subsequent processing is the same as that shown in FIG.

1 is a block diagram of a data transmission / reception unit in a physical layer of high-speed serial communication in a semiconductor integrated circuit according to a first embodiment of the present invention. It is an example of a symbol distribution reference table. It is a figure which shows typically the mode of the assembly of the data from the logic lane assembled by the symbol assembly circuit. It is a block diagram of the data transmission / reception part of the physical layer of the high-speed serial communication in the semiconductor integrated circuit concerning the 2nd Embodiment of this invention. It is a schematic diagram which shows the example of a symbol distribution rule. It is a schematic diagram which shows the symbol distribution rule which concerns on the 3rd Embodiment of this invention. It is an example of the symbol distribution result by the symbol distribution rule which concerns on the 3rd Embodiment of this invention. It is a block diagram of the data transmission / reception part of the physical layer of the high-speed serial communication in the semiconductor integrated circuit concerning the 4th Embodiment of this invention. 4 is a flowchart of negotiation used in a data transmission / reception unit of a physical layer for high-speed serial communication in a semiconductor integrated circuit according to the present invention. It is another form of the flowchart of the negotiation utilized in the data transmission / reception part of the physical layer of the high-speed serial communication in the semiconductor integrated circuit which concerns on this invention. It is a schematic diagram which shows link establishment when a part logical lane cannot be connected. It is an example of the symbol distribution reference table set by the negotiation shown in FIG. It is a figure which shows a mode that packet data is byte-stripe. It is a schematic diagram which shows the example of allocation of the physical lane number with respect to a logical lane number in the prior art using PCI Express.

Explanation of symbols

2, 2 ', 2 "... Transmitter, 4, 4', 4" ... Receiver, 6, 6 ', 6 "... Symbol distribution circuit, 8, 8', 8" ... Symbol assembly circuit, 10 ... first symbol counter, 12 ... second symbol counter, 14 ... symbol allocation reference table, 30 ... mode selection register, 32 ... symbol reference for transmission Table 34... Symbol distribution reference table for reception.

Claims (7)

In a semiconductor integrated circuit including a data transmission / reception unit in the physical layer of high-speed serial communication,
The data transmission / reception unit includes a transmission unit and a reception unit,
The transmission unit includes a symbol distribution circuit, an 8B10B conversion circuit, a parallel serial (P2S) conversion circuit, and a first symbol counter.
The receiver is composed of a symbol assembly circuit, a 10B8B conversion circuit, a serial parallel (S2P) conversion circuit, and a symbol counter.
In addition, a symbol allocation reference table is included in the storage unit of the common part of the transmission unit and the reception unit,
The symbol distribution reference table is set by negotiation with the communication partner,
The symbol distribution circuit of the transmission unit refers to the symbol distribution reference table, determines a symbol distribution lane based on the count value from the first symbol counter, and the symbol assembly circuit of the reception unit performs symbol distribution A semiconductor integrated circuit characterized by referring to a reference table and assembling data from lanes based on a counter value from the second symbol counter. Instead of the above symbol distribution reference table,
A mode selection register for holding data indicating which of a plurality of preset symbol distribution rules to select;
The symbol distribution circuit of the transmission unit refers to a mode selection register, determines a symbol distribution lane based on data held in the mode selection register and a count value from the first symbol counter, and the reception unit The symbol assembling circuit refers to a mode selection register and symbol-assembles data from the lane based on data held in the mode selection register and a counter value from the second symbol counter. The semiconductor integrated circuit according to claim 1.   2. The semiconductor integrated circuit according to claim 1, wherein when a first symbol of a packet and a final symbol of a packet are included in one time cycle, a symbol distribution rule is temporarily fixed in a forward direction with respect to the lane. circuit. In the storage unit of the transmission unit and the storage unit of the reception unit, a transmission symbol allocation reference table and a reception symbol allocation reference table are separately provided,
The symbol distribution circuit of the transmission unit refers to the transmission symbol distribution reference table, determines a symbol distribution lane based on the count value from the first symbol counter, and the symbol assembly circuit of the reception unit includes: 2. The semiconductor integrated circuit according to claim 1, wherein data from the lane is symbol-assembled based on a counter value from the second symbol counter with reference to the reception symbol allocation reference table. Information related to the symbol distribution reference table is allocated in advance in the configuration register area,
The above negotiation is
2. The semiconductor integrated circuit according to claim 1, wherein after the link is established as PCI express, the information related to the symbol allocation reference table is written and read by Configuration Write / Read transaction.   6. The semiconductor integrated circuit according to claim 5, wherein the symbol distribution reference table is set only for a lane having a link established.   A serial transmission system comprising at least the semiconductor integrated circuit according to claim 1.

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