JP4849016B2 - Device test equipment - Google Patents

Description

  The present invention relates to a device test apparatus for testing a transmission device that transmits a serial signal.

  In recent years, many computers such as personal computers are equipped with high-speed serial interfaces such as PCI Express (registered trademark) and Serial ATA (Advanced Technology Attachment) as a standard in order to improve data transfer speed. In recent years, with the progress of high-definition broadcasting, or with the full shift to terrestrial digital broadcasting coming soon, HDMI (which can transmit video signals, audio signals, and control signals as digital signals with a single cable) High-Definition Multimedia Interface) is spreading.

  A high-speed serial interface consists of a transmitting device that transmits a serial signal and a receiving device that receives a serial signal transmitted via a cable. When testing a high-speed serial interface, both of these devices are tested. There is a need. Here, when testing the transmission device, it is necessary to perform a test using the serial signal itself transmitted from the transmission device. For example, when HDMI is taken as an example, the serial signal transmitted from the transmission device is: It is extremely high speed of several Gbps (bit per second). For this reason, conventionally, for example, by displaying the waveform of a serial signal using a broadband oscilloscope, tests such as rise time, fall time, skew, eye pattern opening, and jitter have been performed.

The following Patent Document 1 discloses a test system for testing a device that outputs LVDS (Low Voltage Differential Signal). Patent Document 2 below discloses a technique for testing the automatic resolution of a receiving device that receives a high-speed serial signal.
JP 2006-322775 A JP-T-2006-518947

  By the way, as described above, when testing a high-speed serial interface transmission device using an oscilloscope, the waveform of the serial signal transmitted for each transmission device is displayed and visually checked for rise time, fall time, skew, eye There is a problem in that it is necessary to obtain pattern aperture, jitter, and the like, and it takes a long time to test each transmitting device. Moreover, this test method cannot be said to be a realistic test method when there are a large number of transmitting devices.

  Generally, a device testing apparatus has been conventionally used for testing various devices. This device test apparatus determines whether a device is good (pass) / failure (fail) based on a signal obtained by applying a test pattern to a device to be tested. By using this device test apparatus, a wide variety of tests can be performed efficiently. However, since the serial signal transmitted from the high-speed serial interface is as high as several Gbps as described above, there is a problem that it cannot be tested by a conventional device test apparatus.

  Here, if a test is performed using a low-speed parallel signal obtained by receiving a high-speed serial signal transmitted from the transmission device by the reception device, it is considered that the transmission device can be tested by a conventional device test apparatus. It is done. However, such a test method has a problem that although it is known whether or not a defect has occurred, the cause of the defect (defective item) cannot be known.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a device test apparatus capable of efficiently testing a transmission device that transmits a high-speed serial signal.

In order to solve the above-described problems, a device test apparatus according to the present invention is characterized in that jitter is generated from a clock signal (CK10) having a predetermined frequency in a device test apparatus (1) that tests a transmission device (50) that transmits a serial signal. And a second clock signal (CK21) with reduced jitter is generated from a clock signal (CK20) having a frequency slightly lower than the predetermined frequency, and A clock generation unit (12) that outputs a start signal (ST) when an edge between the first clock signal and the second clock signal has a predetermined relationship, and the start signal is output from the clock generation unit A test signal sign for applying a test signal (D1) to the transmitting device in synchronization with the first clock signal at a timing. A sampling unit (13), a sampling unit (14) for undersampling a serial signal transmitted from the transmitting device upon application of the test signal in synchronization with the second clock signal, and a sampling obtained by the sampling unit And a test unit (11) that performs pass / fail determination of the transmission device based on data, and the clock signal that is the basis of the first clock signal and the second clock signal is output from the test unit, The frequency of the second clock signal is set to be lower than the frequency of the first clock signal by a frequency corresponding to an integer multiple of the minimum resolution of the test unit .
According to the present invention, at the timing when the start signal is output from the clock generator, the test signal is applied to the transmission device in synchronization with the first clock signal with reduced jitter, and is transmitted from the transmission device by the application of the test signal. The serial signal is undersampled in synchronization with the second clock signal with reduced jitter, and the quality of the transmitting device is determined based on this sampling data.
Further, in the device test apparatus of the present invention, the clock generation unit generates a first clock signal (21) in which jitter is reduced from the clock signal having the predetermined frequency, and the first filter (21) than the predetermined frequency. A second filter (22) for generating a second clock signal with reduced jitter from a clock signal having a slightly lower frequency, and a relative position between an edge position of the first clock signal and an edge position of the second clock signal; A clock monitoring unit (23) that monitors the positional relationship and outputs the start signal when both edge positions coincide with each other is provided.
In the device test apparatus of the present invention, a test start signal (S1) indicating that the clock monitoring unit starts applying the test signal to the transmitting device is output from the test unit, and the first clock The start signal is output when the edge position of the signal matches the edge position of the second clock signal .
In addition , the device test apparatus of the present invention includes a receiving unit (17) that detects a preset header from a serial signal transmitted from the transmitting device and converts the serial signal into a parallel signal, and the test unit Is characterized in that, when the header is detected by the receiving unit, the quality of the transmitting device is determined based on the converted parallel signal.
In addition, the device test apparatus of the present invention includes a jitter measuring unit (20) that measures jitter included in a serial signal transmitted from the transmitting device.
The device test apparatus of the present invention is a device in which the transmitting device transmits a transfer clock together with the serial signal, and the jitter measuring unit uses the serial signal based on the transfer clock transmitted from the transmitting device. It is characterized by measuring the jitter.
In addition, the device test apparatus of the present invention includes a frequency dividing unit (19) that divides the frequency of the serial signal transmitted from the transmitting device.
Furthermore, the device test apparatus of the present invention is characterized in that the test signal application unit applies a predetermined pattern in units of odd bits to the transmission device as the test signal.

  According to the present invention, the test signal is applied to the transmission device in synchronization with the first clock signal with reduced jitter, and the transmission device is applied with the application of the test signal in synchronization with the second clock signal with reduced jitter. Undersampling the serial signal transmitted from the receiver, and judging the quality of the transmitting device based on this sampling data, it is possible to efficiently test a transmitting device that transmits a high-speed serial signal is there. In addition, a header set in advance is detected from the serial signal transmitted from the transmission device, the serial signal is converted into a parallel signal, and the quality of the transmission device is determined based on the converted parallel signal. Since it is also possible to measure the jitter contained in the transmitted serial signal, there is an effect that a wide variety of tests can be performed efficiently.

  Hereinafter, a device test apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Configuration of device test equipment]
FIG. 1 is a block diagram showing a main configuration of a device test apparatus according to an embodiment of the present invention. As shown in FIG. 1, the device test apparatus 1 includes a test unit 11, a clock generation unit 12, a transmission control unit 13 (test signal application unit), a sampling unit 14, a sampling control unit 15, a selector 16, and a reception module 17 (reception unit). ), A reception control unit 18, a frequency divider 19 (frequency division unit), and a jitter measurement unit 20, and tests a transmission device (hereinafter referred to as DUT) 50.

  In this embodiment, it is assumed that the DUT 50 is an HDMI transmission device, and the serial signal transfer rate is 1.65 Gbps (the maximum transfer clock frequency is 165 MHz). As shown in FIG. 1, the DUT 50 includes a PLL (Phase Locked Loop) circuit 51, a clock signal transmission unit 52, and a serial signal transmission unit 53. The PLL circuit 51 generates the transfer clock from the first clock signal CK11 (details will be described later) output from the clock generation unit 12.

  The clock signal transmission unit 52 transmits the transfer clock generated by the PLL circuit 51 as a differential signal to the pair of clock lines L2. The serial signal transmission unit 53 converts the test data D1 (for example, 10-bit parallel data) output from the transmission control unit 13 into a differential serial signal, and uses the serial signal as a transfer clock from the PLL circuit 51. The data is transmitted to the pair of data lines L1 in synchronization. Note that an HDMI transmission device includes a plurality of pairs (for example, three pairs) of data lines that transmit serial signals that are differential signals and a pair of clock lines that transmit transfer clocks that are differential signals. In FIG. 1, only a pair of data lines L1 and a pair of clock lines L2 are shown for simplification of illustration.

  The device test apparatus 1 of the present embodiment is a test apparatus that can realize a compliance test of the DUT 50, and specifically, can implement a sampling test, a function test, and a jitter test. Here, the compliance test refers to a test in which a predetermined test item is performed in accordance with a predetermined procedure, and whether or not the DUT 50 is designed according to the specification. An HDMI transmitting device and a receiving device are required to pass such a compliance test so that compatibility problems do not occur.

  The above sampling test samples a serial signal transmitted from the DUT 50, and uses the sampling data to determine whether the rise time, fall time, eye pattern opening, etc. of the serial signal are within the standard. This is a test to be confirmed. The above function test is a test for confirming whether various functions that can be realized by HDMI are realized by the DUT 50. The jitter test is a test for confirming whether or not the jitter of the serial signal transmitted from the DUT 50 is within a preset jitter standard.

  The test unit 11 controls the operation of each block shown in FIG. 1 to control the operation of the device test apparatus, thereby realizing the sampling test, the function test, and the jitter test. Specifically, the test unit 11 controls the application of test data (test signal) D1 to the DUT 50, and in the case of a sampling test, performs a read control of the sampling data stored in the sampling control unit 15 to perform a function test. In this case, the reading control of the parallel signal stored in the reception control unit 18 is performed, and in the case of the jitter test, the reading control of the jitter signal S4 from the jitter measuring unit 20 is performed.

  In addition, when the test unit 11 reads the sampling data from the sampling control unit 15, the test unit 11 performs a predetermined software process on the read sampling data to obtain a serial signal that is a differential signal and sampling data of the transfer clock as a single signal. Performs processing to convert to an end signal. Furthermore, the test unit 11 performs pass / fail judgment indicating the quality of the DUT 50 based on the various data or signals read out.

  The test unit 11 outputs two types of clock signals CK10 and CK20 that are necessary for testing the DUT 50. The clock signal CK10 is a signal that mainly defines the application timing of the test data D1 to the DUT 50, and the clock signal CK20 is a signal that mainly defines the sampling timing in the sampling unit 14. The frequency of the clock signal CK10 is set to substantially the same frequency as the maximum frequency 165 MHz of the HDMI transfer clock, and the frequency of the clock signal CK20 is set to a frequency slightly lower than the frequency of the clock signal CK10. This is because the signal transmitted from the DUT 50 is undersampled.

Here, the test unit 11 is provided with a timing adjustment device (not shown) called a vernier, and the minimum resolution Δ of the test unit 11 (the shortest time for timing fine adjustment) is the internal operation of the test unit 11. Determined by frequency and vernier resolution. For example, when the internal operating frequency of the test unit 11 is 133 MHz and the resolution of the vernier is “512”, the minimum resolution Δ of the test unit 11 is Δ = (1 / (133 × 10 ⁶ )) / 512. ≈14.7 [psec]. The clock signals CK10 and CK20 are set based on the final resolution of the test unit 11.

  Specifically, if the set value of the vernier related to the clock signal CK10 is set to “412” which is a value between “0” and the resolution “512” of the vernier, the frequency f1 of the clock signal CK10 is f1 = 1/1 /. Since (412 × Δ) ≈165.2 MHz, the maximum frequency of the HDMI transfer clock can be set to substantially the same frequency as 165 MHz. On the other hand, if the vernier setting value for the clock signal CK20 is set to “413”, the frequency f2 of the clock signal CK20 is f2 = 1 / (413 × Δ) ≈164.8 MHz. Thus, the frequency f2 of the clock signal CK20 is set to a frequency that is lower than the frequency f1 of the clock signal CK10 by a frequency corresponding to an integer multiple (positive integer multiple) of the minimum resolution Δ in the test unit 11.

  The clock generator 12 generates a first clock signal CK11 with reduced jitter from the clock signal CK10 output from the test unit 11, and also generates a second clock signal CK21 with reduced jitter from the clock signal CK20. Further, when the edges of the first clock signal CK11 and the second clock signal CK21 have a predetermined relationship, the tart signal ST is output. The start signal ST is maintained at the “H (high)” level until a predetermined time elapses from the time when the edges of the first clock signal CK11 and the second clock signal CK21 are in the predetermined relationship. Signal. Details of the start signal ST will be described later.

  The clock generation unit 12 includes a filter unit 21 (first filter), a filter unit 22 (second filter), and a clock monitoring unit 23. The filter unit 21 generates a first clock signal CK11 with reduced jitter from the clock signal CK10 output from the test unit 11. The filter unit 22 generates a second clock signal CK21 with reduced jitter from the clock signal CK20 output from the test unit 11. These filter units 21 and 22 are provided for the purpose of reducing jitter because the clock signals CK10 and CK20 output from the test unit 11 are too jittery to be used for the high-speed DUT 50 test.

  Here, the filter units 21 and 22 can be configured to include a band-pass filter and a waveform shaping circuit. In the band pass filters provided in the filter units 21 and 22, the center frequency of each transmission band is set to a frequency substantially equal to the frequency of the clock signals CK10 and CK20 in order to enhance the jitter reduction effect. It is desirable to use one having the smallest possible width. If the jitter of the clock signals CK10 and CK20 can be suppressed to a necessary level, a low pass filter or a high pass filter can be used in addition to the band pass filter. The waveform shaping circuit is a circuit that performs waveform shaping of the signal output from the bandpass filter by comparing the signal output from the bandpass filter with a predetermined threshold value and binarizing the signal.

  The clock monitoring unit 23 monitors the relative positional relationship between the edge of the first clock signal CK11 and the edge of the second clock signal CK21, and outputs the start signal ST described above when both edges are in a predetermined relationship. To do. Here, the clock monitoring unit 23 receives the test start signal S1 from the test unit 11 (a signal indicating that the application of the test data D1 to the DUT 50 is started), and the test start signal S1 is at “H” level. In this case, and every time both rising edge positions coincide, the clock monitoring unit 23 outputs the start signal ST.

  The time during which the “H” level of the start signal ST is continued is determined by the vernier setting value described above and the number of measurement points required for the compliance test. For example, when the vernier setting value for the clock signal CK10 is “412” and the vernier setting value for the clock signal CK20 is “413”, the rising edges of the first clock signal CK11 and the second clock signal CK21 are The coincident period T0 is a time obtained by adding the minimum resolution Δ of the test section 11 to these least common multiples “170165”. If the number of measurement points during this period T0 is “412” and the number of measurement points required for the compliance test is at least “10000”, the “H” level of the start signal ST is continued. The time is a time corresponding to 25 cycles of the above-described cycle T0. As shown in FIG. 1, the clock monitoring unit 23 outputs the second clock signal CK21 generated by the filter unit 22 to the outside.

  The transmission control unit 13 performs application control of the test data D1 to the DUT 50 under the control of the test unit 11. Specifically, the transmission control unit 13 includes a memory (not shown) that stores test data D1 to be applied to the DUT 50. After the write control of the test data D1 to the memory is performed (or together with the write control). ) The test data D1 is applied to the DUT 50 by performing read control of the already written test data D1. Note that the above-described memory is desirably a dual port memory capable of performing writing and reading simultaneously.

  Test data D <b> 1 to be stored in a memory provided in the transmission control unit 13 is output from the test unit 11. The transmission control unit 13 controls the writing of the test data D1 to the memory using the write enable signal WE1 and the write clock signal WC1 output from the test unit 11. In addition, the transmission control unit 13 controls the reading of the test data D1 from the memory using the first clock signal CK11 and the start signal ST output from the clock generation unit 12. The read control is also performed by using the read enable signal RE1 output from the test unit 11 instead of the start signal ST output from the clock generation unit 12.

  The sampling unit 14 includes comparators 31a and 31b, comparators 32a and 32b, and comparators 33 and 34. The serial signal transmitted from the DUT 50 via the pair of data lines L1 and the pair of clock lines from the DUT 50 are provided. The transfer clock transmitted via L2 is sampled in synchronization with the second clock signal CK21. The comparators 31a and 31b are provided for the pair of data lines L1, and the comparators 32a and 32b are provided for the pair of clock lines L2. The comparator 33 is provided in parallel with the comparators 31a and 31b, and the comparator 34 is provided in parallel with the comparators 32a and 32b.

  The comparators 31a and 31b respectively compare the serial signal, which is a differential signal through each of the pair of data lines L1, with a predetermined reference voltage V1 at the timing of the rising edge of the second clock signal CK21, and the voltage of the serial signal is If the reference voltage V1 is exceeded, an “H” level signal is output. The comparators 32a and 32b compare the transfer clock, which is a differential signal through each of the pair of clock lines L2, with the reference voltage V1 at the timing of the rising edge of the second clock signal CK21, and the voltage of the transfer clock is the reference voltage. If V1 is exceeded, an “H” level signal is output. The value of the reference voltage V1 is varied under the control of the test unit 11.

  The comparator 33 converts a serial signal that is a differential signal via a pair of data lines L1 into a single-end signal, and the comparator 34 converts a transfer clock that is a differential signal via a pair of clock lines L2 into a single-end signal. To do. It should be noted that the second clock signal CK21 is not input to the comparators 33 and 34, and the serial signal and the transfer clock are not sampled. Signals (sampling data) indicating the comparison results of the comparators 31a and 31b and the comparators 32a and 32b are output to the sampling control unit 15, the signal from the comparator 33 is output to the selector 16, and the signal from the comparator 34 is the jitter measurement unit 20. Is output.

  If there is an individual difference between the comparators 31a, 31b, 32a, and 32b, a time position shift may occur between the sampling data output from these. For example, the sampling data output from the comparator 31b may be delayed with respect to the sampling data output from the comparator 31a. In this embodiment, in order to simplify the explanation, it is assumed that there is no shift in the time position of the sampling data due to the individual difference between the comparators 31a, 31b, 32a, and 32b.

  The sampling control unit 15 includes a memory (not shown) that stores sampling data from the comparators 31a and 31b and the comparators 32a and 32b. The sampling control unit 15 controls writing of the sampling data to the memory and controls the testing unit 11. Below, the sampling data already stored in the memory is read out. Specifically, the sampling control unit 15 performs control to write sampling data from the comparators 31a and 31b and the comparators 32a and 32b to the memory in synchronization with the second clock signal CK21 output from the clock generation unit 12. Note that the above-described memory is desirably a dual port memory capable of performing writing and reading simultaneously.

  Note that, when the sampling data writing capacity to the memory is exhausted, the sampling control unit 15 outputs a full (FULL) signal S2 indicating that to the testing unit 11. In addition, the sampling control unit 15 controls the reading of sampling data from the memory using the read enable signal RE2 and the read clock signal RC2 output from the test unit 11. The sampling data read by the sampling control unit 15 is output to the test unit 11.

  The selector 16 has an input end that receives the signal output from the comparator 33 of the sampling unit 14 and two output ends, and selects a signal input to the input end under the control of the test unit 11. Output from one of the output terminals. The test unit 11 controls the selector 16 so that the output terminal to which the receiving module 17 is connected is selected in the case of the functional test, and the output terminal to which the frequency divider 19 is connected is selected in the case of the jitter test. . The receiving module 17 receives a serial signal (a signal obtained by converting a serial signal transmitted from the DUT 50 into a single-ended signal) via the selector 16 and the first clock signal CK11 generated by the clock generator 12, A header set in advance is detected from the input serial signal, and the input serial signal is converted into a parallel signal.

  The reception control unit 18 outputs a signal indicating the header detection result of the reception module 17 to the test unit 11 as a header detection signal S3. The reception control unit 18 includes a memory (not shown) that stores the parallel signal converted by the reception module 17. After performing parallel signal write control on the memory (or with write control), The parallel signal that has already been written is read out and output to the test unit 11. Note that the above-described memory is desirably a dual port memory capable of performing writing and reading simultaneously.

  The reception control unit 18 performs writing control of the parallel signal to the memory using the write enable signal WE3 output from the reception module 17 and the first clock signal CK11 output from the clock generation unit 12. Further, the reception control unit 18 performs reading control of the parallel signal from the memory using the read enable signal RE3 and the read clock signal RC2 output from the test unit 11. The parallel signal read by the reception control unit 18 is output to the test unit 11.

  The frequency divider 19 divides the serial signal via the selector 16 by a predetermined frequency division ratio. Note that the frequency division ratio of the frequency divider 19 is set to a value that reduces the frequency of the serial signal to a frequency at which the jitter measurement unit 20 can measure the jitter. The jitter measuring unit 20 uses the edge position of the signal output from the comparator 34 of the sampling unit 14 as a reference, and converts the shift time from the reference of the edge position of the signal output from the frequency divider 19 into a voltage, thereby converting the serial position into a voltage. Measure signal jitter. Then, the jitter measurement unit 20 outputs a signal indicating the measurement result to the test unit 11 as a jitter signal S4.

  Next, the operation of the device testing apparatus 1 according to the embodiment of the present invention having the above-described configuration will be described. As described above, the device test apparatus 1 of the present embodiment can implement a sampling test, a function test, and a jitter test. For this reason, below, operation | movement in each of these tests is demonstrated in order. In the following description, it is assumed that the clock signals CK10 and CK20, the write clock signal WC1, and the read clock signal RC2 are always output from the test unit 11 for the sake of simplicity. For this reason, it is assumed that clock signals CK11 and CK21 are always output from the clock generator 12.

[Operation during sampling test]
FIG. 2 is a block diagram in which only the configuration used for the sampling test is extracted from the configuration of the device test apparatus 1 shown in FIG. FIG. 3 is a flowchart showing an outline of operations performed in the device test apparatus 1 during the sampling test. The operation during the sampling test will be described with reference to these drawings.

  Before the sampling test is started, the test unit 11 writes the test data D1 to the transmission control unit 13 (step S11). Specifically, test data D1 and write enable signal WE1 are output from test unit 11 to transmission control unit 13, and transmission control unit 13 transmits a write clock signal while write enable signal WE1 is at the “H” level. The test data D1 is written by writing the test data D1 in a memory (not shown) in synchronization with the WC1. When the writing of the test data D1 is completed, the write enable signal WE1 becomes “L” level and the output of the test data D1 from the test unit 11 is stopped. Further, the test unit 11 sets the value of the reference voltage V1 input to the comparators 31a, 31b, 32a, and 32b of the sampling unit 14 to a predetermined value.

  When the writing of the test data D1 to the transmission control unit 13 is completed, a test start signal S1 is output from the test unit 11, thereby starting a test for the DUT 50 (step S12). FIG. 4 is a timing chart showing the relationship between the start signal ST, the first clock signal CK11, the second clock signal CK21, and the like. In FIG. 4, only the rising edge of the second clock signal CK21 is indicated by an arrow.

  When the test start signal S1 output from the test unit 11 is input to the clock monitoring unit 23 of the clock generation unit 12, the first clock signal CK11 is first output from the clock monitoring unit 23 after the test start signal S1 is input. The start signal ST is output when the rising edge position of the second clock signal CK21 coincides with the rising edge position of the second clock signal CK21 (time t1 in FIG. 4). As shown in FIG. 4, the start signal ST is “H” for a predetermined period after rising (a time corresponding to 25 periods of the period T0 in which the rising edge positions of the first clock signal CK11 and the second clock signal CK21 coincide). ”Is a signal that continues the level.

  The start signal ST output from the clock monitoring unit 23 is input to the read enable signal input terminal (RE) of the transmission control unit 13. As a result, test data stored in a memory (not shown) included in the transmission control unit 13 is read in synchronization with the first clock signal CK11 output from the clock generation unit 12. The test data D1 read by the transmission control unit 13 is sequentially applied to the DUT 50 (step S13). The test data D1 applied to the DUT 50 is converted into a differential serial signal by the serial signal transmission unit 53 provided in the DUT 50, and transmitted to the pair of data lines L1 in synchronization with the transfer clock from the PLL circuit 51. The transfer clock generated by the PLL circuit 51 is converted into a differential signal by the clock signal transmission unit 52 and transmitted to the pair of clock lines L2.

  If the test data D1 is 10-bit parallel data, the serial signal transmitted from the DUT 50 is a 10-bit continuous signal in each cycle of the first clock signal CK11 as shown in FIG. The serial signal and transfer clock transmitted from the DUT 50 are input to the sampling unit 14 and undersampled (step S14). That is, the serial signal, which is a differential signal through each of the pair of data lines L1, is compared with the reference voltage V1 at the rising edge timing of the second clock signal CK21 in the comparators 31a and 31b, and the voltage of the serial signal is the reference. If the voltage V1 is exceeded, an “H” level signal is output. Similarly, the transfer clock, which is a differential signal through each of the pair of clock lines L2, is compared with the reference voltage V1 at the rising edge timing of the second clock signal CK21 in the comparators 32a and 32b, and the voltage of the transfer clock is If the reference voltage V1 is exceeded, an “H” level signal is output.

  Here, the test data D1 is applied to the DUT 50 in synchronization with the first clock signal CK11. On the other hand, the serial signal and the transfer clock transmitted from the DUT 50 are undersampled using the second clock signal CK21 having a frequency slightly lower than the frequency of the first clock signal CK11. Therefore, referring to FIG. 4, the rising edge of the second clock signal CK21 that defines the measurement point (sampling point) within the period T0 in which the rising edge positions of the first clock signal CK11 and the second clock signal CK21 coincide. It can be seen that the position of the edge (indicated by the arrow) within one cycle of the first clock signal CK11 is slightly different for each cycle. It can also be seen that the above operation is repeated while the start signal ST is at the “H” level (until the time corresponding to 25 periods T0 from time t1 to time t2 elapses).

  Each of the signals (sampling data) output from the comparators 31a and 31b and the comparators 32a and 32b is output to the sampling control unit 15 and is synchronized with the second clock signal CK21 used for undersampling in the sampling unit 14. Then, it is written in a memory (not shown) provided in the sampling control unit 15 (step S15). In this manner, the serial signal and the transfer clock transmitted from the DUT 50 are sequentially undersampled by the sampling unit 14, and the sampling data is written to the sampling control unit 15.

  When the above operation is repeated and the sampling data writing capacity to the memory included in the sampling control unit 15 is lost, the full signal S2 indicating that fact is output from the sampling control unit 15 to the test unit 11 (step S16). ). The test unit 11 reads the sampling data from the sampling control unit 15 by outputting the read enable signal RE2 based on the full signal S2 (step S17). Note that while the read enable signal RE2 is at the “H” level, sampling data is sequentially read from the sampling control unit 15 in synchronization with the read clock RC2.

  Next, the test unit 11 determines whether or not the sampling test has been completed (step S18). When it is determined that the sampling test is not completed (when the determination result is “NO”), the test unit 11 determines the value of the reference voltage V1 input to the comparators 31a, 31b, 32a, and 32b of the sampling unit 14. Is changed (step S19), the test start signal S1 is output again, and the DUT 50 is tested. In this manner, the operation of sampling the serial signal and the transfer clock is repeated while changing the value of the reference voltage V1 until the sampling test is completed. During the test of the DUT 50, it is desirable to apply the test data D1 continuously without stopping the application.

  On the other hand, when it is determined that the sampling test has been completed (when the determination result is “YES”), a predetermined software process is performed on the sampling data read from the sampling control unit 15 to obtain a serial signal that is a differential signal. Processing to convert the signal and the transfer clock into a single-ended signal is performed. The sampling data subjected to the above processing becomes data indicating the waveform of the serial signal and the transfer clock. Next, the test unit 11 determines pass / fail indicating whether the DUT 50 is good or not based on the converted signal (step S20). Specifically, it is determined using the sampling data obtained by the above processing whether the rise time, fall time, eye pattern opening, etc. of the serial signal are within the standard.

  As described above, in the sampling test, the clock generator 12 generates the first clock signal CK11 and the second clock signal CK21 with reduced jitter from the clock signals CK10 and CK20 from the test unit 11. Then, the test data D1 is applied to the DUT 50 in synchronization with the first clock signal CK11 with reduced jitter, and the serial signal and the transfer clock transmitted from the DUT 50 are sampled at the timing of the second clock signal CK21 with reduced jitter. ing. For this reason, even if the operating speed of the DUT 50 is as high as several Gbps, the test can be performed without any problem. Further, in the present embodiment, it is not necessary to display the serial signal waveform on an oscilloscope and visually determine it as in the prior art, so that objective determination can be performed in a short time. For this reason, an efficient test is possible even if the number of DUTs 50 is large.

[Operation during functional test]
FIG. 5 is a block diagram in which only the configuration used for the function test is extracted from the configuration of the device test apparatus 1 shown in FIG. FIG. 6 is a flowchart showing an outline of operations performed in the device test apparatus 1 during the function test. The operation during the function test will be described with reference to these drawings. Before the function test is started, the test unit 11 writes test data D1 to the transmission control unit 13 (step S21).

  Specifically, test data D1 and write enable signal WE1 are output from test unit 11 to transmission control unit 13, and transmission control unit 13 transmits a write clock signal while write enable signal WE1 is at the “H” level. The test data D1 is written by writing the test data D1 in a memory (not shown) in synchronization with the WC1. When the writing of the test data D1 is completed, the write enable signal WE1 becomes “L” level and the output of the test data D1 from the test unit 11 is stopped.

  When the writing of the test data D1 to the transmission control unit 13 is completed, the read enable signal RE1 is output from the test unit 11, thereby starting a test for the DUT 50 (step S22). The enable signal RE1 is input to the read enable signal input terminal (RE) of the transmission control unit 13. As a result, test data stored in a memory (not shown) included in the transmission control unit 13 is read in synchronization with the first clock signal CK11 output from the clock generation unit 12. The test data D1 read by the transmission control unit 13 is sequentially applied to the DUT 50 (step S23). The test data D1 applied to the DUT 50 is converted into a differential serial signal by the serial signal transmission unit 53 provided in the DUT 50, and transmitted to the pair of data lines L1 in synchronization with the transfer clock from the PLL circuit 51.

  The serial signal transmitted from the DUT 50 is received by the comparator 33 of the sampling unit 14 and converted into a single-ended signal, and the converted signal is input to the receiving module 17 via the selector 16. Then, the reception module 17 detects the header included in the serial signal. When the header is not detected by the reception module 17 (when the determination result of step S24 is “NO”), the reception module 17 determines whether or not a certain time has passed since the header detection was started. (Step S25). If the determination result in step S25 is “NO”, the header is detected again. On the other hand, if the determination result in step S25 is “YES”, it is determined that an error has occurred. .

  On the other hand, when the header is detected by the reception module 17 (when the determination result of step S24 is “YES”), the reception module 17 outputs a signal indicating the detection result to the reception control unit 18. At the same time, the serial signal is converted into a parallel signal and output to the reception control unit 18 together with the write enable signal WE3 (step S26). While the write enable signal WE3 output from the reception module 17 is at “H” level, the reception control unit 18 outputs the parallel signal output from the reception module 17 to a memory (not shown) in synchronization with the first clock signal CK11. Write (step S27). A signal indicating the detection result output from the reception module 17 to the reception control unit 18 is output to the test unit 11 as a header detection signal S3.

  When the test unit 11 receives the header detection signal S3 output from the reception control unit 18, the test unit 11 outputs a read enable signal RE3. As a result, the reception control unit 18 reads out the parallel data stored in the memory in synchronization with the read clock RC2, and outputs it to the test unit 11 (step S28). Next, the test unit 11 determines pass / fail indicating whether the DUT 50 is good or bad using the parallel signal read in step S28 (step S29).

  As described above, during the function test, the test data D1 is applied to the DUT 50 using the first clock signal CK11 generated by the clock generation unit 12, and a high-speed serial signal is received as a low-speed parallel signal. After conversion, writing to the reception control unit 18 is performed using the first clock signal CK11. Here, since the detection of the header is performed on the high-speed serial signal before being converted into the low-speed parallel signal, it is possible to test whether various functions that can be realized with HDMI can be realized with the DUT 50. it can. In addition, the sampling test and the function test described above can be easily switched. Therefore, an efficient test such as performing a function test immediately after the sampling test is possible.

[Operation during jitter test]
FIG. 7 is a block diagram in which only the configuration used for the jitter test is extracted from the configuration of the device test apparatus 1 shown in FIG. FIG. 8 is a flowchart showing an outline of operations performed by the device test apparatus 1 during a jitter test. The operation during the jitter test will be described with reference to these drawings. Similarly to the sampling test and the function test, even during the jitter test, the test unit 11 writes the test data D1 to the transmission control unit 13 before starting the test (step S31).

  Specifically, test data D1 and write enable signal WE1 are output from test unit 11 to transmission control unit 13, and transmission control unit 13 transmits a write clock signal while write enable signal WE1 is at the “H” level. The test data D1 is written by writing the test data D1 in a memory (not shown) in synchronization with the WC1. However, the test data D1 written to the memory of the transmission control unit 13 is data repeated in units of odd bits (for example, 9 bits). This is because if the data applied to the DUT 50 is repeated data in units of even bits, only the edge jitter related to a specific bit is measured, and the edge jitter related to other bits cannot be measured. This is to prevent the occurrence of a malfunction.

  FIG. 9 is a diagram illustrating an example of test data D1 used at the time of jitter measurement. In FIG. 9, a cycle T <b> 11 indicates the cycle of the first clock signal CK <b> 11, and test data D <b> 1 that is 10-bit parallel data is output from the test unit 11 and written to the transmission control unit 13 every cycle T <b> 11. In FIG. 9, for convenience of explanation, the first bit to the tenth bit of the test data D1 are arranged in time order. The period T12 indicates the time required to transmit a 9-bit serial signal from the DUT 50. Note that data D2 in FIG. 9 is data obtained by dividing test data D1 by 2, and data D3 is data obtained by dividing test data D3 by 4.

  Assuming that the test data D1 output from the test unit 11 is data repeated in units of even 10 bits, the test data D1 is divided into two or four times within each cycle T11. The edge position in is the same in all periods T11. On the other hand, if the test data D1 output from the test unit 11 is data repeated in units of odd 9 bits consisting of “101010100”, the test data D1 is divided by two as shown in FIG. The edge positions in each period T11 of the data D3 obtained by dividing the data D2 and the test data D1 by 4 are different positions for each period T11. For this reason, it becomes possible to measure the jitter of the edge concerning all the bits of the test data D1.

  When the writing of the test data D1 to the transmission control unit 13 is completed, a read enable signal RE1 is output from the test unit 11, thereby starting a test for the DUT 50 (step S32). The enable signal RE1 is input to the read enable signal input terminal (RE) of the transmission control unit 13. As a result, test data stored in a memory (not shown) included in the transmission control unit 13 is read in synchronization with the first clock signal CK11 output from the clock generation unit 12. The test data D1 read by the transmission control unit 13 is sequentially applied to the DUT 50 (step S33). The test data D1 applied to the DUT 50 is converted into a differential serial signal by the serial signal transmission unit 53 provided in the DUT 50, and transmitted to the pair of data lines L1 in synchronization with the transfer clock from the PLL circuit 51. The transfer clock generated by the PLL circuit 51 is converted into a differential signal by the clock signal transmission unit 52 and transmitted to the pair of clock lines L2.

  The serial signal transmitted from the DUT 50 is received by the comparator 33 of the sampling unit 14 and converted into a single end signal. The converted signal is input to the frequency divider 19 via the selector 16, and after being divided by a predetermined frequency dividing ratio, is input to the jitter measuring unit 20. The transfer clock transmitted from the DUT 50 is received by the comparator 34 of the sampling unit 14 and converted into a single end signal, and then input to the jitter measuring unit 20. Then, the jitter measuring unit 20 converts the deviation time from the reference of the edge position of the signal output from the frequency divider 19 into a voltage with the edge position of the signal output from the comparator 34 of the sampling unit 14 as a reference. To measure the jitter of the serial signal (step S34).

  When jitter measurement is performed by the jitter measurement unit 20, the test unit 11 reads the measurement result as a jitter signal S4 (step S35). Next, the test unit 11 determines whether or not the jitter test has been completed (step S36). When it is determined that the jitter test has not ended (when the determination result is “NO”), the test unit 11 outputs the read enable signal RE1 again to test the DUT 50. On the other hand, when it is determined that the jitter test is completed (when the determination result is “YES”), the test unit 11 determines whether or not the jitter is within the standard based on the jitter signal S4 read in step S35. (Pass / Fail) is determined (step S37). Note that the average value of jitter can be obtained by repeating the processes of steps S32 to S35 shown in FIG. 8, but the determination process of step S36 may be omitted if the average value need not be obtained.

  As described above, during the jitter test, the test data D1 is applied to the DUT 50 using the first clock signal CK11 generated by the clock generation unit 12, and transmitted from the DUT 50 using the transfer clock transmitted from the DUT 50 as a reference. The jitter of the serial signal is measured. For this reason, it is possible to perform a jitter test efficiently. In addition, since jitter measurement is performed using data that is repeated in units of odd bits, it is possible to measure the edge jitter associated with each bit of the test data D1.

  The device test apparatus according to the embodiment of the present invention has been described above, but the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above embodiment, the serial signal and the transfer clock transmitted from the DUT 50 are sampled as they are as differential signals, and converted into single-ended signals by performing predetermined software processing in the test unit 11. However, the conversion process to the single-ended signal may be performed by the sampling unit 14.

  In the above embodiment, for the sake of simplicity of explanation, the time position shift between the sampling data caused by the individual differences of the comparators 31a, 31b, 32a, and 32b is ignored. However, in actuality, since these time position shifts occur, the processing for finely adjusting the time position shifts may be performed by the sampling unit 14 in hardware. Alternatively, the time position between the sampling data read from the sampling control unit 15 may be finely adjusted by the test unit 11 by software without performing the fine adjustment in the sampling unit 14.

  FIG. 10 is a block diagram illustrating a modification of the sampling unit 14. In FIG. 10, the same blocks as those shown in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 10, in this modification, waveform synthesizing units 40a and 40b are added to the sampling unit 14 shown in FIG. 1, and a skew adjusting unit 41 is provided. The waveform synthesizer 40a synthesizes the sampling data output from each of the comparators 31a and 31b and converts it into sampling data of a single end signal. Similarly, the waveform synthesizer 40b synthesizes the sampling data output from each of the comparators 32a and 32b and converts it to single-ended signal sampling data. The sampling data synthesized by these waveform synthesis units 40 a and 40 b is output to the sampling control unit 15.

  The skew adjustment circuit 41 is a circuit that adjusts the timing of the second clock signal CK21 input to the comparators 31a, 31b, 32a, and 32b based on the characteristics of the comparators 31a, 31b, 32a, and 32b. The amount of time position deviation between sampling data caused by individual differences among the comparators 31a, 31b, 32a, and 32b is measured in advance, and data indicating the amount of deviation is input to the skew adjustment unit 41. With the above configuration, processing for finely adjusting a time position shift between sampling data and conversion processing to a single-ended signal can be performed in hardware.

  FIG. 11 is a block diagram illustrating another modification of the sampling unit 14. In FIG. 11, the same blocks as those shown in FIG. 1 are denoted by the same reference numerals. In the modification shown in FIG. 11A, a high-speed operational amplifier 42 and a comparator 44 are provided instead of the comparators 31a and 31b of the sampling unit 14 shown in FIG. 1, and a high-speed operational amplifier is provided instead of the comparators 32a and 32b. 43 and a comparator 45 are provided. A skew adjustment circuit 41 similar to that of the modification shown in FIG. 10 is provided.

  The high-speed operational amplifiers 42 and 43 are operational amplifiers that can operate normally even if the serial signal transfer speed is as high as several Gbps, and each converts the serial signal and the transfer clock, which are differential signals, into single-ended signals. The comparators 44 and 45 compare the serial signal (single-end signal) output from the high-speed operational amplifiers 42 and 43 with a predetermined reference voltage V1 at the timing of the rising edge of the second clock signal CK21, respectively, and the serial signal voltage is If the reference voltage V1 is exceeded, an “H” level signal is output. With the above configuration, the processing for finely adjusting the time position shift between the sampling data and the conversion processing to the single-ended signal can be performed in hardware as in the sampling unit 14 shown in FIG.

  In the modification shown in FIG. 11B, a high-speed sample and hold circuit 46 and a high-speed A / D conversion circuit 48 are provided instead of the comparators 31a and 31b of the sampling unit 14 shown in FIG. Instead, a high-speed sample / hold circuit 47 and a high-speed A / D conversion circuit 49 are provided. As in the modification shown in FIG. 11A, a skew adjustment circuit 41 is provided.

  The high-speed sample and hold circuits 46 and 47 are circuits that hold the level of the serial signal and the transfer clock at the timing of the rising edge of the second clock signal CK21, and even if the transfer speed of the serial signal is as high as several Gbps. Normal operation is possible. The high-speed A / D conversion circuits 48 and 49 are circuits capable of high-speed operation similar to the high-speed sample / hold circuits 46 and 47, and the level held by the high-speed sample / hold circuits 46 and 47 is set to the second clock signal. Binarization (digitization) is performed at the timing of CK21. Also with the above configuration, the processing for finely adjusting the time position deviation between the sampling data and the conversion processing to the single-ended signal can be performed in hardware.

  In the above-described embodiment, by setting the setting value of the vernier provided in the test unit 11 to “412”, the frequency f1 of the clock signal CK10 is set to substantially the same frequency as the maximum frequency 165 MHz of the HDMI transfer clock. The frequency f2 of the clock signal CK20 is set to 164.8 MHz, which is slightly lower than the frequency f1 of the clock signal CK10, by setting the vernier setting value to “413”. This set value is merely an example, and the frequency of the clock signals CK10 and CK20 is set to an arbitrary frequency as long as the set value of the vernier is within the range of the vernier resolution (the range of “0” to “512”). can do.

It is a block diagram which shows the principal part structure of the device test apparatus by one Embodiment of this invention. It is the block diagram which extracted only the structure used for a sampling test among the structures of the device test apparatus 1 shown in FIG. It is a flowchart which shows the outline | summary of the operation | movement performed with the device test apparatus 1 at the time of a sampling test. 4 is a timing chart showing the relationship between a start signal ST, a first clock signal CK11, a second clock signal CK21, and the like. It is the block diagram which extracted only the structure used for a function test among the structures of the device test apparatus 1 shown in FIG. It is a flowchart which shows the outline | summary of the operation | movement performed with the device test apparatus 1 at the time of a function test. It is the block diagram which extracted only the structure used for a jitter test among the structures of the device test apparatus 1 shown in FIG. It is a flowchart which shows the outline | summary of the operation | movement performed with the device test apparatus 1 at the time of a jitter test. It is a figure which shows an example of the test data D1 used at the time of jitter measurement. It is a block diagram which shows the modification of the sampling part. It is a block diagram which shows the other modification of the sampling part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Device test apparatus 11 Test part 12 Clock generation part 13 Transmission control part 14 Sampling part 17 Reception module 19 Frequency divider 20 Jitter measurement part 21, 22 Filter part 23 Clock monitoring part 50 DUT
CK10, CK20 clock signal CK11 first clock signal CK21 second clock signal D1 test data S1 test start signal ST start signal

Claims (8)

In a device test apparatus for testing a transmission device that transmits a serial signal,
Generating a first clock signal with reduced jitter from a clock signal having a predetermined frequency, generating a second clock signal with reduced jitter from a clock signal having a frequency slightly lower than the predetermined frequency, and A clock generator that outputs a start signal when edges of the first clock signal and the second clock signal have a predetermined relationship;
A test signal application unit that applies a test signal to the transmission device in synchronization with the first clock signal at a timing when the start signal is output from the clock generation unit;
A sampling unit that undersamples a serial signal transmitted from the transmitting device by application of the test signal in synchronization with the second clock signal;
Based on the sampling data obtained by the sampling section, and a test unit for performing quality determination of the transmission device,
The clock signal that is the basis of the first clock signal and the second clock signal is output from the test unit,
The frequency of the second clock signal is set to a frequency lower than the frequency of the first clock signal by a frequency corresponding to an integral multiple of the minimum resolution of the test unit.
Device testing apparatus characterized by. The clock generation unit generates a first clock signal with reduced jitter from the clock signal having the predetermined frequency; and
A second filter for generating a second clock signal with reduced jitter from a clock signal having a frequency slightly lower than the predetermined frequency;
A clock monitoring unit that monitors a relative positional relationship between an edge position of the first clock signal and an edge position of the second clock signal, and outputs the start signal when both edge positions coincide with each other. The device test apparatus according to claim 1, wherein:   The clock monitoring unit outputs a test start signal indicating that the application of the test signal to the transmission device is started from the test unit, and an edge position of the first clock signal and an edge position of the second clock signal The device test apparatus according to claim 2, wherein the start signal is output when the values coincide with each other. While detecting a header set in advance from a serial signal transmitted from the transmission device, and including a receiving unit that converts the serial signal into a parallel signal,
  When the header is detected by the reception unit, the test unit performs pass / fail determination of the transmission device based on the converted parallel signal.
  The device test apparatus according to claim 1, wherein the device test apparatus is a device test apparatus. The device test apparatus according to claim 1, further comprising a jitter measurement unit that measures jitter included in a serial signal transmitted from the transmission device. The transmission device is a device that transmits a clock signal together with the serial signal,
  The device test apparatus according to claim 5, wherein the jitter measurement unit measures jitter of the serial signal with reference to a clock signal transmitted from the transmission device. The device test apparatus according to claim 6, further comprising a frequency divider that divides a frequency of a serial signal transmitted from the transmission device. 8. The device test apparatus according to claim 5, wherein the test signal application unit applies a predetermined pattern in units of odd bits to the transmission device as the test signal. 9. .

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