JP4849635B2 - Signal discrimination circuit and optical signal reception discrimination circuit - Google Patents

Description

  When dealing with a signal in which signals of a plurality of bit rates are time-division multiplexed, the present invention provides an integer multiple when all or some of the plurality of bit rates are not in an integer multiple or a fraction of an integer. Alternatively, the present invention relates to a signal discriminating circuit that instantaneously discriminates a signal for each bit rate group or bit rate that has a 1 / integer relationship, and an optical signal reception discriminating circuit that discriminates and receives an optical signal by using this signal discrimination circuit. is there.

  The demands of users who use data transmission services are diversifying with the times, and services with a plurality of bit rates are provided. In general, a receiving circuit that receives a signal is designed to receive only a signal of a specific bit rate, but a multi-rate receiver that can receive a signal of a plurality of bit rates with the aim of reducing capital investment. The need for

  Up to now, in order to realize a system in which the bit rate of a signal is switched with time (time division multiplexing), a method of mainly using a burst receiver capable of instantaneously switching and receiving signals of a plurality of bit rates Has been proposed. This is because when a receiver that has a relatively slow response performance to bit rate switching is used like a normal continuous signal receiver, the receiver state takes a relatively long time each time the bit rate is switched. This is because the signal cannot be received during that time, and the transmission efficiency is significantly deteriorated.

  For example, Patent Document 1 and Patent Document 2 propose a system for instantaneously determining the data speed and switching the clock of the receiver for reception. What can be said in common in these systems is that the bit rates that can be handled are limited to those having an integer multiple or a fraction of an integer each.

When it is not necessary to switch the light receiving sensitivity for switching the bit rate, the clock recovery circuit may have a function of instantaneously switching the clock signal with respect to the bit rate. Since the frequency synchronization circuit to be used has a slow response performance and a narrow frequency variable range, a clock frequency of a multiplier circuit, a frequency divider circuit (1/2 frequency divider circuit 308 of Patent Document 1, and frequency divider circuit 423 of Patent Document 2), etc. Is converted into an integer multiple or a fraction of an integer (strictly, a power of 2 or 1 of a power of 2). For this reason, the receivable bit rate is limited to an integer multiple or a fraction of an integer of the oscillation frequency of the oscillator.
JP 2002-051033 A JP-A-8-008954

  As described above, according to the conventional technique, when a plurality of bit rates are handled, it cannot be saved unless an integer multiple or a fraction of an integer is established between the bit rates. When handling multiple bit rates that are not an integer multiple or a fraction of an integer, a clock recovery circuit inside the clock / data recovery circuit is provided for each bit rate, and instantaneously corresponding to the bit rate of the input signal A switching function is required, but in general, when multiple clock recovery circuits having an oscillation circuit are provided, interference between the oscillation circuits may occur due to electromagnetic coupling, which may require shielding between the oscillation circuits. was there.

  Further, the receiving devices of Patent Document 1 and Patent Literature 2 are configured to output received signals of different bit rates from the same output terminal. For this reason, even if the receiver can receive a bit rate that is not an integer multiple or a fraction of an integer, the circuit and device connected to the subsequent stage of the receiver are also an integer multiple or a fraction of an integer. There is a problem that it is necessary to be able to cope with a plurality of unrelated bit rates.

  It is an object of the present invention to suppress interference between oscillation circuits, which is a problem when one clock / data recovery circuit has a plurality of oscillation circuits. It is an object of the present invention to provide a signal discriminating circuit and an optical signal receiving discriminating circuit that do not require a function for handling a plurality of bit rates that are not related to one of the above.

In order to achieve the above object, the signal discrimination circuit according to the first aspect of the present invention provides a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not in an integer multiple or a fraction of an integer. A signal discriminating circuit for discriminating and recognizing and having a clock / data recovery circuit corresponding to each bit rate group or each bit rate having an integer multiple or a fraction of an integer, and said time division multiplexed The signal is distributed to all the clock and data recovery circuits, and a gate circuit is provided in or inside the clock and data recovery circuit, and the opening and closing of the gate circuit is controlled by a bit rate control signal. The multiplexed signals are distinguished and output for each bit rate group or each bit rate having an integer multiple or a fraction of an integer.
The signal discriminating circuit of the invention according to claim 2 is a signal discriminating circuit for discriminating and regenerating a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer. A clock / data recovery circuit corresponding to each bit rate group or each bit rate having an integer multiple or a fraction of an integer, and one signal input terminal and all the clock / data recovery circuits By connecting a route switching circuit between the input terminals of the, and controlling the route switching circuit with a bit rate control signal, the time-division multiplexed signal has an integer multiple or a fraction of an integer relationship. Discriminating and outputting for each bit rate group or for each bit rate.
An optical signal reception discriminating circuit according to a third aspect of the present invention converts an optical signal obtained by time-division multiplexing a plurality of bit rate signals into a current signal using a photoelectric conversion element, and the current signal is amplified by impedance conversion amplification. An optical signal reception discriminating circuit that performs conversion amplification into a voltage signal by a circuit, amplifies it to a voltage signal having a constant amplitude using a post-amplifier circuit, and discriminates and reproduces it by a clock data reproduction circuit,
A signal discriminating circuit according to claim 1 or 2 is provided instead of the clock and data recovery circuit, and the time-division multiplexed optical signal is converted into a voltage signal. It is characterized by discriminating and outputting each bit rate group or bit rate concerned.
According to a fourth aspect of the present invention, in the optical signal receiving discrimination circuit according to the third aspect, a parallel feedback parallel injection type amplifier circuit is used as the impedance conversion amplifier circuit, and the parallel feedback resistance of the parallel feedback parallel injection type amplifier circuit is reduced. The resistance value is a variable resistance that can be controlled by the bit rate control signal.
According to a fifth aspect of the present invention, in the optical signal receiving discrimination circuit according to the third aspect, a band is controlled by a bit rate control signal between the output terminal of the impedance conversion amplifier circuit and the input terminal of the post-amplifier circuit. A possible band variable low-pass filter circuit is inserted.
An optical signal receiving and discriminating circuit according to a sixth aspect of the present invention provides an optical / electrical conversion element for optical signals obtained by time-division-multiplexing a plurality of bit rate signals, all or a part of which are not integral multiples or a fraction of an integer. The current signal is converted into a voltage signal by an impedance conversion amplifier circuit, amplified to a voltage signal having a constant amplitude by a post-amplifier circuit, and then identified and reproduced by a clock / data recovery circuit. An optical signal reception discriminating circuit having a plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate having a relation of an integral multiple or a fraction of an integer as the post-amplifier circuit The output signal of the impedance conversion amplifier circuit is distributed to all the post-amplifier circuits, and the output signals of the plurality of post-amplifier circuits are identified by the corresponding clock / data recovery circuits. For each bit rate group or bit rate that is in an integral multiple or a fraction of an integer, or an input terminal portion or an internal portion of the post-amplifier circuit, or an input terminal portion of the clock / data recovery circuit, or A gate circuit is provided inside, and the opening and closing of the gate circuit is controlled by a bit rate control signal, thereby converting the time-division multiplexed optical signal into a voltage signal, and a bit having an integer multiple or a fraction of an integer relationship. Discriminating and outputting for each rate group or bit rate.
An optical signal receiving and discriminating circuit according to a seventh aspect of the present invention provides an optical / electrical conversion element comprising an optical signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer. The current signal is converted into a voltage signal by an impedance conversion amplifier circuit, amplified to a voltage signal having a constant amplitude by a post-amplifier circuit, and then identified and reproduced by a clock / data recovery circuit. An optical signal reception discriminating circuit having a plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate having a relation of an integral multiple or a fraction of an integer. A path switching circuit is connected between the output terminal and the input terminals of all the post-amplifier circuits, and the output signals of the plurality of post-amplifier circuits are respectively associated with clock / data recovery circuits. In addition to reproducing separately, the route switching circuit is controlled by a bit rate control signal to convert the time-division multiplexed optical signal into a voltage signal, and a hit rate group having an integer multiple or a fraction of an integer relationship It is characterized in that the output is discriminated at every bit rate or every bit rate.
The invention according to claim 8 is the optical signal reception discriminating circuit according to claim 6, wherein the output terminal of the impedance conversion amplifier circuit and the input terminal of at least one post-amplifier circuit among the plurality of post-amplifier circuits. Between the two, a low-pass filter circuit or a band-variable low-pass filter circuit whose band can be controlled by a bit rate control signal is inserted.
The invention according to claim 9 is the optical signal reception discriminating circuit according to claim 7, wherein an output terminal of the route switching circuit and an input terminal of at least one post-amplifier circuit among the plurality of post-amplifier circuits. Between the two, a low-pass filter circuit or a band-variable low-pass filter circuit whose band can be controlled by a bit rate control signal is inserted.

  According to the present invention, a clock / data recovery circuit is provided for each bit rate group or for each bit rate having an integer multiple or a fraction of an integer, so that one clock / data recovery circuit includes a plurality of oscillation circuits. It is possible to suppress interference between the oscillation circuits, which becomes a problem when it is provided. Also, the bit rate equal to or a fraction of an integer of the oscillation frequency of the clock recovery circuit included in each clock / data recovery circuit can be selected by opening / closing the gate circuit provided in the input terminal section or switching the route switching circuit. Can be output from each output terminal for each bit rate group or bit rate having a relation of an integer multiple or a fraction of an integer. A function for handling a plurality of bit rates not having an integer multiple or a fraction of an integer is not required.

<Example 1>
FIG. 1 shows a signal discrimination circuit according to the first embodiment of the present invention. In the figure, 1 is a signal input terminal, 2 is a first signal output terminal, 3 is a second signal output terminal, 4 is a third signal output terminal, and 5 is a first clock / data recovery circuit (CDR circuit). , 6 is a second clock and data recovery circuit, 7 is a third clock and data recovery circuit, 8 is a first bit rate control signal input terminal, 9 is a second bit rate control signal input terminal, and 10 is a first bit rate control signal input terminal. 3 is a bit rate control signal input terminal, 11 is a first gate circuit, 12 is a second gate circuit, and 13 is a third gate circuit. The clock / data recovery circuits 5, 6, and 7 are provided for each bit rate group or each bit rate having an integer multiple or a fraction of an integer.

  The bit rate switching timing of the signal input to all the signal discriminating circuits of the present invention (or an optical signal receiving discriminating circuit which will be described later using the signal discriminating circuit) is a control for controlling the transmission timing of the circuit that transmits the signal. It is assumed that it is given as a bit rate control signal from a circuit or a bit rate determination means provided separately.

  As is clear from the present embodiment, the signal discrimination circuit of the present invention has clock / data recovery circuits 5, 6, and 7 for each bit rate group or bit rate that have an integer multiple or a fraction of an integer. Therefore, it is easy to suppress the interference between the oscillation circuits, which is a problem when one clock / data recovery circuit has a plurality of oscillation circuits.

  Further, by selecting the opening and closing of the gate circuits 11, 12, 13 provided on the input terminal 1 side, the oscillation frequency of the clock recovery circuit included in each clock / data recovery circuit 5, 6, 7 is the same. Alternatively, only a signal with a bit rate of 1 / integer can be identified and reproduced, and each output terminal 2, 3, 4 for each bit rate group or bit rate having an integer multiple or 1 / integer relationship. Therefore, the circuit and device in the subsequent stage do not need a function for handling a plurality of bit rates not having an integer multiple or a fraction of an integer relationship.

<Example 2>
FIG. 2 shows a signal discrimination circuit according to the second embodiment of the present invention. The same components as those in Example 1 are denoted by the same reference numerals. Reference numeral 5A denotes a first clock / data recovery circuit with a built-in gate circuit, 5B denotes a second clock / data recovery circuit with a built-in gate circuit, and 5C denotes a third clock / data recovery circuit with a built-in gate circuit.

  The present embodiment is an example in which the gate circuits 11, 12, 13 of the first embodiment are provided in the clock / data recovery circuits 5, 6, 7 and the bit rate control signal input terminals 8, 9, 10 are connected to the clock It is directly provided in the data reproduction circuits 5A, 6A, 7A. Since the function is not different from that of the first embodiment, the same effect can be obtained.

<Example 3>
FIG. 3 shows a signal discrimination circuit according to the third embodiment of the present invention. The same components as those in Example 1 are denoted by the same reference numerals. Reference numeral 17 denotes a route switching circuit. In the first embodiment, the opening / closing of the gate circuits 11, 12, 13 is selected, and in the second embodiment, the opening / closing of the gate circuits in the built-in clock / data recovery circuits 5A, 6A, 7A is selected. In this embodiment, the function of recognizing and reproducing only a signal having a bit rate equal to or a fraction of an integer of the oscillation frequency of the clock recovery circuit included in each clock / data recovery circuit is realized. The same function is provided by transmitting the signal only to the clock / data recovery circuit corresponding to the bit rate of the input signal using the switch of the switching circuit 17.

  In the present embodiment, the loss of signal power due to the distribution can be suppressed by using the path switching circuit 17 having a small insertion loss compared to the case of distributing the signal as in the first and second embodiments. The identification sensitivity of the data reproduction circuit can be increased.

<Example 4>
FIG. 4 shows an optical signal receiving discrimination circuit according to the fourth embodiment of the present invention. The same components as those in Example 1 are denoted by the same reference numerals. Reference numeral 18 denotes a photoelectric conversion element, 19 denotes an impedance conversion amplifier circuit, 20 denotes a post-amplifier circuit, 21 denotes a signal discrimination circuit described with reference to FIG. 1, and 22 denotes a power source or ground.

  The present embodiment is an example in which the signal discrimination circuit shown in the first embodiment is applied to an optical signal reception discrimination circuit, and can receive and discriminate an optical signal obtained by time-division multiplexing a plurality of bit rate signals.

  In the present embodiment, the configuration of the first embodiment is used for the signal discriminating circuit 21, but the same effect can be obtained by using any of the signal discriminating circuits of the first, second, and third embodiments. Further, although the parallel feedback parallel injection type amplifier circuit is used for the impedance conversion amplifier circuit 19, the same applies to any circuit as long as it has a function of converting and amplifying the output current signal of the photoelectric conversion element 18 into a voltage signal. The effect is obtained.

<Example 5>
FIG. 5 shows an optical signal receiving discrimination circuit according to the fifth embodiment of the present invention. The same components as those in Example 4 are denoted by the same reference numerals. In the figure, reference numeral 23 denotes a variable resistor, and 24 denotes a resistance value control terminal. In literature (T. Yoshida et al., "New 156M / 2.5Gbit / s multi-rate SPF transceiver with automatic sensitivity switching", The 10th Optolectronics and Communications Conference (OECC2005), Jul. 2005, paper 6B4-3.) As described above, when the configuration of the parallel feedback parallel injection type amplifier circuit is used for the impedance conversion amplifier circuit, the light receiving sensitivity of the optical receiver changes when the value of the feedback resistor is changed. The greater the feedback resistance, the better the light receiving sensitivity, but at the same time the circuit bandwidth decreases.

  In order to equalize and amplify the signal, a band of bit rate x 0.7 Hz or more is required. Therefore, if the value of the feedback resistor can be optimized in accordance with the bit rate, the light receiving sensitivity can be optimized for each bit rate. it can. In this embodiment, the variable feedback resistor 23 is used as the parallel feedback resistor, and the value can be changed by inputting the control signal to the resistance value control terminal 24. Therefore, the light receiving sensitivity is optimized according to the bit rate of the received optical signal. Can be made.

  In FIG. 5, the configuration of the first embodiment is used for the signal discrimination circuit 21 as in FIG. 4, but the same effect can be obtained by using any of the signal discrimination circuits of the first, second, and third embodiments. .

<Example 6>
FIG. 6 shows an optical signal receiving discrimination circuit according to a sixth embodiment of the present invention. The same components as those in Example 4 are denoted by the same reference numerals. Reference numeral 25 denotes a band variable low-pass filter circuit, and 26 denotes a band control terminal. In this embodiment, instead of changing the feedback resistance of the impedance conversion amplifier circuit 19, a band-variable low-pass filter circuit 25 is inserted between the impedance conversion amplifier circuit 19 and the post-amplifier circuit 20, and a bit is connected to the band control terminal 26. By inputting the rate control signal, the noise band is optimized for each bit rate, so that a certain light receiving sensitivity improvement effect can be obtained.

<Example 7>
FIG. 7 shows an optical signal receiving discrimination circuit according to the seventh embodiment of the present invention. The same components as those in Example 4 are denoted by the same reference numerals. Reference numeral 27 denotes a first post-amplifier circuit, 28 denotes a second post-amplifier circuit, and 29 denotes a third post-amplifier circuit. In the present embodiment, signal distribution is performed in the subsequent stage of the impedance conversion amplifier circuit 19, and the same effects as those of the fourth embodiment can be obtained in terms of function. Further, the post-amplifier circuits 27, 28, and 29 operate on the signal having the highest bit rate among the bit rates handled by the clock / data recovery circuits 5, 6, and 7 connected to the subsequent stage of the post-amplifier circuits. In the case of having an optimized band, the light receiving sensitivity optimized for each bit rate group can be obtained.

<Example 8>
FIG. 8 shows an optical signal receiving discrimination circuit according to the eighth embodiment of the present invention. The same components as those in Example 7 are denoted by the same reference numerals. As is apparent from the figure, in the example in which the positions of the gate circuits 11, 12, and 13 that realize the discrimination function are provided between the post-amplifier circuits 27, 28, and 29 and the clock / data recovery circuits 5, 6, and 7, respectively. Yes, the same effect as in Example 7 can be obtained.

<Example 9>
FIG. 9 shows an optical signal receiving discrimination circuit according to the ninth embodiment of the present invention. The same components as those in Example 7 are denoted by the same reference numerals. This embodiment is an example in which a gate circuit that realizes a discrimination function is provided in the post-amplifier circuit, and the bit rate control signal input terminals 8, 9, and 10 have post-amplifier circuits 27A, 28A, and 29A with built-in gate circuits. Is provided directly. Also in this embodiment, the same effects as those of Embodiments 7 and 8 can be obtained.

<Example 10>
FIG. 10 shows an optical signal receiving discrimination circuit according to the tenth embodiment of the present invention. The same components as those in Example 7 are denoted by the same reference numerals. The present embodiment is an example in which a gate circuit for realizing a discrimination function is provided in the clock / data recovery circuit, and the bit rate control signal input terminals 8, 9, and 10 are provided with the clock / data recovery circuits 5A and 6A with a built-in gate circuit. , 7A. In this embodiment, the same effects as those of Embodiments 7, 8, and 9 can be obtained.

<Example 11>
FIG. 11 shows an optical signal receiving discrimination circuit according to the eleventh embodiment of the present invention. The same reference numerals are assigned to the same components as those in the third and seventh embodiments. The present embodiment is an example in which the signal discrimination function of the seventh to tenth embodiments is realized by using the route switching circuit 17 as in the third embodiment. In the present embodiment, the same effects as those of the third embodiment with respect to the first and second embodiments can be obtained with respect to the seventh to tenth embodiments.

<Example 12>
FIG. 12 shows an optical signal receiving discrimination circuit according to the twelfth embodiment of the present invention. The same components as those in Example 6 and Example 7 are denoted by the same reference numerals. In this embodiment, a variable band low-pass filter circuit 25 is inserted at the head of the branch circuit including the first post-amplifier circuit 27.

  When this branch circuit handles not only the same bit rate as the oscillation frequency of the clock recovery circuit included in the first clock / data recovery circuit 5, but also a bit rate of 1 / integer, bandwidth control is performed according to the bit rate. By inputting a bit rate control signal to the terminal 26, it is possible to optimize the noise band for each bit rate, so that an effect of improving the light receiving sensitivity can be obtained.

  In this embodiment, for convenience, the example using the band variable low-pass filter circuit 25 is shown. However, when a post-amplifier circuit having a wide band must be used, a fixed low-pass filter circuit is used. By using and optimizing the band, the same effects as those of Examples 7 to 10 can be obtained. Further, in this embodiment, an example in which the low-pass filter circuit is inserted before the gate circuit is shown. However, the same effect can be obtained even when the gate circuit is subsequent to the post-amplifier circuit. . Further, in this embodiment, for the sake of convenience, an example in which a filter circuit is inserted into the branch circuit including the first post-amplifier circuit 27 is shown, but it may be provided in a plurality of branch circuits or in all branch circuits. Also good. In the present embodiment, an example in which a filter circuit is inserted on the basis of the seventh embodiment has been described. However, the same effect can be obtained when applied to any of the seventh to tenth embodiments.

<Example 13>
FIG. 13 shows an optical signal receiving discrimination circuit according to the thirteenth embodiment of the present invention. The same reference numerals are assigned to the same components as those in Example 11 and Example 12. The present embodiment is an example in which the signal discrimination function of the twelfth embodiment is realized by using the route switching circuit 17 as in the third embodiment, and the same effect as the third embodiment with respect to the first and second embodiments is obtained. 12 is obtained.

  In the present embodiment, an example using the band variable low-pass filter circuit 25 is shown for convenience, but when a post-amplifier circuit having a wide band must be used, a fixed low-pass filter circuit is used. By optimizing the bandwidth, the same effect as in the eleventh embodiment can be obtained. Further, in this embodiment, for the sake of convenience, an example in which a filter circuit is inserted into the branch circuit including the first post-amplifier circuit has been shown. However, the filter circuit may be provided in a plurality of branch circuits or in all branch circuits. good.

<Other embodiments>
In the above embodiment, an example in which three clock / data recovery circuits 5, 6, and 7 (or 5A, 6A, and 7A) are provided for convenience is shown. It is only necessary to have the same number of clock data recovery circuits as the number of rate groups or types of bit rates. Further, although the signal connection is shown by a single-end type notation, the same effect can be obtained even if all or a part of the signal connection is a differential type connection. In the embodiments of FIGS. 1, 2, 4, 5, 6, 7, 8, 9, 10, and 12, the branching portion is shown as a branch of connection for convenience, but the same applies even if distribution is performed using a distribution circuit or other distribution means. The effect is obtained. Furthermore, all the gate circuits used in the embodiments of the present invention do not depend on internal materials or circuit configurations as long as they have a function of passing or blocking signals according to control signals.

  As described above, as in the present embodiment, one clock / data recovery circuit is provided by having a clock / data recovery circuit for each bit rate group or each bit rate having an integer multiple or a fraction of an integer relationship. Interference between oscillation circuits, which is a problem when the circuit has a plurality of oscillation circuits, can be suppressed, and each clock and data can be regenerated by selecting the open / close of the gate circuit provided at the input terminal or switching the route switching circuit. Only a signal having a bit rate equal to or a fraction of an integer of the oscillation frequency of the clock regeneration circuit included in the circuit can be identified and reproduced, and each bit rate group having an integer multiple or a fraction of an integer relationship or Since each bit rate can be output from an individual output terminal, the subsequent circuits and devices have an integral multiple or a fraction of an integer. It does not require the ability to handle multiple bit rates no relationship.

It is a block diagram of the signal discrimination circuit of Example 1 of this invention. It is a block diagram of the signal discrimination circuit of Example 2 of the present invention. It is a block diagram of the signal discrimination circuit of Example 3 of the present invention. It is a block diagram of the optical signal reception discrimination circuit of Example 4 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 5 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 6 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 7 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 8 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 9 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 10 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 11 of this invention. It is a block diagram of the optical signal reception discrimination circuit of Example 12 of this invention. It is a block diagram of the optical signal receiving discrimination circuit of Example 13 of this invention.

Explanation of symbols

1: Signal input terminal 2, 3, 4: Signal output terminal 5, 6, 7: Clock / data recovery circuit 5A, 6A, 7A: Clock / data recovery circuit with built-in gate circuit 8-10: Bit rate control signal input terminal 11 , 12, 13: Gate circuit 17: Path switching circuit 18: Photoelectric conversion element 19: Impedance conversion amplifier circuit 20: Post-amplifier circuit 21: Signal discrimination circuit 22: Power supply or ground 23: Variable resistor 24: Resistance control Control terminal 25: Band variable low-pass filter circuit 26: Band control terminal 27, 28, 29: Post-amplifier circuit 27A, 28A, 29A: Post-amplifier circuit with built-in gate circuit

Claims (9)

A signal discriminating circuit for discriminating and regenerating a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer,
A clock / data recovery circuit corresponding to each bit rate group or each bit rate having a relation of an integer multiple or a fraction of an integer,
Distributing the time-division multiplexed signal to all clock and data recovery circuits;
A gate circuit is provided inside or inside the clock / data recovery circuit, and the gate circuit is controlled by a bit rate control signal so that the time-division multiplexed signal is an integer multiple or a fraction of an integer. A signal discriminating circuit that discriminates and outputs each bit rate group or each bit rate in the relationship of A signal discriminating circuit for discriminating and regenerating a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer,
A clock / data recovery circuit corresponding to each bit rate group or each bit rate having a relation of an integer multiple or a fraction of an integer,
A route switching circuit is connected between one signal input terminal and input terminals of all the clock / data recovery circuits,
By controlling the route switching circuit with a bit rate control signal, the time-division multiplexed signal is discriminated and output for each bit rate group or bit rate having an integer multiple or a fraction of an integer relationship. A signal discrimination circuit characterized by that. An optical signal obtained by time-division-multiplexing a plurality of bit rate signals is converted into a current signal using a photoelectric conversion element, and the current signal is converted and amplified into a voltage signal by an impedance conversion amplifier circuit. An optical signal reception discriminating circuit for performing identification and reproduction by a clock and data reproduction circuit after being amplified to a voltage signal having a constant amplitude using,
A signal discriminating circuit according to claim 1 or 2 is provided instead of the clock and data recovery circuit, and the time-division multiplexed optical signal is converted into a voltage signal. An optical signal reception discriminating circuit which discriminates and outputs each bit rate group or bit rate concerned. In the optical signal reception discrimination circuit according to claim 3,
A parallel feedback parallel injection amplifier circuit is used as the impedance conversion amplifier circuit, and the resistance value of the parallel feedback resistor of the parallel feedback parallel injection amplifier circuit is a variable resistor that can be controlled by the bit rate control signal. Optical signal reception discrimination circuit. In the optical signal reception discrimination circuit according to claim 3,
An optical signal receiving discrimination characterized in that a band-variable low-pass filter circuit capable of controlling a band by a bit rate control signal is inserted between an output terminal of the impedance conversion amplifier circuit and an input terminal of the post-amplifier circuit. circuit. An optical signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which is not an integer multiple or a fraction of an integer, is converted into a current signal using a photoelectric conversion element, and the current signal is converted into an impedance. An optical signal reception discriminating circuit that converts and amplifies to a voltage signal by a conversion amplifier circuit, amplifies it to a voltage signal having a constant amplitude using a post-amplifier circuit, and performs identification and reproduction by a clock and data recovery circuit,
The post-amplifier circuit has a plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate in the integer multiple or a fraction of an integer,
Distributing the output signal of the impedance conversion amplifier circuit to all the post-amplifier circuits;
The output signals of the plurality of post-amplifier circuits are discriminated and reproduced by corresponding clock / data reproduction circuits, and the post-position is provided for each bit rate group or bit rate having a relation of the integral multiple or the integral fraction. A gate circuit is provided in the input terminal part or inside of the amplifier circuit, or in the input terminal part or inside of the clock / data recovery circuit,
By controlling the opening and closing of the gate circuit with a bit rate control signal, the time-division multiplexed optical signal is converted into a voltage signal, and each bit rate group or bit rate having an integer multiple or a fraction of an integer relationship. And an optical signal receiving discrimination circuit characterized in that the discrimination signal is outputted after discrimination. An optical signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which is not an integer multiple or a fraction of an integer, is converted into a current signal using a photoelectric conversion element, and the current signal is converted into an impedance. An optical signal reception discriminating circuit that converts and amplifies to a voltage signal by a conversion amplifier circuit, amplifies it to a voltage signal having a constant amplitude using a post-amplifier circuit, and performs identification and reproduction by a clock and data recovery circuit,
A plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate in a relation of the integer multiple or a fraction of an integer,
A path switching circuit is connected between the output terminal of the impedance conversion amplifier circuit and the input terminals of all the post-amplifier circuits,
The output signals of the plurality of post-amplifier circuits are discriminated and reproduced by corresponding clock / data reproduction circuits, and the route switching circuit is controlled by a bit rate control signal, whereby the time-division multiplexed optical signal is converted. An optical signal reception discriminating circuit which converts to a voltage signal and discriminates and outputs it for each hit rate group or bit rate which have an integer multiple or a fraction of an integer relationship. In the optical signal reception discrimination circuit according to claim 6,
A band can be controlled by a low-pass filter circuit or a bit rate control signal between an output terminal of the impedance conversion amplifier circuit and an input terminal of at least one of the plurality of post-amplifier circuits. An optical signal reception discriminating circuit, wherein a band-variable low-pass filter circuit is inserted. The optical signal reception discrimination circuit according to claim 7,
A band can be controlled by a low-pass filter circuit or a bit rate control signal between the output terminal of the route switching circuit and the input terminal of at least one post-amplifier circuit among the plurality of post-amplifier circuits. An optical signal reception discriminating circuit, wherein a band-variable low-pass filter circuit is inserted.

Images