JP4850785B2 - Variable gain circuit - Google Patents

Description

  The present invention relates to a variable gain circuit, and more particularly to a variable gain circuit including a variable gain amplifier having a multi-stage connection with a wide variable gain range, low signal distortion, and low power consumption.

  As an example of a multistage variable gain circuit, a circuit configuration shown in FIG. 8 is known. FIG. 8 shows a circuit configuration of a variable gain circuit using a conventional multistage variable gain amplifier, which is described in Non-Patent Document 1, “Jitter Considerations in the Design of a 10-Gb / s Automatic Gain Control Amplifier”, IEEE. Transactions on Microwave Theory and Techniques, vol. 53, no. 2, (2005), FIG.

  In FIG. 8, Vin is a differential input signal voltage, Vout is a differential output signal voltage, Input Stage is an input stage, and VGA1 to VGA3 are each a variable gain amplifier that variably amplifies the gain of the differential input signal. , VGC1 to VGC3 are gain control voltages for controlling the gains of the variable gain amplifiers VGA1 to VGA3. AGC is a gain control voltage VGC1 to VGC3 corresponding to the monitoring result of the voltage level of the differential output signal voltage Vout. An automatic gain controller (Automatic Gain Controller) and DC Offset Cancellation output to each of the VGAs 1 to 3 are DC voltage offset cancelers.

  The gain variable circuit 10C in FIG. 8 is configured as a multistage variable gain amplifier, in which variable gain amplifiers VGA1 to VGA1 are connected in series in three stages.

  The operation of the variable gain circuit 10C in FIG. 8 will be described. The automatic gain adjuster AGC monitors the amplitude | Vout | of the differential output signal voltage Vout and detects a difference from a target amplitude | Vout | set in advance in the automatic gain adjuster AGC. Hereinafter, the amplitude | Vout | of the monitored differential output signal voltage is expressed as Vout, m, and the amplitude | Vout | of the target differential output signal voltage is expressed as Vout, g. Next, the gain control voltages VGC1 to VGC1 to V3 are generated so as to set the difference (Vout, m−Vout, g) from the detected target to “0” and output to each of the variable gain amplifiers VGA1 to VGA1. With the gain control voltages VGC1 to VGC3, the gains of the variable gain amplifiers VGA1 to VGA3 are adjusted so that the difference (Vout, m−Vout, g) becomes “0”, and the monitored terminal, that is, the output of the gain variable circuit 10C The target amplitude Vout, g can be obtained at the terminal.

In the conventional example of Non-Patent Document 1, the gains of the three variable gain amplifiers VGA1 to VGA1 are not controlled so that the gains of the three variable gain amplifiers VGA1 to VGA1 are equal to each other. ) To G (VGA3) G (VGA1) ≧ G (VGA2) ≧ G (VGA3)
Is controlled by the automatic gain adjuster AGC so as to increase in this order, that is, as it becomes closer to the input signal terminal side of the differential input signal voltage Vin. This is because the closer to the input signal terminal side, the higher the noise characteristic can be improved by keeping the gain of the variable gain amplifier VGA high. Further, the DC voltage offset canceller is added so that the gain of the variable gain circuit 10C is not reduced by the DC voltage offset of the input differential signal voltage Vin.
Daniel Kucharski et al .; “Jitter Considerations in the Design of a 10-Gb / s Automatic Gain Control Amplifier”, IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 2, (2005), pp. 590-597

However, as in the case of the conventional example of FIG. 8, the gain variable amplifier VGA closer to the input signal terminal side of the differential input signal voltage Vin is
G (VGA1) ≧ G (VGA2) ≧ G (VGA3)
Since the gain is adjusted high, the signal amplitude of the output signal increases in the variable gain amplifier VGA close to the input signal terminal side, and the subsequent variable gain amplifier VGA following the subsequent stage is driven with a large signal amplitude. The Rukoto. In general, the variable gain amplifier VGA driven with a large signal amplitude is likely to cause distortion in the output signal. As a result, the differential output signal Vout of the variable gain circuit in which the variable gain amplifier VGA is connected in series in multiple stages has a corresponding signal. Distortion will be included.

  Since the main application destination of the conventional variable gain circuit 10C in FIG. 8 is digital optical communication in the NRZ (Non-Return-to-Zero) signal format, the signal distortion of the differential output signal Vout is allowed to some extent. (For example, odd-order harmonic distortion that accelerates the rise and fall times of the signal is allowed to some extent). However, signal distortion of the differential output signal Vout is a major issue when used in applications where input / output linearity and signal waveform reproducibility are strongly required, such as analog optical communication.

  In the conventional example of FIG. 8, the three variable gain amplifiers VGA1 to VGA3 are independently controlled using three independent gain control signal voltages VGC1 to VGC1. When such independent control is employed, the circuit configuration becomes complicated, and the chip area and the power consumption increase.

  The present invention has been made in view of the above problems, and the problem to be solved by the present invention is to provide a small gain variable circuit having a large gain variable width, a small signal distortion, and low power consumption. There is.

  The present invention has been made in order to solve the above-described problems, and is composed of the following technical means, thereby reducing signal distortion, power consumption, small size, and relatively low configuration. A gain variable circuit comprising a simple multistage variable gain amplifier is realized.

The first technical means includes a plurality of variable gain amplifiers connected in series between an input signal terminal and an output signal terminal, and a target signal amplitude based on a result of monitoring the signal amplitude of the output signal at the output signal terminal. To generate a single gain control signal and output to each of the plurality of variable gain amplifiers as a signal for adjusting the gain of each of the plurality of variable gain amplifiers. In the variable gain circuit in which the gain of each of the variable gain amplifiers sequentially increases from the input signal terminal side to the output signal terminal side, each of the variable gain amplifiers includes a first amplification transistor and one end Is connected to the collector of the first amplifying transistor, the other end is connected to the first power supply voltage terminal, and one end is connected to the first amplifying transistor. A first amplifying circuit comprising a first emitter resistor connected to the emitter of the second amplifying circuit; a second amplifying transistor having a collector connected to one end of the first collector resistor; A second amplifying resistor connected to the emitter of the first transistor, a third amplifying transistor, one end connected to the collector of the third amplifying transistor, and the other end A third amplifying circuit comprising a second collector resistor connected to the first power supply voltage terminal and a third emitter resistor having one end connected to the emitter of the third amplifying transistor; A fourth amplifying transistor connected to one end of the second collector resistor and a fourth emitter resistor having one end connected to the emitter of the fourth amplifying transistor; A collector is connected to a connection point in which an amplifier circuit unit composed of four amplifier circuits, a width circuit, and the other end of the first emitter resistor and the other end of the third emitter resistor are connected, The first gain adjusting transistor for adjusting the gain of the one amplifier circuit and the third amplifier circuit, and the other end of the second emitter resistor and the other end of the fourth emitter resistor are connected in common. A gain adjusting circuit comprising a second gain adjusting transistor for adjusting a gain of the second amplifying circuit and the fourth amplifying circuit, wherein a collector is connected to the connection point, and the first gain adjusting transistor A variable gain amplifier comprising a constant current source connected between a connection point where the emitter of the transistor and the emitter of the second gain adjusting transistor are connected in common and a second power supply voltage terminal. The first and A connection point where the positive side signal of the differential input signal is applied to a connection point where the bases of the second amplification transistors are commonly connected, and the bases of the third and fourth amplification transistors are connected in common A signal on the complementary side of the differential input signal is applied to the first and second amplifier circuits, and the third and fourth amplifier circuits are operated in a differential manner. From the connection point where the collectors of the amplifying transistors are connected in common, the complementary signal of the amplified differential output signal is output, and from the connection point where the collectors of the third and fourth amplifying transistors are connected in common Each of the plurality of variable gain amplifiers configured as a differential amplifier circuit that outputs a positive signal of the differential output signal after amplification, and connected in series between the input signal terminal and the output signal terminal In the first The resistance values of the mitter resistance and the third emitter resistance are equal to each other, the resistance values of the second emitter resistance and the fourth emitter resistance are equal to each other, and the first emitter resistance or the third emitter resistance is equal to each other. And the second emitter resistance or the fourth emitter resistance are not equal, and the first emitter resistance or the third emitter included in each of the plurality of variable gain amplifiers. Each of the resistance value of the resistor and the resistance value of the second emitter resistor or the fourth emitter resistor is gradually decreased or made equal as it proceeds from the input signal terminal side to the output signal terminal side. A positive signal of the single gain control signal that is set and output as a differential control signal from the automatic gain adjuster is transferred to the first gain adjusting transistor. By applying to the base of the second gain adjusting transistor a signal on the complementary side of the single gain control signal that is applied as a differential control signal from the automatic gain adjuster. The gain of the variable gain amplifier configured as the differential amplifier circuit is adjusted .

The second technical means includes a plurality of variable gain amplifiers connected in series between the input signal terminal and the output signal terminal, and a target signal amplitude based on a result of monitoring the signal amplitude of the output signal at the output signal terminal. To generate a single gain control signal and output to each of the plurality of variable gain amplifiers as a signal for adjusting the gain of each of the plurality of variable gain amplifiers. In the variable gain circuit in which the gain of each of the variable gain amplifiers sequentially increases from the input signal terminal side to the output signal terminal side, each of the variable gain amplifiers includes a first amplification transistor and one end Is connected to the collector of the first amplifying transistor, the other end is connected to the first power supply voltage terminal, and one end is connected to the first amplifying transistor. A first amplifying circuit comprising a first emitter resistor connected to the emitter of the second amplifying circuit; a second amplifying transistor having a collector connected to one end of the first collector resistor; A second amplifying resistor connected to the emitter of the first transistor, a third amplifying transistor, one end connected to the collector of the third amplifying transistor, and the other end A third amplifying circuit comprising a second collector resistor connected to the first power supply voltage terminal and a third emitter resistor having one end connected to the emitter of the third amplifying transistor; A fourth amplifying transistor connected to one end of the second collector resistor and a fourth emitter resistor having one end connected to the emitter of the fourth amplifying transistor; A collector is connected to a connection point in which an amplifier circuit unit composed of four amplifier circuits, a width circuit, and the other end of the first emitter resistor and the other end of the third emitter resistor are connected, The first gain adjusting transistor for adjusting the gain of the one amplifier circuit and the third amplifier circuit, and the other end of the second emitter resistor and the other end of the fourth emitter resistor are connected in common. A gain adjusting circuit comprising a second gain adjusting transistor for adjusting a gain of the second amplifying circuit and the fourth amplifying circuit, wherein a collector is connected to the connection point, and the first gain adjusting transistor A variable gain amplifier comprising a constant current source connected between a connection point where the emitter of the transistor and the emitter of the second gain adjusting transistor are connected in common and a second power supply voltage terminal. The first and A connection point where the positive side signal of the differential input signal is applied to a connection point where the bases of the second amplification transistors are commonly connected, and the bases of the third and fourth amplification transistors are connected in common A signal on the complementary side of the differential input signal is applied to the first and second amplifier circuits, and the third and fourth amplifier circuits are operated in a differential manner. From the connection point where the collectors of the amplifying transistors are connected in common, the complementary signal of the amplified differential output signal is output, and from the connection point where the collectors of the third and fourth amplifying transistors are connected in common Each of the plurality of variable gain amplifiers configured as a differential amplifier circuit that outputs a positive signal of the differential output signal after amplification, and connected in series between the input signal terminal and the output signal terminal In the first The resistance values of the mitter resistance and the third emitter resistance are equal to each other, the resistance values of the second emitter resistance and the fourth emitter resistance are equal to each other, and the first emitter resistance or the third emitter resistance is equal to each other. And the second emitter resistance or the fourth emitter resistance are not equal, and the resistance value of the first collector resistance included in each of the plurality of variable gain amplifiers, and Each of the resistance values of the second collector resistors is set so as to sequentially increase or become equal from the input signal terminal side to the output signal terminal side, and from the automatic gain adjuster as a differential control signal A signal on the positive side of the single output gain control signal is applied to the base of the first gain adjustment transistor, and a differential control signal is output from the automatic gain adjuster. By applying a complementary signal of the single gain control signal output to the base of the second gain adjusting transistor, the gain of the variable gain amplifier configured as the differential amplifier circuit is increased. It is characterized by adjusting .

The third technical means includes a plurality of variable gain amplifiers connected in series between the input signal terminal and the output signal terminal, and a target signal amplitude based on the result of monitoring the signal amplitude of the output signal at the output signal terminal. To generate a single gain control signal and output to each of the plurality of variable gain amplifiers as a signal for adjusting the gain of each of the plurality of variable gain amplifiers. In the variable gain circuit in which the gain of each of the variable gain amplifiers sequentially increases from the input signal terminal side to the output signal terminal side, each of the variable gain amplifiers includes a first amplification transistor and one end Is connected to the collector of the first amplifying transistor, the other end is connected to the first power supply voltage terminal, and one end is connected to the first amplifying transistor. A first amplifying circuit comprising a first emitter resistor connected to the emitter of the second amplifying circuit; a second amplifying transistor having a collector connected to one end of the first collector resistor; A second amplifying resistor connected to the emitter of the first transistor, a third amplifying transistor, one end connected to the collector of the third amplifying transistor, and the other end A third amplifying circuit comprising a second collector resistor connected to the first power supply voltage terminal and a third emitter resistor having one end connected to the emitter of the third amplifying transistor; A fourth amplifying transistor connected to one end of the second collector resistor and a fourth emitter resistor having one end connected to the emitter of the fourth amplifying transistor; A collector is connected to a connection point in which an amplifier circuit unit composed of four amplifier circuits, a width circuit, and the other end of the first emitter resistor and the other end of the third emitter resistor are connected, The first gain adjusting transistor for adjusting the gain of the one amplifier circuit and the third amplifier circuit, and the other end of the second emitter resistor and the other end of the fourth emitter resistor are connected in common. A gain adjusting circuit comprising a second gain adjusting transistor for adjusting a gain of the second amplifying circuit and the fourth amplifying circuit, wherein a collector is connected to the connection point, and the first gain adjusting transistor and a first second end of the gain adjustment emitter resistor one end to the emitter of the other end and the second gain adjustment transistor of the gain adjustment emitter resistor is connected to one end to the emitter of the transistor is connected Common connection point A variable gain amplifier including a constant current source connected between the second power supply voltage terminal , wherein the bases of the first and second amplifying transistors are connected in common Apply a signal on the positive side of the differential input signal to the point, and apply a signal on the complementary side of the differential input signal to the connection point where the bases of the third and fourth amplification transistors are connected in common. The first and second amplifying circuits and the third and fourth amplifying circuits are differentially operated to amplify from a connection point where the collectors of the first and second amplifying transistors are connected in common. A complementary signal of the subsequent differential output signal is output, and a positive signal of the amplified differential output signal is output from a connection point where collectors of the third and fourth amplification transistors are connected in common. Configured as a differential amplifier circuit, and In each of the plurality of variable gain amplifiers connected in series between the input signal terminal and the output signal terminal, the resistance values of the first emitter resistor and the third emitter resistor are equal, and the first The resistance values of the second emitter resistance and the fourth emitter resistance are equal, and the first emitter resistance or the third emitter resistance and the second emitter resistance or the fourth emitter resistance The resistance values are not equal, the resistance values of the first gain adjusting emitter resistor and the second gain adjusting emitter resistor included in each of the variable gain amplifiers are equal, and a plurality of the gains are included. Each of the resistance value of the first gain adjusting emitter resistor and the resistance value of the second gain adjusting emitter resistor included in each variable amplifier is set from the input signal terminal side. The signal on the positive side of the single gain control signal set as a differential control signal, which is set so as to increase sequentially as it goes to the force signal terminal side, is used for the first gain adjustment. By applying to the base of the second gain adjusting transistor a signal on the complementary side of the single gain control signal that is applied to the base of the transistor and output as a differential control signal from the automatic gain adjuster. The gain of the variable gain amplifier configured as the differential amplifier circuit is adjusted .

According to a fourth technical means, in the gain variable circuit according to any one of the first to third technical means, the first to fourth amplifying transistors, the first and second gain adjusting transistors are provided. It is either a bipolar transistor or a field effect transistor.

  According to the variable gain circuit of the present invention, since a variable gain amplifier closer to the input signal terminal side in a configuration in which a plurality of variable gain amplifiers are connected in series in multiple stages, a configuration in which the gain is controlled to be smaller is adopted. An effect like this can be achieved.

  First, it is possible to realize a variable gain circuit with a simple configuration in which multiple stages are connected in series, with little signal distortion and a large gain variable width.

  Furthermore, it is possible to realize a gain variable circuit having a simple configuration in which multiple stages are connected in series, having little signal distortion, a large gain variable width, and good noise characteristics when the input signal is small. .

  An exemplary embodiment of a variable gain circuit according to the present invention will be described below in detail with reference to the drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, the main features of the variable gain circuit of the present invention will be described first. The present invention relates to a variable gain circuit composed of variable gain amplifiers connected in series in multiple stages, and adjusts the gain of the variable gain amplifier on the output signal terminal side to increase its gain sequentially than the input signal terminal side. By having such characteristics, not only the signal distortion is small and the gain variable width is large, but also an effect that a small gain variable circuit with low power consumption can be realized.

(First embodiment)
First, the block configuration in the first embodiment of the variable gain circuit according to the present invention will be described with reference to FIG. In FIG. 1, each of VGA1 and VGA2 is a variable gain amplifier that variably amplifies the gain of the differential input signal, and AGC is a gain control voltage corresponding to the monitoring result of the voltage level of the differential output signal voltage Vout. This is an automatic gain controller for output. In is an input signal terminal of the variable gain amplifier VGA1, Out1 is an output signal terminal of the variable gain amplifier VGA1 and an input signal terminal of the variable gain amplifier VGA2, and Out2 is an output signal terminal of the variable gain amplifier VGA2.

  The gain variable circuit 10 of this embodiment shown in FIG. 1 has two stages of variable gain amplifiers VGA1 and 2 connected in series, and the automatic gain adjuster AGC has the amplitude of the output voltage of the second stage variable gain amplifier VGA2. The gains of the two variable gain amplifiers VGA1 and VGA2 are controlled by a single gain control voltage VGC.

The internal circuit constants of the variable gain amplifiers VGA1 and VGA2 are set in advance so that the two variable gain amplifiers VGA1 and VGA2 have different gains. The gains G (VGA1) and G (VGA3) of the variable gain amplifiers VGA1 and VGA2 are In any gain control voltage VGC, the gain G (VGA1) of the first-stage variable gain amplifier VGA1 on the input signal terminal In side is smaller than the second-stage variable gain amplifier VGA2, that is,
G (VGA1) <G (VGA2)
Is set to maintain the relationship.

  Note that the “gain” described below includes a negative gain, that is, a loss. When the gain is negative, the gain relationship is G (VGA1) <G (VGA2). This means that the loss of the first-stage variable gain amplifier VGA1 is smaller than that of the second-stage variable gain amplifier VGA2. It means that it is bigger than the loss.

  Next, the operation of the variable gain circuit 10 of this embodiment shown in FIG. 1 will be described using the level diagram of FIG. 2 shows the input signal terminal In of the first-stage variable gain amplifier VGA1, the output signal terminal Out1 of the first-stage variable gain amplifier VGA1, and the second-stage variable gain amplifier VGA2 in the variable gain circuit 10. The voltage amplitude level at each of the output signal terminals Out2 is illustrated. In FIG. 2, the broken line is a level diagram of the gain variable circuit in the conventional example as shown in FIG. 8, and the solid line is the level of the gain variable circuit 10 of this embodiment. The diagram is shown. In the case of an input amplitude 1 whose amplitude level is smaller than the target output amplitude, a case where the gain variable circuit performs an amplification operation with a positive gain is shown. In the case of an input amplitude 2 whose amplitude level is larger than the target output amplitude, This shows a case where the variable gain circuit performs a loss operation with a negative gain.

Here, as described with reference to FIG. 8, the gain variable circuit of the conventional example has a larger gain as the gain variable amplifier VGA is closer to the input terminal In in order to improve noise characteristics (in the case of a negative gain, This shows a case where the gain is set such that the gain variable amplifier VGA closer to the input terminal In has a smaller loss. That is, in the variable gain circuit having a two-stage configuration, in contrast to the case of the variable gain circuit 10 of the present embodiment, at any gain control voltage,
G (VGA1)> G (VGA2)
The gain is set so that

  Therefore, the level diagram in the conventional gain variable circuit is as shown by the broken line in FIG. 2. In the case of a positive gain, the first-stage variable gain amplifier VGA1 has a large gain with respect to the input signal. Is amplified, the voltage amplitude at the output signal terminal OUT1 of the first-stage variable gain amplifier VGA1 is large, and the large-amplitude signal is input to drive the second-stage variable gain amplifier VGA2. The second-stage variable gain amplifier VGA2 performs amplification with a smaller gain than the first-stage variable gain amplifier VGA1, and outputs a target output at the output signal terminal OUT2 of the second-stage variable gain amplifier VGA2. Reach the amplitude.

  In general, when the variable gain amplifier VGA is driven with a large amplitude, signal distortion is likely to occur. In the conventional variable gain circuit, the gain of the second stage from the output signal terminal OUT1 of the first stage variable gain amplifier VGA1. Large distortion tends to occur in the process of reaching the output signal terminal OUT2 of the variable amplifier VGA2.

On the other hand, in the case of the variable gain circuit 10 of the present embodiment shown in FIG. 1, as described above, the gains G (VGA1) and G (VGA2) of the first and second-stage gain variable amplifiers VGA1 and VGA2 respectively. At any gain control voltage VGC
G (VGA1) <G (VGA2)
Therefore, the level diagram is shown by a solid line in FIG. 2, and in the case of a positive gain, the output signal terminal OUT1 of the first stage variable gain amplifier VGA1 has a large amplitude as in the conventional example. Therefore, the second stage variable gain amplifier VGA2 is driven by the relatively small amplitude signal. The second-stage variable gain amplifier VGA2 performs amplification with a gain larger than that of the first-stage variable gain amplifier VGA1, and a target output amplitude at the output signal terminal OUT2 of the second-stage variable gain amplifier VGA2. To reach.

  That is, in the case of the variable gain circuit 10 of the present embodiment shown in FIG. 1, unlike the conventional variable gain circuit, the second stage variable gain amplifier VGA2 is not driven with a large amplitude. Can be suppressed. Furthermore, since the gain of the second-stage variable gain amplifier VGA2 is large, the input capacitance in anticipation of the input side of the second-stage variable gain amplifier VGA2 from the output side of the first-stage variable gain amplifier VGA1 is large. It can be increased by the mirror effect, and unnecessary high frequency gain can be reduced. As a result, harmonic distortion can be suppressed.

  Note that the noise characteristic in the case of the variable gain circuit 10 of the present embodiment shown in FIG. 1 is worse than that of the conventional variable gain circuit. However, as long as a signal-to-noise ratio (Signal-to-Noise Ratio) is sufficiently ensured until reaching the variable gain circuit 10 of the present embodiment, the variable gain circuit 10 of the present embodiment. Deterioration can be suppressed to a negligible level.

  In the above description, the case of the two-stage configuration of the first and second stage variable gain amplifiers VGA1 and VGA2 has been described. However, the present invention is not limited to such a case, and two or more stages are provided. Even in the case of a variable gain circuit configured by connecting a plurality of variable gain amplifiers VGA in series in multiple stages, the same is true, and as the closer to the output signal terminal side from the input signal terminal side, the multiple gain variable What is necessary is just to comprise so that the gain of amplifier VGA may increase sequentially.

(Second embodiment)
Next, a specific circuit configuration example of the variable gain circuit according to the present invention will be described as a second embodiment with reference to FIG. Note that the variable gain circuit 10A of this embodiment shown in FIG. 3 includes a first amplifier circuit unit 15a having two differential pairs, a first gain adjustment circuit 16a, and a first constant current source 17a. The second stage comprising the first stage variable gain amplifier VGA1, the second amplifier circuit section 25a having two differential pairs, the second gain adjusting circuit 26a, and the second constant current source 27a. An automatic gain adjuster AGC that outputs a gain control voltage corresponding to the result of monitoring the voltage level of the differential output signal of the second-stage variable gain amplifier VGA2 is provided in series with the variable gain amplifier VGA2. .

In FIG. 3, reference numeral xt ×× (×× indicates one of numeric of 11,12,21,22,31,32,41,42,5,6,7,8) are bipolar transistor, code RL △△ (△△ represents any numeric, 2, 3, 4) is a load resistor, reference numeral RE ○○ (○○ is 11,12,21,22,31, either indicating the numeric of) the emitter resistance of 32,41,42, Vout, m is the output signal terminal QT of the second stage of the variable amplifier VGA2 the automatic gain controller AGC to monitor the differential output signal in QC Output signal amplitude, Vc is a differential control signal (corresponding to the gain control voltage VGC in the case of FIG. 1), VCC is a first power supply voltage terminal collector side power supply voltage terminal, and VEE is a second power supply voltage terminal. Some emitter-side power supply voltage terminals, DUT / DUC are differential signals ChikaraTadashi / complementary terminal, DLT / DLC Each differential control signal (Vc) Input Positive / auxiliary terminals, QT / QC are each differential signal output positive / complementary terminal.

  In the variable gain circuit 10A of the present embodiment shown in FIG. 3, as described above, the two variable gain amplifiers VGA1 and VGA2 of the first stage and the second stage are connected in series, and the automatic gain adjuster AGC monitors the amplitude of the output voltage of the differential output signal of the second stage variable gain amplifier VGA2, and the difference between the second stage variable gain amplifier VGA2 monitored as the output of the final stage variable gain amplifier VGA. A single differential control signal Vc is generated from the difference (Vout, g−Vout, m) between the output signal amplitude Vout, m of the dynamic output signal and the target output signal amplitude Vout, g. The gain of the two variable gain amplifiers VGA1 and VGA2 is controlled only by a single differential control signal Vc generated by the automatic gain adjuster AGC to obtain a target output signal amplitude Vout, g. Has been.

  Here, each of the variable gain amplifiers VGA1 and VGA2 has the same structure, and each of the first amplifier circuits 11a and 21a, the third amplifier circuits 13a and 23a, and the second amplifier circuit. 12a and 22a and fourth amplifier circuits 14a and 24a form two differential pairs, and amplifier circuits 15a and 25a, and gain adjustment circuits 16a and 26a that adjust the gains of the amplifier circuits 15a and 25a. , And constant current sources 17a and 27a for supplying constant current to the amplifier circuit portions 15a and 25a.

  The first amplifier circuits 11a and 21a are connected to the first amplifier transistors xt11 and xt31, the first emitter resistors RE11 and RE31 connected to the emitters of the first amplifier transistors xt11 and xt31, and the collector. The first amplifier resistors RL1 and RL3 shared with the second amplifier circuits 12a and 22a are configured. The second amplifier circuits 12a and 22a include second amplifier transistors xt21 and xt41, second amplifier transistors And second emitter resistors RE21 and RE41 connected to the emitters of the transistors xt21 and xt41. The collector resistors connected to the collectors of the second amplifying transistors xt21 and xt41 are the first collector resistors RL1 and RL3 shared with the first amplifying circuits 11a and 21a as described above.

  The third amplifying circuits 13a and 23a include third amplifying transistors xt12 and xt32, third emitter resistors RE12 and RE32 connected to the emitters of the third amplifying transistors xt12 and xt32, and collectors, respectively. The fourth amplifier circuits 14a and 24a are connected to each other and are shared by the fourth amplifier circuits 14a and 24a, and are shared by the fourth amplifier circuits 14a and 24a. The fourth amplifier circuits 14a and 24a include fourth amplifier transistors xt22 and xt42, And fourth emitter resistors RE22 and RE42 connected to the emitters of the amplifying transistors xt22 and xt42. Note that the collector resistors connected to the collectors of the fourth amplification transistors xt22 and xt42 are the second collector resistors RL2 and RL4 shared with the third amplifier circuits 13a and 23a, as described above.

  The gain adjustment circuits 16a and 26a are constituted by a differential pair of first gain adjustment transistors xt5 and xt7 and second gain adjustment transistors xt6 and xt8.

  The bases of the first / second gain adjusting transistors xt5, xt7 / xt6, xt8 of the gain adjusting circuits 16a, 26a are supplied from the automatic gain adjuster AGC via the differential control signal input positive / complement terminals DLT / DLC. Thus, a differential control signal, that is, a gain adjustment signal Vc is applied, and the first amplifier circuits 11a and 21a to the fourth amplifier circuits 14a and 24a of the amplifier circuit sections 15a and 25a are applied according to the value of the gain adjustment signal Vc. The gain is adjusted and outputted to the variable gain amplifier VGA at the next stage, and finally outputted as a differential output signal after amplification from the differential signal output positive / complement terminal QT / QC.

  That is, in the first-stage variable gain amplifier VGA1 of the variable gain circuit 10A of FIG. 3, the first amplification circuit unit 15a is connected to the collector side of the first amplification transistor xt11 and the first amplification transistor xt11. A first amplifying circuit 11a including a first collector resistor RL1 to be connected, a first emitter resistor RE11 connected to the emitter side of the first amplifying transistor xt11, and a first amplifying circuit 11a having a collector connected to the first collector resistor RL1. An amplifying circuit unit composed of two amplifying circuits: a second amplifying transistor xt21 and a second amplifying circuit 12a comprising a second emitter resistor RE21 connected to the emitter side of the second amplifying transistor xt21; It has the same configuration as the amplification circuit section, and is a collection of the third amplification transistor xt12 and the third amplification transistor xt12. A third amplifying circuit 13a comprising a second collector resistor RL2 connected to the side and a third emitter resistor RE12 connected to the emitter side of the third amplifying transistor xt12, and a collector to the second collector resistor RL2. An amplifying circuit unit composed of two amplifying circuits, a fourth amplifying circuit 14a comprising a fourth transistor xt22 connected and a fourth emitter resistor RE22 connected to the emitter side of the fourth amplifying transistor xt22; I have.

  The second stage variable gain amplifier VGA2 includes a first amplifying transistor xt31 and a first collector resistor RL3 connected to the collector side of the first amplifying transistor xt31 as the second amplifying circuit unit 25a. The first amplifier circuit 21a composed of the first emitter resistor RE31 connected to the emitter side of the first amplifier transistor xt31, the second amplifier transistor xt41 having the collector connected to the first collector resistor RL3, The amplifier circuit unit is composed of two amplifier circuits, the second amplifier circuit 22a including the second emitter resistor RE41 connected to the emitter side of the second amplifier transistor xt41, and has the same configuration as the amplifier circuit unit. The second collector resistor connected to the collector side of the third amplifying transistor xt32 and the third amplifying transistor xt32. A third amplifier circuit 23a comprising an anti-RL4, a third emitter resistor RE32 connected to the emitter side of the third amplifying transistor xt32, and a fourth transistor xt42 having a collector connected to the second collector resistor RL4, And an amplifying circuit unit composed of two amplifying circuits, a fourth amplifying circuit 24a composed of a fourth emitter resistor RE42 connected to the emitter side of the fourth amplifying transistor xt42.

  The other terminals of the first collector resistors RL1 and RL3 and the second collector resistors RL2 and RL4 are connected to a collector power supply voltage terminal VCC which is a first power supply voltage terminal.

  Among the amplifying transistors of the two amplifying circuits forming the differential pair as the amplifying circuit portions 15a and 25a, each of the first amplifying transistors xt11 and xt31 and the third amplifying transistors xt12 and xt32 is provided. The emitter side is commonly connected via the first emitter resistors RE11 and RE31 and the third emitter resistors RE12 and RE32, and the second amplifying transistors xt21 and xt41 and the fourth amplifying transistors xt22 and xt42 are connected. Each emitter side is commonly connected via second emitter resistors RE21 and RE41 and fourth emitter resistors RE22 and RE42.

  In the first stage variable gain amplifier VGA1, the first and second amplifying transistors xt11 and xt21 having the base terminal connected in common and the third and fourth amplifying transistors having the base terminal connected in common. A differential input signal is applied to the bases of xt12 and xt22 via the differential signal input positive / complement terminal DUT / DUC as an input signal for amplification of the first stage, and the second stage In the variable gain amplifier VGA2, each of the first and second amplifying transistors xt31 and xt41 having a base terminal connected in common and the third and fourth amplifying transistors xt32 and xt42 having a base terminal connected in common. The collectors of the third and fourth amplifying transistors xt12 and xt22 in the first stage variable gain amplifier VGA1 connected in series with the previous stage (that is, the base) Positive output signal output terminal), collectors of the first and second amplifying transistors xt11 and xt21 (that is, the output terminal of the differential output complementary signal), differential input as the second stage amplification input signal A signal is applied.

  That is, in the first-stage variable gain amplifier VGA1, differential input signals are applied to the bases of the first and second amplification transistors xt11 and xt21 and the third and fourth amplification transistors xt12 and xt22, respectively. When applied, the first and third emitter resistors RE11 and RE12 are connected in common and the second and fourth resistors RE21 and RE22 are connected in common, respectively. The transistors xt11 and xt12 and the second and fourth amplifying transistors xt21 and xt22 perform a differential amplifying operation in combination with each other, and the first and second amplifying transistors xt11, xt11, xt21 and the third and fourth amplifying transistors xt12 and xt22, whose collector terminals are commonly connected, are increased from the respective collector terminals. Differential amplifying operation is performed that outputs a differential output signal as an output signal after. The same applies to the second-stage variable gain amplifier VGA2, and a differential amplification operation is performed.

  Note that the first emitter resistors RE11 and RE31 of the first amplifier circuits 11a and 21a constituting the differential pair and the third emitter resistors RE12 and RE32 of the third amplifier circuits 13a and 23a are commonly connected. Also, the terminals to which the second emitter resistors RE21 and RE41 of the second amplifier circuits 12a and 22a and the fourth emitter resistors RE22 and RE42 of the fourth amplifier circuits 14a and 24a are connected in common are respectively The first constant current source CS1 17a and the second constant current source CS2 27a are connected via the first gain adjustment transistors xt5, xt7 and the second gain adjustment transistors xt6, xt8. The first constant current source CS1 17a and the second constant current source CS2 27a are connected to the emitter side power supply voltage terminal VEE which is the second power supply voltage terminal. It is.

  Here, the resistance values of the first emitter resistor RE11, the second emitter resistor RE21, the third emitter resistor RE12, and the fourth emitter resistor RE22 in the first-stage variable gain amplifier VGA1, and the second-stage gain. The resistance values of the first emitter resistor RE31, the second emitter resistor RE41, the third emitter resistor RE32, and the fourth emitter resistor RE42 in the variable amplifier VGA2 have the following relationship.

RE11 = RE12 ≠ RE21 = RE22
and,
RE31 = RE32 ≠ RE41 = RE42
That is, the first emitter resistors RE11 and RE31 and the third emitter resistors RE12 and RE32 are equal in phase, the second emitter resistors RE21 and RE41 and the fourth emitter resistors RE22 and RE42 are equal in phase, and the first The emitter resistors RE11 and RE31 or the third emitter resistors RE12 and RE32 and the second emitter resistors RE21 and RE41 or the fourth emitter resistors RE22 and RE42 are set to different values.

  By adopting such a configuration, each single variable gain amplifier VGA1, VGA2 has a circuit configuration excellent in input / output linearity.

Furthermore, excellent input / output linearity is ensured even in a circuit configuration in which a variable gain amplifier VGA having a single input / output linearity is connected in multiple stages, such as a two-stage variable gain circuit 10A shown in FIG. As described above, the resistance values of the first emitter resistor RE11, the second emitter resistor RE21, the third emitter resistor RE12, and the fourth emitter resistor RE22 in the first stage variable gain amplifier VGA1, The following relationship is maintained among the resistance values of the first emitter resistor RE31, the second emitter resistor RE41, the third emitter resistor RE32, and the fourth emitter resistor RE42 in the variable gain amplifier VGA2. Set to That is, regarding the resistance values of the eight emitter resistors of the first to fourth amplifier circuits 11a, 21a to 14a, 24a constituting the upper differential pair in the variable gain amplifiers VGA1 and VGA2,
RE11 = RE12> RE31 = RE32
and,
RE21 = RE22> RE41 = RE42
It is set to become.

  That is, the resistance values of the emitter resistors RE11 and RE12 and the resistance values of the emitter resistors RE21 and RE22 in the first-stage variable gain amplifier VGA1 respectively correspond to the corresponding emitter resistors RE31 and RE31 in the second-stage variable gain amplifier VGA2. It is set to be larger than the resistance value of RE32 and the resistance values of emitter resistors RE41 and RE42. When a plurality of variable gain amplifiers are configured in two or more stages, the resistance value of the first emitter resistance or the third emitter resistance included in each variable gain amplifier and the second emitter resistance Alternatively, each of the resistance values of the fourth emitter resistors is set so as to gradually decrease or become equal in some cases as it proceeds from the input signal terminal side to the output signal terminal side.

  As a result, under the same differential control signal, that is, the gain control signal Vc, the gain of the first-stage variable gain amplifier VGA1 is always smaller than the gain of the second-stage variable gain amplifier VGA2. Therefore, the output of the first-stage variable gain amplifier VGA1 does not have an extremely large amplitude, but the second-stage variable gain amplifier VGA2 is driven with a voltage having a relatively small amplitude, and the signal distortion is reduced. A small differential output signal is output from the second-stage variable gain amplifier VGA2, that is, the variable gain circuit 10A.

  Next, simulation results regarding input / output linearity of the variable gain circuit 10A of the present embodiment shown in FIG. 3 will be described using the output signal spectrum of FIG. In the schematic diagram of the output signal spectrum of FIG. 4, FIG. 4A shows a simulation result regarding input / output linearity in the case of the gain variable circuit of the conventional example for comparison with the gain variable circuit 10A of the present embodiment. FIG. 4B shows a simulation result regarding input / output linearity in the case of the variable gain circuit 10A of the present embodiment.

  4 (A) and 4 (B), FIG. 4 (A1) and FIG. 4 (B1) respectively show the output signal spectrum in the case of the conventional gain variable circuit, and the gain variable circuit of this embodiment. 10A shows the simulation result of the output signal spectrum in the case of 10A, and each of FIG. 4 (A2) and FIG. 4 (B2) on the lower side shows the output signal waveform (output time waveform) in the case of the conventional gain variable circuit, this implementation The simulation result of the output signal waveform (output time waveform) in the case of the variable gain circuit 10A is shown.

  In this simulation, a 3 GHz sine wave signal having a differential voltage of 300 mVpp is input as a differential input signal to the differential signal input positive / complement terminal DUT / DUC of the first-stage variable gain amplifier VGA1.

Further, as a conventional variable gain circuit, the same circuit configuration as that of the variable gain circuit 10A of the present embodiment in FIG. 3 is used, and related gains G (VGA1) and G (VGA2) of the variable gain amplifiers VGA1 and VGA2 are related. Example gain distribution condition G (VGA1) ≧ G (VGA2)
In this range, G (VGA1) = G (VGA2) is a condition that can suppress the distortion of the output signal to the smallest value.
The resistance values of the emitter resistors are set so that RE11 = RE12 = RE31 = RE32
and,
RE21 = RE22 = RE41 = RE42
Is used.

Further, for the variable gain circuit 10A of the present embodiment, RE11 = RE12> RE31 = RE32, which are the above-described conditions relating to the resistance value of the emitter resistor of the present embodiment.
and,
RE21 = RE22> RE41 = RE42
To meet,
RE11 = RE12 = 2 × RE31 = 2 × RE32
and,
RE21 = RE22 = 2 × RE41 = 2 × RE42
Is used.

  As is clear from the simulation results shown in FIG. 4, the ratio of the 9 GHz component, which is the third harmonic distortion of the 3 GHz differential output signal, to the 3 GHz component is as shown in FIG. As shown in FIG. 4 (B1), the gain variable circuit 10A according to the present embodiment is −18.6 dB, as shown in FIG. 4 (B1). It can be seen that the harmonic suppression improvement effect of 4.1 dB is obtained as compared with the case of the variable gain circuit.

(Third embodiment)
Next, a specific circuit configuration example of the variable gain circuit according to the present invention will be described as a third embodiment with reference to FIG. Note that the variable gain circuit 10B of the present embodiment shown in FIG. 5 is also the first amplifier having two differential pairs, as in the case of the variable gain circuit 10A shown in FIG. 3 as the second embodiment. A first stage variable gain amplifier VGA1 including a circuit unit 15a, a first gain adjustment circuit 16b, and a first constant current source 17a, a second amplifier circuit unit 25a including two differential pairs, A second gain variable amplifier VGA2 including a second gain adjustment circuit 26b and a second constant current source 27a are connected in series, and the voltage level of the differential output signal of the second gain variable amplifier VGA2 is monitored. An automatic gain adjuster AGC that outputs a gain control voltage according to the result is provided.

  However, in the variable gain circuit 10B of this embodiment shown in FIG. 5, each of the first gain adjustment transistors xt5, xt7 and the second gain adjustment transistors xt6, xt8 constituting the gain adjustment circuits 16b, 26b. Unlike the gain adjustment circuits 16a and 26a in the case of the variable gain circuit 10A shown in FIG. 3, the emitter includes first gain adjustment emitter resistors RE5 and RE7, and second gain adjustment emitter resistors RE6 and RE8. It is connected.

  Here, in the gain adjustment circuits 16b and 26b, the first gain adjustment emitter resistors RE5 and RE7 connected to the emitters of the first gain adjustment transistors xt5 and xt7 and the second gain adjustment transistors xt6 and xt8, respectively. As for the resistance values of the second gain adjusting emitter resistors RE6 and RE8, the following variable gain circuit 10B, in which the variable gain amplifier VGA is connected in multiple stages, also ensures the following excellent input / output linearity. Set up a relationship like this.

RE5 = RE6 <RE7 = RE8
That is, the first gain adjusting emitter resistor RE5 connected to the emitter of the first gain adjusting transistor xt5 and the emitter of the second gain adjusting transistor xt6 of the first stage variable gain amplifier VGA1 are connected. The resistance values of the second gain adjusting emitter resistors RE6 are equal to each other and are connected to the emitter of the first gain adjusting transistor xt7 of the second stage variable gain amplifier VGA2. The resistance values of the second gain adjustment emitter resistor RE8 connected to RE7 and the emitter of the second gain adjustment transistor xt8 are equal to each other, and the first gain of the first-stage variable gain amplifier VGA1. The resistance values of the adjustment emitter resistor RE5 and the second gain adjustment emitter resistor RE6 are the same as the first gain adjustment of the second-stage variable gain amplifier VGA2. Emitter resistor RE7, to a value smaller than the resistance value of the second gain adjusting emitter resistor RE8.

  Next, an example of the operation of the variable gain circuit 10B of this embodiment shown in FIG. 5 will be described with reference to the schematic diagram of FIG. FIG. 6 shows gains of the variable gain amplifiers VGA1 and VGA2 when the input amplitude of the differential input signal input to the differential signal input positive / complement terminal DUT / DUC of the variable gain circuit 10B of the present embodiment changes. FIG. 6A is a schematic diagram for explaining the distribution variation. FIG. 6A shows gains G (VGA1) and G (VGA2) of the variable gain amplifiers VGA1 and VGA2 when the input amplitude of the differential input signal changes. FIG. 6B shows how the difference in voltage amplitude of the gain control differential voltage, that is, the gain control signal Vc applied to the differential control signal input positive / complement terminal DLT / DLC changes. Is schematically shown.

Here, the input amplitude of the input signal to the differential signal input positive / auxiliary terminal DUT / DUC variable gain circuit 10B, the differential signal input positive terminal DUT and the differential signal input auxiliary terminal DU C shown in FIG. 5 The gain distribution of the variable gain amplifiers VGA1 and VGA2 is to monitor the differential output signal from the variable gain circuit 10B and adjust the gain from the automatic gain adjuster AGC. Difference in voltage amplitude of gain control signal Vc input as a differential control signal to circuits 16b and 26b, that is, a differential control signal applied between differential control signal input positive terminal DLT and differential control signal input complementary terminal DLC The gain control signal Vc varies depending on the difference in voltage amplitude.

When the input amplitude of the differential input signal to the gain variable circuit 10B is equal to or smaller than a predetermined threshold Vblc, the gain control differential voltage of the gain control signal Vc input as a differential control signal to the gain adjustment circuits 16b and 26b. As shown in FIG.
Vc ≧ 0
That is, the control voltage of the differential control signal input positive terminal DLT is equal to or higher than the control voltage of the differential control signal input complementary terminal DLC,
DLT ≧ DLC
As shown in FIG. 6A, the gain G (VGA1) of the first-stage variable gain amplifier VGA1 is equal to or higher than the gain G (VGA2) of the second-stage variable gain amplifier VGA2. Or equal.

On the other hand, when the input amplitude of the differential input signal to the gain variable circuit 10B is larger than the threshold value Vblc, the gain control differential voltage of the gain control signal Vc input as a differential control signal to the gain adjustment circuits 16b and 26b is As shown in FIG.
Vc <0
That is, the control voltage of the differential control signal input positive terminal DLT is smaller than the control voltage of the differential control signal input complementary terminal DLC,
DLT <DLC
As shown in FIG. 6A, the gain G (VGA1) of the first-stage variable gain amplifier VGA1 is smaller than the gain G (VGA2) of the second-stage variable gain amplifier VGA2. Or are equal.

This is because the lower differential pair in the first and second stage variable gain amplifiers VGA1 and VGA2 to which the same gain control signal Vc is input, that is, the emitter resistors RE5, RE6, RE7, As described above, the resistance value of RE8 is low on the first stage (previous stage) variable gain amplifier VGA1 side and high on the second stage (backstage) VGA2 side,
RE5 = RE6 <RE7 = RE8
This is because two upper differential pairs that determine the gain of each of the variable gain amplifiers VGA1 and VGA2 (that is, the first and third in the first stage variable gain amplifier VGA1 in FIG. 5) are set. A pair of amplifier circuits 11a and 13a and a pair of second and fourth amplifier circuits 12a and 14a, a pair of first and third amplifier circuits 21a and 23a in the second stage variable gain amplifier VGA2, and a second, The switching operation between the fourth amplifier circuits 22a and 24a) requires a small differential voltage value of the gain control signal Vc on the variable gain amplifier VGA1 side, but is large on the variable gain amplifier VGA2 side. This is because the differential voltage value of the gain control signal Vc is required.

  When a plurality of variable gain amplifiers are configured in two or more stages, the resistance value of the first gain adjusting emitter resistance and the second gain adjusting emitter resistance included in each variable gain amplifier. These resistance values are set so as to increase sequentially from the input signal terminal side to the output signal terminal side.

  When the input amplitude of the differential input signal to the gain variable circuit 10B is smaller than the threshold value Vblc, the gain G (VGA1) of the first stage variable gain amplifier VGA1 is equal to or higher than the second stage variable gain amplifier VGA2. Since the input amplitude is small, the output amplitude of the first-stage variable gain amplifier VGA1 does not increase. Accordingly, since the second stage variable gain amplifier VGA2 is not driven with a large amplitude, the signal distortion can be kept within an allowable range. In terms of noise characteristics, when the input amplitude is small, the gain G (VGA1) of the first-stage gain variable amplifier VGA1 on the input signal terminal side is the second-stage gain variable amplifier VGA2 on the output signal terminal side. Therefore, the signal-to-noise ratio is easily secured.

  On the other hand, when the input amplitude of the input signal to the gain variable circuit 10B is larger than the threshold value Vblc, the gain G (VGA1) of the first-stage variable gain amplifier VGA1 on the input signal terminal side is suppressed. The variable gain amplifier VGA2 at the stage is not driven with a large amplitude, and the signal distortion at the output of the variable gain amplifier VGA2 at the second stage can be kept within an allowable range. At this time, the noise characteristic is disadvantageous because the gain G (VGA1) of the first-stage variable gain amplifier VGA1 on the input side is small, but the input amplitude of the differential input signal is large. It is easy to ensure the S / N ratio before the variable gain circuit 10B illustrated in FIG. 5 and it is possible to suppress the degradation of the S / N ratio in the variable gain circuit 10B within an allowable range.

  Next, simulation results regarding input / output linearity of the variable gain circuit 10B of the present embodiment shown in FIG. 5 will be described using the output signal spectrum of FIG. In the schematic diagram of the output signal spectrum of FIG. 7, FIG. 7A shows a simulation result regarding input / output linearity in the case of the gain variable circuit of the conventional example, for comparison with the gain variable circuit 10B of the present embodiment. FIG. 7B shows a simulation result regarding input / output linearity in the case of the variable gain circuit 10B of the present embodiment.

  7A and 7B are respectively an output signal spectrum in the case of the conventional variable gain circuit, and the variable gain circuit of the present embodiment. 10B shows the simulation result of the output signal spectrum in the case of 10B. Each of FIG. 7 (A2) and FIG. 7 (B2) on the lower side shows the output signal waveform (output time waveform) in the case of the gain variable circuit of the conventional example. The simulation result of the output signal waveform (output time waveform) in the case of the variable gain circuit 10B of the embodiment is shown.

  Also in this simulation, as in the simulation of FIG. 4 in the second embodiment, the differential signal input positive / complement terminal DUT / DUC of the first stage variable gain amplifier VGA1 has a differential voltage of 300 mVpp of 3 GHz. It is assumed that a sine wave signal is input as a differential input signal.

Further, as the gain variable circuit of the conventional example, the same circuit configuration as that of the gain variable circuit 10B of the present embodiment in FIG. 5 is used, and the emitter resistors RE5, RE6, RE7, RE8 condition RE5 = RE6 <RE7 = RE8
This condition is that the distortion of the output signal can be suppressed to the smallest value although RE5 = RE6 = RE7 = RE8.
Is used.

Further, for the variable gain circuit 10B of the present embodiment, the conditions relating to the emitter resistors RE5, RE6, RE7, RE8 of the gain adjustment circuits 16b, 26b of the present embodiment RE5 = RE6 <RE7 = RE8.
To meet,
7 × RE5 = 7 × RE6 = RE7 = RE8
Is used.

  As is clear from the simulation results shown in FIG. 7, the ratio of the 9 GHz component, which is the third harmonic distortion of the 3 GHz differential output signal, to the 3 GHz component is as shown in FIG. As shown in A1), the gain variable circuit 10B according to the present embodiment is −18.6 dB, whereas in the present embodiment, as shown in FIG. Also, it can be seen that the effect of improving harmonic suppression of 1.3 dB is obtained as compared with the conventional gain variable circuit.

(Other embodiments)
In the description of each embodiment of the variable gain circuit according to the present invention, the amplifying transistors xt11, xt12, xt21, xt22, xt31, xt32, xt41, xt42, the gain adjusting transistors xt5, xt6, xt7, xt8 are as follows: Although the case where a bipolar transistor is used has been described, the present invention is not limited to such a case. For example, even when a field effect transistor is used, the same embodiment is possible.

In the second embodiment, the upper differential pair of the first-stage variable gain amplifier VGA1 on the input signal terminal side, that is, the emitters of the amplifying transistors xt11, xt12, xt21, and xt22 constituting each of the amplifying circuit unit 15a Resistors RE11, RE12, RE21, and RE22 are connected to the upper differential pair of the variable gain amplifier VGA2 at the second stage on the output signal terminal side, that is, the emitters of the amplifying transistors xt31, xt32, xt41, and xt42 constituting each of the amplifier circuit sections 25a. By making the resistance values of the resistors RE31, RE32, RE41, and RE42 larger than the resistance values of the first and second gain variable amplifiers VGA1 and VGA2,
G (VGA1) <G (VGA2)
The relationship was established so that

  However, such a setting relating to the gain is set not by the resistance value of the emitter resistance of each of the amplifying transistors xt11, xt12, xt21, xt22, xt31, xt32, xt41, xt42 but by the resistance value of the load resistance, that is, the collector resistance. Anyway. That is, the resistance values of the collector resistors RL3, RL4 of the amplifying transistors xt31, xt32, xt41, xt42 constituting each of the upper differential pair of the second stage variable gain amplifier VGA2 on the output signal terminal side, that is, the amplifier circuit unit 25a, The upper differential pair of the first-stage variable gain amplifier VGA1 on the input signal terminal side, that is, the resistance values of the collector resistors RL1 and RL2 of the amplifying transistors xt11, xt12, xt21, and xt22 constituting the amplifying circuit unit 15a. A similar setting for gain can be made by setting it to be large or equal in some cases.

  When a plurality of variable gain amplifiers are configured in two or more stages, each of the resistance value of the first collector resistance and the resistance value of the second collector resistance included in each variable gain amplifier is These are set so as to increase sequentially from the input signal terminal side to the output signal terminal side or to be equal in some cases.

  Further, in order to suppress the signal distortion of the output signal, the difference in resistance value of the emitter resistance of the upper differential pair between the variable gain amplifiers VGA1 and VGA2 described in the second embodiment, that is, the amplifier circuit unit 15a. The resistance values of the emitter resistors RE11, RE12, RE21, RE22 of the amplifying transistors xt11, xt12, xt21, xt22 and the emitter resistors RE31, RE32 of the amplifying transistors xt31, xt32, xt41, xt42 constituting the amplifying circuit unit 25a. , RE41, RE42, and the resistance value of the emitter resistance of the lower differential pair between the variable gain amplifiers VGA1, VGA2 described in the third embodiment, that is, gain adjustment. Emitter resistor RE5 of gain adjusting transistors xt5, xt6 constituting circuit 16b At the same time aiming the structures differentiation, the between the resistance value of the emitter resistor RE7, RE8 gain adjustment transistor XT7, XT8 constituting the resistance value and the gain adjustment circuit 26b of RE6 are possible.

1 is a block configuration diagram showing a first embodiment of a variable gain circuit according to the present invention. It is a level diagram explaining operation | movement of 1st embodiment of the variable gain circuit which concerns on this invention. It is a circuit diagram which shows the concrete circuit structural example of the gain variable circuit which concerns on this invention as 2nd embodiment. It is a schematic diagram which shows the simulation result regarding the input-output linearity of 2nd embodiment of the gain variable circuit which concerns on this invention. It is a circuit diagram which shows the concrete circuit structural example of the gain variable circuit which concerns on this invention as 3rd embodiment. It is a schematic diagram explaining the mode of the fluctuation | variation of the gain distribution of a variable gain amplifier when the input amplitude of the differential input signal input with respect to the gain variable circuit of 3rd Embodiment which concerns on this invention changes. It is a schematic diagram which shows the simulation result regarding the input-output linearity of 3rd embodiment of the gain variable circuit which concerns on this invention. It is a block block diagram which shows the circuit structure of the variable gain circuit using the conventional multistage variable gain amplifier.

Explanation of symbols

10, 10A, 10B, 10C ... gain variable circuit, 11a, 21a ... first amplifier circuit, 12a, 22a ... second amplifier circuit, 13a, 23a ... third amplifier circuit, 14a, 24a ... fourth amplifier Circuit, 15a, 25a ... Amplifier circuit section, 16a, 16b, 26a, 26b ... Gain adjustment circuit, 17a, 27a ... Constant current source, AGC ... Automatic gain adjuster, In ... Input signal terminal, DLC ... Differential control signal input Auxiliary terminal, DLT ... Differential control signal input positive terminal, DUC ... Differential signal input auxiliary terminal, DUT ... Differential signal input positive terminal, Out1, Out2 ... Output signal terminal, QC ... Differential signal output auxiliary terminal, QT ... Differential signal output positive terminal, RE11, RE31 ... first emitter resistor, RE21, RE41 ... second emitter resistor, RE12, RE32 ... third emitter resistor, RE22, RE42 ... fourth Emitter resistor, RE5, RE7 ... first gain adjusting emitter resistor, RE6, RE8 ... second gain adjusting emitter resistor, RL1, RL2, RL3, RL4 ... load resistor, Vc ... differential control signal (gain control signal) ), VCC ... collector-side power supply voltage terminal, VEE ... emitter-side power supply voltage terminal, VGA1-3 ... variable gain amplifier, VGC, VGC1-3 ... gain control voltage, Vin ... differential input signal voltage, Vout ... differential output signal Voltage, Vout, g ... target output signal amplitude, Vout, m ... output signal amplitude, xt11, xt12, xt21, xt22, xt31, xt32, xt41, xt42, xt5, xt6, xt7, xt8 ... bipolar transistor.

Claims (4)

  A plurality of variable gain amplifiers connected in series between the input signal terminal and the output signal terminal, and the result of monitoring the signal amplitude of the output signal at the output signal terminal, a single signal amplitude is obtained to obtain a target signal amplitude. An automatic gain adjuster that generates a gain control signal and outputs the gain control signal to each of the plurality of variable gain amplifiers as a signal for adjusting the gain of each of the plurality of variable gain amplifiers. In the variable gain circuit, the gain of each of the variable gain amplifiers sequentially increases from the input signal terminal side to the output signal terminal side, wherein each of the variable gain amplifiers includes a first amplification transistor and one end of the first amplification transistor. A first collector resistor connected to the collector of the transistor, the other end connected to the first power supply voltage terminal, and one end connected to the emitter of the first amplifying transistor A first amplifying circuit comprising the first emitter resistor, a second amplifying transistor whose collector is connected to one end of the first collector resistor, and one end of which is the emitter of the second amplifying transistor A second amplifying circuit connected to the second amplifying resistor, a third amplifying transistor, one end connected to the collector of the third amplifying transistor, and the other end to the first power source A third amplifying circuit comprising a second collector resistor connected to the voltage terminal and a third emitter resistor having one end connected to the emitter of the third amplifying transistor; and a collector serving as the second collector Four amplifier circuits, a fourth amplifier circuit including a fourth amplifier transistor connected to one end of the resistor and a fourth emitter resistor having one end connected to the emitter of the fourth amplifier transistor. A collector is connected to a connection point in which an amplifier circuit unit composed of a width circuit, the other end of the first emitter resistor, and the other end of the third emitter resistor are connected together, and the first amplifier circuit and the A collector is connected to a connection point where the first gain adjusting transistor for adjusting the gain with the third amplifier circuit, the other end of the second emitter resistor and the other end of the fourth emitter resistor are connected in common. A gain adjusting circuit connected to the second amplifying circuit for adjusting a gain of the second amplifying circuit and the fourth amplifying circuit; an emitter of the first gain adjusting transistor; A variable gain amplifier comprising a constant current source connected between a connection point where the emitters of the two gain adjusting transistors are connected in common and a second power supply voltage terminal, And a second amplification transformer Apply the positive signal of the differential input signal to the connection point where the bases of the respective transistors are commonly connected, and the differential input to the connection point where the bases of the third and fourth amplifying transistors are commonly connected. A signal on the complementary side of the signal is applied to cause the first and second amplifier circuits and the third and fourth amplifier circuits to perform a differential operation so that each of the first and second amplifier transistors Outputs the complementary side signal of the amplified differential output signal from the connection point where the collectors are commonly connected, and the difference after amplification from the connection point where the collectors of the third and fourth amplification transistors are connected in common In each of the plurality of variable gain amplifiers configured as a differential amplifier circuit that outputs a positive side signal of a dynamic output signal and connected in series between the input signal terminal and the output signal terminal, Emitter resistance and the above The resistance values of the three emitter resistors are equal to each other, the resistance values of the second emitter resistor and the fourth emitter resistor are equal to each other, and the first emitter resistor or the third emitter resistor is The resistance value of the first emitter resistor or the third emitter resistor included in each of the plurality of variable gain amplifiers is not equal to the second emitter resistor or the fourth emitter resistor, And each of the resistance values of the second emitter resistance or the fourth emitter resistance is set so as to become smaller or equal in order as it proceeds from the input signal terminal side to the output signal terminal side, and the automatic A signal on the positive side of the single gain control signal output as a differential control signal from the gain adjuster is applied to the base of the first gain adjusting transistor. And applying a complementary signal of the single gain control signal output as a differential control signal from the automatic gain adjuster to the base of the second gain adjusting transistor, thereby performing the differential amplification. A gain variable circuit for adjusting a gain of the variable gain amplifier configured as a circuit. A plurality of variable gain amplifiers connected in series between the input signal terminal and the output signal terminal, and the result of monitoring the signal amplitude of the output signal at the output signal terminal, a single signal amplitude is obtained to obtain a target signal amplitude. An automatic gain adjuster that generates a gain control signal and outputs the gain control signal to each of the plurality of variable gain amplifiers as a signal for adjusting the gain of each of the plurality of variable gain amplifiers. In the variable gain circuit, the gain of each of the variable gain amplifiers sequentially increases from the input signal terminal side to the output signal terminal side, wherein each of the variable gain amplifiers includes a first amplification transistor and one end of the first amplification transistor. A first collector resistor connected to the collector of the transistor, the other end connected to the first power supply voltage terminal, and one end connected to the emitter of the first amplifying transistor A first amplifying circuit comprising the first emitter resistor, a second amplifying transistor whose collector is connected to one end of the first collector resistor, and one end of which is the emitter of the second amplifying transistor A second amplifying circuit connected to the second amplifying resistor, a third amplifying transistor, one end connected to the collector of the third amplifying transistor, and the other end to the first power source A third amplifying circuit comprising a second collector resistor connected to the voltage terminal and a third emitter resistor having one end connected to the emitter of the third amplifying transistor; and a collector serving as the second collector Four amplifier circuits, a fourth amplifier circuit including a fourth amplifier transistor connected to one end of the resistor and a fourth emitter resistor having one end connected to the emitter of the fourth amplifier transistor. A collector is connected to a connection point in which an amplifier circuit unit composed of a width circuit, the other end of the first emitter resistor, and the other end of the third emitter resistor are connected together, and the first amplifier circuit and the A collector is connected to a connection point where the first gain adjusting transistor for adjusting the gain with the third amplifier circuit, the other end of the second emitter resistor and the other end of the fourth emitter resistor are connected in common. A gain adjusting circuit connected to the second amplifying circuit for adjusting a gain of the second amplifying circuit and the fourth amplifying circuit; an emitter of the first gain adjusting transistor; A variable gain amplifier comprising a constant current source connected between a connection point where the emitters of the two gain adjusting transistors are connected in common and a second power supply voltage terminal, And a second amplification transformer Apply the positive signal of the differential input signal to the connection point where the bases of the respective transistors are commonly connected, and the differential input to the connection point where the bases of the third and fourth amplifying transistors are commonly connected. A signal on the complementary side of the signal is applied to cause the first and second amplifier circuits and the third and fourth amplifier circuits to perform a differential operation so that each of the first and second amplifier transistors Outputs the complementary side signal of the amplified differential output signal from the connection point where the collectors are commonly connected, and the difference after amplification from the connection point where the collectors of the third and fourth amplification transistors are connected in common In each of the plurality of variable gain amplifiers configured as a differential amplifier circuit that outputs a positive side signal of a dynamic output signal and connected in series between the input signal terminal and the output signal terminal, Emitter resistance and the above The resistance values of the three emitter resistors are equal to each other, the resistance values of the second emitter resistor and the fourth emitter resistor are equal to each other, and the first emitter resistor or the third emitter resistor is The resistance value of the first collector resistor included in each of the plurality of gain variable amplifiers and the second collector resistance is not equal to the second emitter resistor or the fourth emitter resistor , and the second collector Each of the resistance values of the resistors is set so as to sequentially increase or become equal as it advances from the input signal terminal side to the output signal terminal side, and is output as a differential control signal from the automatic gain adjuster. The signal on the positive side of the gain control signal is applied to the base of the first gain adjustment transistor, and is output as a differential control signal from the automatic gain adjuster. The complement side of the signal of said gain control signal, by applying to the base of the second gain adjusting transistor, and adjusting the gain of said variable gain amplifier configured as the differential amplifier circuit Variable gain circuit. A plurality of variable gain amplifiers connected in series between the input signal terminal and the output signal terminal, and the result of monitoring the signal amplitude of the output signal at the output signal terminal, a single signal amplitude is obtained to obtain a target signal amplitude. An automatic gain adjuster that generates a gain control signal and outputs the gain control signal to each of the plurality of variable gain amplifiers as a signal for adjusting the gain of each of the plurality of variable gain amplifiers. In the variable gain circuit, the gain of each of the variable gain amplifiers sequentially increases from the input signal terminal side to the output signal terminal side, wherein each of the variable gain amplifiers includes a first amplification transistor and one end of the first amplification transistor. A first collector resistor connected to the collector of the transistor, the other end connected to the first power supply voltage terminal, and one end connected to the emitter of the first amplifying transistor A first amplifying circuit comprising the first emitter resistor, a second amplifying transistor whose collector is connected to one end of the first collector resistor, and one end of which is the emitter of the second amplifying transistor A second amplifying circuit connected to the second amplifying resistor, a third amplifying transistor, one end connected to the collector of the third amplifying transistor, and the other end to the first power source A third amplifying circuit comprising a second collector resistor connected to the voltage terminal and a third emitter resistor having one end connected to the emitter of the third amplifying transistor; and a collector serving as the second collector Four amplifier circuits, a fourth amplifier circuit including a fourth amplifier transistor connected to one end of the resistor and a fourth emitter resistor having one end connected to the emitter of the fourth amplifier transistor. A collector is connected to a connection point in which an amplifier circuit unit composed of a width circuit, the other end of the first emitter resistor, and the other end of the third emitter resistor are connected together, and the first amplifier circuit and the A collector is connected to a connection point where the first gain adjusting transistor for adjusting the gain with the third amplifier circuit, the other end of the second emitter resistor and the other end of the fourth emitter resistor are connected in common. A gain adjusting circuit connected to the second amplifying circuit for adjusting a gain of the second amplifying circuit and the fourth amplifying circuit; and one end of the emitter of the first gain adjusting transistor. A connection point where the other end of the connected first gain adjusting emitter resistor and the other end of the second gain adjusting emitter resistor connected at one end to the emitter of the second gain adjusting transistor are connected in common; Said second power supply voltage A variable gain amplifier including a constant current source connected between the terminals and a differential input signal at a connection point where the bases of the first and second amplifying transistors are commonly connected Of the differential input signal is applied to a connection point where the bases of the third and fourth amplifying transistors are commonly connected, and the first and second signals are applied. A differential output signal after amplification from a connection point where the collectors of the first and second amplifying transistors are commonly connected by differentially operating a second amplifying circuit and the third and fourth amplifying circuits And a differential amplifier circuit for outputting a positive signal of the amplified differential output signal from a connection point where collectors of the third and fourth amplification transistors are connected in common And the input signal terminal In each of the plurality of variable gain amplifiers connected in series with the output signal terminal, the first emitter resistor and the third emitter resistor have the same resistance value, and the second emitter resistor The resistance values of the fourth emitter resistance are equal to each other, and the resistance values of the first emitter resistance or the third emitter resistance and the second emitter resistance or the fourth emitter resistance are not equal. And the resistance values of the first gain adjusting emitter resistor and the second gain adjusting emitter resistor included in each of the variable gain amplifiers are equal to each other and included in each of the plurality of variable gain amplifiers. The resistance value of the first gain adjusting emitter resistor and the resistance value of the second gain adjusting emitter resistor are respectively advanced from the input signal terminal side to the output signal terminal side. The signal on the positive side of the single gain control signal output as a differential control signal from the automatic gain adjuster is applied to the base of the first gain adjusting transistor. Applying the complementary signal of the single gain control signal output as a differential control signal from the automatic gain adjuster to the base of the second gain adjusting transistor, thereby the differential amplifier circuit A variable gain circuit characterized by adjusting a gain of the variable gain amplifier configured as described above . In the variable gain circuit according to any one of claims 1 to 3, wherein the first to fourth amplifying transistor, said first, second gain adjustment transistor, either a bipolar transistor or a field effect transistor A gain variable circuit characterized by the above.

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