JP4851888B2 - Data transfer method and data transfer method - Google Patents

Description

  The present invention relates to a data transfer method and a data transfer method, and more particularly to a data transfer method and a data transfer method that can prevent a decrease in throughput and latency when periodic execution of clock phase adjustment is required.

  In an interface for performing high-speed serial communication, a clock on the transmission side and a clock on the reception side have the same frequency but have different errors because of different sources. Therefore, the clock phase adjustment on the transmission side and the reception side is performed at the initialization of the operation start. However, even if the operation is started in this way, the phase shifts due to a clock error between the transmission side and the reception side over time, and therefore, it is necessary to adjust the clock phase again at regular intervals. Since data transfer must be stopped during the clock phase adjustment period, there is a problem that latency and throughput are lowered.

  As a conventional data transfer method and data transfer method for solving these problems, there is one that shortens the time required for clock phase adjustment (see, for example, Patent Document 1).

JP-A-11-88162

  However, these conventional data transfer methods and data transfer methods cannot completely avoid interruption of data transfer during the clock phase adjustment period, and the performance of the throughput and latency is deteriorated due to the influence of the clock phase adjustment. There was a problem that it was unavoidable.

  An object of the present invention is to provide a data transfer method and a data transfer method that solve the performance degradation caused by clock phase adjustment, which is the conventional problem described above.

  The first data transfer method of the present invention is a data transfer method having one or more transmission paths, and generates transfer data on the receiving side when data transfer cannot be performed on any of the one or more transmission paths. One or more redundant transmission lines for transferring redundant data to be used, and clock phase adjustment of the one or more transmission lines and the one or more redundant transmission lines, the one or more transmission lines and the one or more redundant transmission lines A means for shifting the timing every time is provided.

  The second data transfer system of the present invention is a data transfer system having one or more transmission paths in the first data transfer system, wherein the clock of any one of the one or more transmission paths is a clock. When phase adjustment is performed, receiving means for generating the transfer data by complementing with the redundant data of the redundant transmission path is provided.

  A third data transfer system of the present invention is a data transfer system having one or more transmission paths in the first or second data transfer system, and is one of the one or more transmission paths. And receiving means for generating the transfer data by complementing with the redundant data of the redundant transmission line when a failure of the transmission line is detected.

  In a fourth data transfer method of the present invention, in the first, second, or third data transfer method, the redundant data is parity data of transfer data of the one or more transmission paths, The generation of the transfer data is obtained by taking an exclusive OR of the transfer data and the redundant data on the transmission line excluding any of the transmission lines on which the data transfer is not possible.

  The first data transfer method of the present invention is a data transfer method for an interface having one or more transmission lines, and when one of the one or more transmission lines cannot transfer data, one or more redundant transmissions are performed. The transfer data is generated on the receiving side using the redundant data transferred on the path, and the clock phase adjustment of the one or more transmission paths and the one or more redundant transmission paths is performed using the one or more transmission paths and the 1 The timing is shifted for each redundant transmission path.

  A second data transfer method of the present invention is the data transfer method of an interface having one or more transmission paths in the first data transfer method, wherein any one of the one or more transmission paths When the clock phase adjustment is performed, the transfer data is generated by complementing with the redundant data of the redundant transmission path.

  A third data transfer method of the present invention is the data transfer method for an interface having one or more transmission paths in the first or second data transfer method, wherein the one or more transmission paths When a failure in any transmission line is detected, the transfer data is generated by complementing the redundant data in the redundant transmission line.

  In a fourth data transfer method of the present invention, in the first, second, or third data transfer method, the redundant data is parity data of transfer data of the one or more transmission paths, The generation of the transfer data is obtained by taking an exclusive OR of the transfer data and the redundant data on the transmission line excluding any of the transmission lines on which the data transfer is not possible.

  The present invention has an effect that performance degradation due to clock phase adjustment can be prevented. The reason is that transfer data can be generated on the receiving side even if data cannot be transferred on any transmission path by transferring redundant data that can complement the transfer data and shifting the clock adjustment timing for each transmission path. It is.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, in the first embodiment of the present invention, there are four transmission lines and one redundant transmission line for each transfer direction connecting LSI 200 and LSI 100 having the same structure, and LSI 200 and LSI 100. It is composed of a link 400 (from the LSI 200 to the LSI 100 direction) and five links 300 (from the LSI 100 to the LSI 200 direction) composed of five SERDES interfaces.

  The LSI 200 includes a processor 210 that processes data to be transmitted / received, a function of dividing transmission data and generating parity data, and a transmission control unit 220 having a function of controlling the timing of DLL adjustment, which is clock phase adjustment of a transmission path, Five transmission macros (SM in FIG. 1) 230 to 234 having a function of serially converting data and outputting to the link 400, five receptions having a function of receiving serial data from the link 300 and converting it into byte data The macro (RM in FIG. 1) 240 to 244 includes a reception control unit 250 having a function of restoring received data to a format usable by the processor 210 and outputting the data to the processor 210. A macro is a circuit unit.

  Each of the transmission macros 230 to 234 has a function of starting a DLL adjustment sequence on the divided links 410 to 414 when the DLL adjustment instruction signal is asserted from the transmission control unit 220.

  The reception macros 240 to 244 of the LSI 200 have a function of recognizing that the DLL adjustment sequence is started from the LSI 100 and asserting a data invalid signal to the reception control unit 250. When receiving a data invalid signal from any of the reception macros 240 to 243, the reception control unit 250 regards input data from the reception macro as invalid, and generates data to be output to the processor 210 from the reception macro. The input data is not used. The DLL adjustment is performed between the transmission macros 230 to 234 and the reception macros 140 to 144 on the corresponding divided links 410 to 414 in both directions, and it takes time of several tens to several hundreds clocks to complete a series of sequences. The DLL adjustment operation is an existing technique and will not be described in particular. During DLL adjustment, the reception macros 240 to 244 continue to assert a data invalid signal to the reception control unit 250.

  The reception macros 140 to 144 have a function of monitoring the error of the corresponding divided link 410 to 414 and asserting a data invalid signal to the reception control unit 150 when the error is detected. Attempt to recover ~ 414. Note that the link error detection method and recovery method are existing techniques and will not be described in particular. When the recovery of the divided links 410 to 414 is successful and the data transfer can be resumed, the reception macros 140 to 144 deassert the data invalid signal, but the recovery of the divided links 410 to 414 fails. Continues to assert the data invalid signal.

  The link 400 is composed of five SERDES interfaces of divided links 410 to 414. Each SERDES interface is capable of transferring data at 2 bytes / clock. The division links 410 to 413 are data transfer transmission paths (total 8 bytes / clock). The division link 414 is a redundant transmission path for transferring a bit-corresponding parity value of the division links 410 to 413 as redundant data.

  Since the LSI 100 has the same configuration as the LSI 200, description thereof is omitted. Since the link 300 has the same configuration as the link 400, the description thereof is omitted. Since the divided links 310 to 314 have the same configuration as the divided links 410 to 414, description thereof is omitted. Since the transmission control unit 120 has the same configuration as the transmission control unit 220, description thereof is omitted. Since the transmission macros 130 to 134 have the same configuration as that of the transmission macros 230 to 234, description thereof is omitted.

  Next, the operation of the best mode for carrying out the present invention will be described with reference to the drawings.

  First, the data transfer operation during normal operation will be described. FIG. 2 shows a data processing flow during normal operation of the present invention.

  When outputting data to the LSI 100, the processor 210 outputs data to the transmission control unit 220 with a transfer capability of 8 bytes / clock (No. 1 in FIG. 2). The transmission control unit 220 divides 8-byte data into 2 bytes × 4 and outputs the data to the data transmission macros 230 to 233. Also, the transmission control unit 220 generates parity data 2 bytes from the output data and outputs it to the parity transmission macro 234 (item number 2 in FIG. 2). Each of the transmission macros 230 to 234 serially converts the 2-byte data received from the transmission control unit 220 and outputs it to each SERDES interface of the link 400 (item number 3 in FIG. 2). Each of the reception macros 140 to 144 of the LSI 100 receives serial data from the link 400, restores the data, and outputs the data to the reception control unit 150 as 2-byte data (No. 5 in FIG. 2). The reception control unit 150 combines the corresponding 2-byte data received from the reception macros 140 to 144, restores the 8-byte data, and outputs the data to the processor 110 (item number 6 in FIG. 2). The processor 110 that has received the 8-byte data executes arbitrary processing (item number 7 in FIG. 2).

  Next, the link adjustment operation will be described. In this embodiment, a SERDES interface that performs serial transfer at high speed is used. In general, in the SERDES interface, it is necessary to periodically perform impedance adjustment in order to cope with a DLL adjustment for improving a clock phase shift between the reception side and the transmission side and a change in temperature and voltage environment. Hereinafter, the DLL adjustment operation from the LSI 200 to the LSI 100 will be described as an example.

  The transmission control unit 220 of the LSI 200 outputs a DLL adjustment instruction signal to each of the transmission macros 230 to 234 individually. The DLL adjustment needs to be performed at regular intervals for each of the divided links 410 to 414, but the transmission control unit 220 transmits each transmission so that the DLL adjustment is not performed simultaneously on the two or more divided links 410 to 413. The DLL adjustment instruction signals are output to the macros 230 to 234 in order. Since the DLL adjustment time is completed within a predetermined time from the start of DLL adjustment, the transmission control unit 220 completes the DLL adjustment by waiting for a predetermined time using the counter circuit or the like from the time when the DLL adjustment instruction signal is output. Recognize that.

  Timings 1 to 6 in FIG. 3 indicate the DLL adjustment operation of the link 400 in the present invention. In FIG. 3, the state of the link 400, the output data of each reception macro 140 to 144, and the data generated by the reception control unit 150 are represented with the vertical axis as the time axis (the downward direction is the direction in which time advances). When the state of the divided links 410 to 414 of the link 400 is “normal operation”, it indicates that the divided links 410 to 414 are in the data transfer state or are in the IDLE state. When the divided links 410 to 414 of the link 400 are in the “DLL adjustment” state, data transfer is not performed and the DLL adjustment pattern is output for a certain period. When the output data of each of the reception macros 140 to 144 is “RM140 reception DATA to RM144 reception DATA”, the data received from the corresponding divided links 410 to 414 is transferred to the reception control unit 150 at 2 bytes / clock. This indicates that it is in the middle or IDLE state. When the output data of each of the reception macros 140 to 144 is “invalid”, it indicates that valid data is not output to the reception control unit 150.

  At timing 1 in FIG. 3, the transmission control unit 220 outputs a DLL adjustment instruction signal to the transmission macro 230. The transmission macro 230 that has received the DLL adjustment instruction signal from the transmission control unit 220 starts a DLL adjustment sequence on the division link 410. In the LSI 100 on the receiving side, when the reception macro 140 detects the DLL adjustment state transfer, it notifies the reception control unit 150 that the data is invalid by a signal. The reception control unit 150 treats data received from the reception macro 140 in the DLL adjustment state as invalid. Since the divided link 410 in the DLL adjustment is a data link, the reception control unit 150 receives each of the received macros 141 to 143 and the parity received macro 144 of the remaining three divided links for data 411 to 413. By performing an exclusive OR (XOR) on the 2-byte data, data for the divided link 410 during the DLL adjustment is generated. The reception control unit 150 treats the generated data as data received from the reception macro 140, merges it with data received from other reception macros 141 to 143, restores the data to 8 bytes, and outputs the data to the processor 110. The reception control unit 150 continues to operate while generating the data of the divided link 410 from the other divided links 411 to 414 as described above during the period in which the divided link 410 is performing the DLL adjustment. When the DLL adjustment of the divided link 410 is completed, the reception macro 140 of the divided link 410 deasserts the data invalid signal output to the reception control unit 150, and resumes data transfer.

  When the DLL adjustment of the divided link 410 is completed, the transmission control unit 220 of the LSI 200 next outputs a DLL adjustment instruction signal to the transmission macro 231 of the divided link 411 (timing 2 in FIG. 3). Similarly, when the DLL adjustment of the division link 411 is completed, the transmission control unit 220 of the LSI 200 next outputs a DLL adjustment instruction signal to the transmission macro 232 of the division link 412 (timing 3 in FIG. 3).

  In addition, when the division link 414 for parity is under DLL adjustment (the case of timing 5 in FIG. 3), each 2-byte data received from the reception macros 140 to 143 of the other four division links 410 to 413 is used. Although parity can be generated, there is no need to supplement the data because it is originally redundant data.

  As described above, the clock phase adjustment for each transmission path is performed at different timings, and the transfer data is complemented by redundant data, so that the clock phase adjustment can be performed without stopping the data transfer. Has the effect of being able to.

  Next, the error recovery operation will be described.

  Error timing 1 in FIG. 3 shows an operation when an intermittent error occurs on the divided link 410. When an error occurs in the division link 410, the reception macro 140 of the receiving LSI 100 detects the error and notifies the reception control unit 150 that the data is invalid by a signal. The reception macro 140 instructs the LSI 200 via the transmission macro 230 to execute the link recovery sequence on the divided link 410. During the execution of the link recovery sequence, data transfer cannot be performed on the divided link 410, and thus the reception macro 140 continues to output a data invalid signal to the reception control unit 150. Note that the link recovery sequence may take several tens to several hundreds of clocks.

  While the divided link 410 is in the data invalid state, the reception control unit 150 generates data of the divided link 410 from the remaining divided links 411 to 414 and continues the operation. Since the data generation method is the same as that when the division link 410 is performing DLL adjustment, the description thereof is omitted. If the execution of the link recovery sequence does not coincide with the link recovery sequence of the other divided links 411 to 414 or the timing of the DLL adjustment sequence, the link recovery sequence can be executed without stopping the data transfer.

  If an error occurs even if the link recovery sequence is performed on the divided link 410, it may be a fixed failure, and the divided link 410 may be blocked. In that case, the reception macro 140 continues to output a data invalid signal to the reception control unit 150. Therefore, when the DLL adjustment or restoration sequence is operated on the other divided links 411 to 414, the data transfer must be stopped, but the data transfer cannot be disabled, and the computer system does not need to be stopped.

  As described above, the clock phase adjustment for each transmission path is performed at different timings, and the transfer data is supplemented with redundant data, so that intermittent errors and fixed errors on the link can be recovered. There is an effect.

  Note that the LSI 100 and the LSI 200 do not have to be a single LSI, and may be divided into a plurality of parts, or may be a board, an apparatus, or an information processing system.

  The present invention is effective in a computer system such as a server that requires high performance and high reliability.

It is a block diagram which shows the structure of the best embodiment of this invention. It is a figure of the data processing flow at the time of normal operation | movement of this invention. It is a figure explaining the operation | movement on the time-axis of the transmission line of this invention.

Explanation of symbols

100 LSI
200 LSI
110 processor 210 processor 120 transmission control unit 220 transmission control unit 130-134 transmission macro 230-234 transmission macro 140-144 reception macro 240-244 reception macro 150 reception control unit 250 reception control unit 300 link 400 link 310-314 divided link 410 ~ 414 Split link

Claims (8)

One or more redundant transmission paths for transferring redundant data for generating transfer data on the receiving side when data transfer is impossible in any of one or more transmission paths for dividing and transferring the transfer data;
It means for performing at different timings in the clock phase adjustment before Kiden sending passage and before Ki冗 length transmission lines, prior Kiden sending passage and before Ki冗 length transmission lines each,
A receiving circuit for notifying that the data to be received is invalid for each transmission path;
A reception control unit that generates the transfer data using the redundant data when any of the reception circuits notifies that the data is invalid.
Data transfer method. The reception circuit, when the clock phase adjustment of the corresponding pre Kiden feed path is performed, and notifies said invalid
2. The data transfer system according to claim 1, wherein: A data transfer system having one or more transmission lines, wherein when the failure of any one of the one or more transmission lines is detected, the transfer data is generated by complementing with the redundant data of the redundant transmission line 3. The data transfer system according to claim 1 or 2, further comprising: a receiving unit configured to perform reception. The redundant data is parity data of transfer data of the one or more transmission paths, and the generation of the transfer data is performed by using the transfer data of the transmission path excluding any of the transmission paths incapable of data transfer and the transfer data. according to claim 1, characterized in that obtained by taking the exclusive oR of the redundant data, or data transfer method according to any one of the three. When data transfer is not possible on one or more transmission paths that divide and transfer the transfer data, transfer data is generated on the receiving side using redundant data transferred on one or more redundant transmission paths. ,
The clock phase adjustment before Kiden sending passage and before Ki冗 length transmission line, running at different timings before Kiden sending passage and before Ki冗 length transmission lines each,
Notifying that the corresponding received data is invalid for each transmission path,
When it is notified that any of the received data is invalid, the transfer data is generated using the redundant data
Data transfer method. If the previous Kiden feed path clock phase adjustment execution is running, you notice that the data to the receiving corresponding is invalid the
6. The data transfer method according to claim 5, wherein: A data transfer method for an interface having one or more transmission paths, wherein when the failure of any one of the one or more transmission paths is detected, the transfer data is complemented with the redundant data of the redundant transmission path. The data transfer method according to claim 5 or 6, wherein the data is generated. The redundant data is parity data of transfer data of the one or more transmission paths, and the generation of the transfer data is performed by using the transfer data of the transmission path excluding any of the transmission paths incapable of data transfer and the transfer data. claim 5 and 6, characterized in that obtained by taking the exclusive oR of the redundant data, or 7 data transfer method according to any one of.

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