JP4854551B2 - Test apparatus for branch prediction circuit of information processing apparatus, test method for branch prediction circuit of information processing apparatus, and test program for branch prediction circuit of information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device, method and program for testing a branch prediction circuit of an information processor, in which verification of the branch prediction circuit can be easily and efficiently performed without performing processing for specifying a branch point and substituting a branch instruction by the other instruction. <P>SOLUTION: In the branch prediction circuit test device 1, a random instruction generation part 11 generates a random instruction sequence, and a test execution control part 12 makes a device 2 of the test object execute the instruction sequence. After completion of execution of the instruction sequence, the control part 12 instructs the generation part 11 to shift the instruction sequence, and the control part 12 makes the device 2 of the test object execute the shifted new instruction sequence. A verification part 13 stores log information every time when the instruction sequence is executed, and compares the log information with an expected value stored in an expected value storage part 132 to verify the operation of the branch prediction circuit 21. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a test technique for a branch prediction circuit of an information processing device, and in particular, causes a device under test to execute a random instruction sequence including a branch instruction, and the device under test based on an execution result of the random instruction sequence. The present invention relates to a test apparatus for a branch prediction circuit of an information processing apparatus, a test method for a branch prediction circuit of an information processing apparatus, and a test program for a branch prediction circuit of the information processing apparatus.

Conventionally, in order to verify a branch prediction circuit, a branch instruction location (branch point) included in an instruction sequence is specified, the branch instruction at the branch point is rewritten to another instruction, the instruction sequence is executed, and branch prediction is performed. Had to be verified to be canceled correctly. Since a branch instruction location (branch point) cannot be specified in a system test using a random instruction sequence, a series of processing (hereinafter referred to as “phantom”) for rewriting a branch instruction included in the random instruction sequence is embedded when generating a random instruction sequence. Then, the random instruction sequence is executed, and the branch prediction circuit is verified based on the execution result.
In addition, as a specific technique for verifying the branch prediction function, the following patent document 1 describes a condition for generating a random instruction sequence, setting a branch destination of a branch instruction in the instruction sequence at random, and comparing with a branch instruction. Test the branch prediction function by setting the instruction to be initialized and the instruction that changes the comparison value to exit the loop repeatedly in the above instruction sequence, and setting the instruction to exit the loop at the time of an unconditional branch instruction. The information processing apparatus test method is described.
Japanese Patent Laid-Open No. 2-115942

Since the technique for verifying the branch prediction circuit by embedding a phantom for rewriting a branch instruction included in a random instruction sequence and executing the instruction when generating a random instruction is the same as the functional test level, the randomness of the test is Lost. In addition, it takes time to rewrite instructions, leading to a decrease in test efficiency.

  The present invention has been made to solve the above problems, and it is possible to easily and efficiently verify a branch prediction circuit without performing a process of specifying a branch point and replacing a branch instruction with another instruction. An object is to provide a test apparatus for a branch prediction circuit of an information processing apparatus, a test method for a branch prediction circuit of an information processing apparatus, and a test program for a branch prediction circuit of the information processing apparatus.

In order to solve the above problems, the present invention solves the above problems as follows.
(1) The correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the storage means stores the information of the branch instruction. An apparatus for testing a branch prediction circuit in an information processing apparatus having a branch prediction circuit for executing an instruction at a branch destination address registered in the storage means without executing the branch instruction when an address is registered Provide. A test apparatus for a branch prediction circuit in the information processing apparatus includes: means for generating a random instruction sequence including a branch instruction; and executing the random instruction sequence by applying the random instruction sequence to the device under test for execution. Thereafter, the random instruction sequence is shifted by a predetermined number of instructions to generate a new instruction sequence in which the address position of the branch instruction included in the executed instruction sequence is updated, and the new instruction sequence is executed again. And a test execution control unit for verifying the operation of the branch prediction circuit of the device under test based on the execution result of the random instruction sequence by the device under test.
(2) The test execution control means, after the new instruction sequence is executed, returns the new instruction sequence to the state before the shift, and the test sequence that has been returned to the state before the shift is tested. Cause the target device to execute.
(3) The test execution control means changes the data defining the branch condition of the branch instruction included in the instruction sequence every time the random instruction sequence is executed.
(4) The verification means, log information storage means for storing log information at the time of the occurrence of the trap, triggered by the occurrence of a trap during the execution of the instruction sequence;
After execution of the instruction sequence, the log information stored in the log information storage unit is compared with an expected value prepared in advance or log information acquired at the previous test, and the execution of the instruction sequence is performed based on the comparison result Comparing means for verifying the results.
(5) The correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the storage means stores the information of the branch instruction A method for testing a branch prediction circuit in an information processing apparatus having a branch prediction circuit that executes an instruction at a branch destination address registered in the storage means without executing the branch instruction when an address is registered Execute. A test method of the branch prediction circuit in the information processing apparatus generates a random instruction sequence including a branch instruction, gives the random instruction sequence to a device under test to be executed, and after executing the random instruction sequence, The random instruction sequence is shifted by a predetermined number of instructions to generate a new instruction sequence in which the address position of the branch instruction included in the executed instruction sequence is updated, and the new instruction sequence is executed again. The operation of the branch prediction circuit of the device under test is verified based on the execution result of the random instruction sequence by the device under test.
(6) Correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the storage means stores the information of the branch instruction A test program for a branch prediction circuit in an information processing apparatus having a branch prediction circuit for executing an instruction at a branch destination address registered in the storage means without executing the branch instruction when an address is registered Provide. A test program for a branch prediction circuit in the information processing apparatus causes a computer to generate a random instruction sequence including a branch instruction and to execute the random instruction sequence by giving the random instruction sequence to a device under test. After the execution of the sequence, the random instruction sequence is shifted by a predetermined number of instructions to generate a new instruction sequence in which the address position of the branch instruction included in the executed instruction sequence is updated, and the new instruction sequence And a process of verifying the operation of the branch prediction circuit of the device under test based on the execution result of the random instruction sequence by the device under test.

According to the present invention, the following effects can be obtained.
(1) In the present invention, a random instruction sequence including a branch instruction is generated and executed by the device under test. After the random instruction sequence is executed, the random instruction sequence is shifted by a predetermined number of instructions. Generate a new instruction sequence in which the address position of the branch instruction included in the executed instruction sequence is updated, cause the device under test to execute the new instruction sequence again, and based on the execution result, The operation of the branch prediction circuit of the target device is verified. Therefore, according to the present invention, by shifting a random instruction string, the address position of the branch instruction included in the random instruction string is updated, and as a result, another instruction is moved to the original address position of the branch instruction. You can create the same state as overwriting. As a result, there is no need to specify a branch point and replace the branch instruction with another instruction, and the branch prediction circuit of the device under test can be verified easily and efficiently.
(2) In the present invention, after the shifted instruction sequence is executed, the new instruction sequence is returned to the state before the shift, and the device under test is executed with the instruction sequence returned to the state before the shift. . Therefore, according to the present invention, for example, whether the log information when the instruction sequence returned to the state before the shift is executed matches the log information when the original instruction sequence before the shift is executed. Thus, the operation of the branch prediction circuit of the device under test can be verified with high accuracy.
(3) The present invention verifies the operation of the branch prediction circuit of the device under test after changing the data defining the branch condition of the branch instruction included in the instruction sequence every time the random instruction sequence is executed. To do. Therefore, according to the present invention, it is possible to verify the operation of the branch prediction circuit of the device under test by repeatedly executing the same instruction sequence while changing the data defining the branch condition. As a result, it is possible to efficiently verify the operation of the branch prediction circuit of the device under test.
(4) The present invention stores log information at the time of the occurrence of a trap triggered by the occurrence of a trap during execution of the instruction sequence, and is prepared in advance with the stored log information after execution of the instruction sequence. The expected value or the log information obtained at the previous test is compared, and the execution result of the instruction sequence is verified based on the comparison result. Therefore, according to the present invention, it is possible to automatically verify whether or not the operation of the branch prediction circuit of the device under test is normal.

FIG. 1 is a diagram showing an example of a system configuration of the present invention.
The branch prediction circuit test device 1 is a processing device that verifies the operation of the branch prediction circuit 21 provided in the device under test 2. The branch prediction circuit test apparatus 1 includes a random instruction generation unit 11, a test execution control unit 12, and a verification unit 13.
The random instruction generation unit 11 generates a random instruction sequence (random instruction sequence) including a branch instruction. The test execution control unit 12 gives the generated random instruction sequence to the instruction execution unit 22 included in the device under test 2 for execution. In addition, after the random instruction sequence is executed, the test execution control unit 12 instructs the random instruction generation unit 11 to shift the random instruction sequence by a predetermined number of instructions and execute the executed instruction sequence. A new instruction sequence in which the address position of the branch instruction included in is updated is generated, and the instruction execution unit 22 is made to execute the new instruction sequence again.

According to an embodiment of the present invention, the test execution control unit 12 further returns the new instruction sequence to the state before the shift and returns to the state before the shift after the new instruction sequence is executed. The instruction execution unit 22 provided in the device under test 2 executes the instruction sequence.
Further, according to one embodiment of the present invention, the test execution control unit 12 includes the instruction execution unit 22 included in the device under test 2 that stores data defining a branch condition of a branch instruction included in the instruction sequence. Change every time a random instruction sequence is executed.

The verification unit 13 verifies the operation of the branch prediction circuit 21 provided in the device under test 2 based on the execution result of the random instruction sequence by the device under test 2.
The verification unit 13 includes a checksum generation unit 131, an expected value storage unit 132, and a comparison unit 133. The checksum generator 131 generates a checksum based on the contents of each register and memory at the time of the trap when the trap is generated during execution of the random instruction sequence, and the checksum of the generated checksum The value is stored as log information. The checksum is, for example, data in a format compressed by adding the contents of each register and memory. The checksum generation unit 131 stores the contents of each register and memory as log information when a hard trap or a soft trap occurs, or at the end of execution of a random instruction sequence regardless of the occurrence of a trap. It may be. The expected value storage unit 132 stores in advance an expected value to be compared with the log information. The comparison unit 133 executes the log information generated by the checksum generation unit 131 and the expected value stored in advance in the expected value storage unit 132 or the log generated during the previous test after the random instruction sequence is executed. Information is compared, and the execution result of the instruction sequence is verified (the operation of the branch prediction circuit 21 is verified) based on the comparison result.

  Note that the functions of the branch prediction circuit test apparatus 1 and the components described above are realized by a CPU and a program executed thereon. The program for realizing the present invention can be stored in a computer-readable recording medium such as a semiconductor memory, a hard disk, a CD-ROM, a DVD, or the like, provided by being recorded in these recording media, or communication. It is provided by transmission / reception using a network via an interface.

The device under test 2 is an information processing device that is a target of verification processing of the branch prediction circuit by the branch prediction circuit test device 1. The device under test 2 includes an instruction execution unit 22 and a branch prediction circuit 21.
The branch prediction circuit 21 stores correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction in the branch prediction management table 211. Further, the branch prediction circuit 21 refers to the branch prediction management table 211 when executing the branch instruction, and executes the branch instruction when the address of the branch instruction is registered in the branch prediction management table 211. Then, the instruction execution unit 22 is caused to execute the instruction at the branch destination address registered in the branch prediction management table 211 as an execution target (perform a branch prediction process). The instruction execution unit 22 fetches the instruction stored in the instruction storage area 100, loads the data stored in the data storage area 101, and executes the instruction.

FIG. 2 is a diagram illustrating an example of a branch instruction and a branch condition of the branch instruction.
As shown in FIG. 2, for example, the branch instruction BRNZ has a branch condition that branches if the value of the target register is not 0, and the branch instruction BRZ is a branch that branches if the value of the target register is 0. The branch instruction BRGZ has a branch condition that branches if the value of the target register is greater than 0, and the branch instruction BRLZ has a branch condition that branches if the value of the target register is less than 0.

FIG. 3 is a diagram for explaining branch prediction processing of the branch prediction circuit provided in the device under test.
As shown in FIG. 3, the branch instruction X is stored at address A of the instruction storage area 100, and the instruction Z is stored at address B, which is the branch destination address of the branch instruction X. Branch prediction processing by the branch prediction circuit 21 is performed according to the following processing steps [1] to [4].
[1]: The instruction execution unit 22 executes the instruction sequence stored in the instruction storage area 100.
[2]: The branch prediction circuit 21 registers the address A, which is the address of the branch instruction X, and the address B, which is the branch destination address branched by the branch instruction X, in the branch prediction management table 211. In the branch prediction management table 211 shown in FIG. 3, a data item called a branch address shows the address of a branch instruction, and a data item called a branch destination address shows a branch destination address branched by a branch instruction.
[3]: The instruction execution unit 22 executes the instruction sequence again.
[4]: The branch prediction circuit 21 refers to the branch prediction management table 211, determines that the address A is the branch instruction X, and executes the instruction Z stored in advance at the address B which is the branch destination address.

  As described above, the branch prediction circuit 21 registers the correspondence information between the address of the branch instruction executed once and the branch address branched by the branch instruction in the branch prediction management table 211, and executes the branch instruction of the same address next time. In this case, the above-described branch prediction process is performed, and the instruction stored in advance at the branch destination address is executed to speed up the process.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In the first embodiment of the present invention, after generating and executing a random instruction sequence including a branch instruction, the random instruction sequence is shifted by a predetermined number of instructions and executed again, and the execution result of the random instruction sequence Based on the above, the operation of the branch prediction circuit is verified.

  FIG. 4 is a diagram showing an example of a test process flow of the branch prediction circuit according to the first embodiment of the present invention. First, the random instruction generation unit 11 of the branch prediction circuit test apparatus 1 generates a random instruction sequence including the branch instruction X as shown in FIG. 5A (step S1). Next, the test execution control unit 12 causes the instruction execution unit 22 of the device under test 2 to execute the generated random instruction sequence (step S2). When the random instruction sequence is executed by the process of step S2, the branch prediction circuit 21 branches the address A which is the address of the branch instruction X and the branch destination by the branch instruction X as shown in FIG. Address B as an address is registered in the branch prediction management table 211.

  Next, after executing the random instruction sequence, the test execution control unit 12 instructs the random instruction generation unit 11 to shift the random instruction sequence by adding one nop instruction to the head of the random instruction sequence. (Step S3). A nop instruction is an instruction that exists as an instruction but does not involve any action. By the process in step S3, for example, a new random instruction sequence in which the random instruction sequence is shifted downward (in the direction in which the address increases) as illustrated in FIG. 5B is generated. Referring to the random instruction sequence shown in FIG. 5B, an instruction C is stored at address A, a branch instruction X is stored at address A ′, and an instruction Y that is a branch destination instruction of branch instruction X is stored at address B ′. Is stored.

  Next, the test execution control unit 12 causes the instruction execution unit 22 to execute the new random instruction sequence again (step S4). At the time of execution of a new random instruction sequence in step S4, the branch prediction circuit 21 searches the address A registered in the branch prediction management table 211 shown in FIG. However, as shown in FIG. 5B, the instruction C is replaced with the branch instruction X at the address A, so that the branch prediction process by the branch prediction circuit 21 is canceled and the instruction C is executed. When a new random instruction sequence is executed by the process of step S4, the branch prediction circuit 21 is the address of the branch instruction X included in the new random instruction sequence as shown in FIG. 6B. Address A ′ and address B ′, which is a branch destination address to be branched by the branch instruction X, are registered in the branch prediction management table 211.

  Next, the test execution control unit 12 instructs the random command generation unit 11 to shift the random command sequence by adding one nop command to the random command sequence executed in step S4 (step S5). . By the processing in step S5, for example, a new random instruction sequence in which the random instruction sequence executed in step S4 is shifted downward is generated as shown in FIG. Referring to the random instruction sequence shown in FIG. 5C, an instruction C is stored at address A ', a branch instruction X is stored at address A ", and an instruction that is a branch destination instruction of branch instruction X at address B". Y is stored.

  Next, the test execution control unit 12 causes the instruction execution unit 22 to execute again the new random instruction sequence generated in step S5 (step S6). At the time of execution of the new random instruction sequence, the branch prediction circuit 21 searches for the address A ′ registered in the branch prediction management table 211 shown in FIG. However, as shown in FIG. 5C, since the instruction C is stored in place of the branch instruction X at the address A ′, the branch prediction process by the branch prediction circuit 21 is canceled and the instruction C is executed. . When a new random instruction sequence is executed by the process of step S6, the branch prediction circuit 21 is the address of the branch instruction X included in the new random instruction sequence, as shown in FIG. 6C. The address A ″ and the address B ″, which is the branch destination address branched by the branch instruction X, are registered in the branch prediction management table 211. Processing similar to the above-described random instruction sequence shift processing (steps S3 and S5) and the shifted instruction sequence execution processing (steps S4 and S6) is repeated until the random instruction sequence is shifted N times.

  For example, each time a random instruction sequence is executed according to the processing flow shown in FIG. 4 described above, the verification unit 13 of the branch prediction circuit test apparatus 1 logs the contents of each register and memory at the end of execution of the instruction sequence. And the log information and the expected value stored in the expected value storage unit 132 are compared, and based on the comparison result, it is verified whether the branch prediction process has been canceled.

  Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment of the present invention, a random instruction sequence including a branch instruction is generated and executed, the random instruction sequence is shifted by a predetermined number of instructions, and then the executed instruction sequence is shifted. Return to the previous instruction sequence and execute again.

  FIG. 7 is a diagram showing an example of a test process flow of the branch prediction circuit according to the second embodiment of the present invention. First, the random instruction generation unit 11 of the branch prediction circuit test apparatus 1 generates a random instruction sequence including the branch instruction X as shown in FIG. 8A (step S11). Next, the test execution control unit 12 causes the instruction execution unit 22 of the device under test 2 to execute the generated random instruction sequence (step S12). When the random instruction sequence is executed by the processing of step S12, the branch prediction circuit 21 branches the address A which is the address of the branch instruction X and the branch destination by the branch instruction X as shown in FIG. Address B as an address is registered in the branch prediction management table 211.

  Next, after executing the random instruction sequence, the test execution control unit 12 instructs the random instruction generation unit 11 to shift the random instruction sequence by adding one nop instruction to the head of the random instruction sequence. (Step S13). By the processing in step S13, for example, a new random instruction sequence in which the random instruction sequence is shifted downward (in the direction in which the address increases) as illustrated in FIG. 8B is generated. Referring to the random instruction sequence shown in FIG. 8B, the instruction C is stored at address A, the branch instruction X is stored at address A ′, and the instruction Y that is the branch destination instruction of the branch instruction X is stored at address B ′. Is stored.

  Next, the test execution control unit 12 causes the instruction execution unit 22 to execute the new random instruction sequence again (step S14). At the time of executing a new random instruction sequence in step S14, the branch prediction circuit 21 temporarily searches for the address A registered in the branch prediction management table 211 shown in FIG. However, as shown in FIG. 8B, since the instruction C is stored in place of the branch instruction X at the address A, the branch prediction process by the branch prediction circuit 21 is canceled and the instruction C is executed. When a new random instruction sequence is executed by the process of step S14, the branch prediction circuit 21 is the address of the branch instruction X included in the new random instruction sequence as shown in FIG. 9B. Address A ′ and address B ′, which is a branch destination address to be branched by the branch instruction X, are registered in the branch prediction management table 211.

  Next, the test execution control unit 12 instructs the random command generation unit 11 to delete one nop command from the random command sequence executed in step S14, thereby shifting the random command sequence upward. (Step S15). By the processing in step S15, for example, an instruction sequence having the same state as the instruction sequence executed in step S12 (instruction sequence shown in FIG. 8A) as shown in FIG. 8C is generated. That is, the instruction sequence shown in FIG. 8B returns to the original state before the shift. Referring to the random instruction sequence shown in FIG. 8C, a branch instruction X is stored at address A, and an instruction Y that is a branch destination instruction of branch instruction X is stored at address B.

  Next, the test execution control unit 12 causes the instruction execution unit 22 to execute again the random instruction sequence that has been returned to the original state by the process of step S15 (step S16). As shown in FIG. 8C, since the branch instruction X is stored at address A, the branch instruction X is executed. When the random instruction sequence is executed by the process of step S16, the branch prediction circuit 21 receives the address A which is the address of the branch instruction X included in the executed random instruction sequence, as shown in FIG. 9C. The B address that is the branch destination address to be branched by the branch instruction X is registered in the branch prediction management table 211.

  For example, each time a random instruction sequence is executed according to the processing flow shown in FIG. 7 described above, the verification unit 13 of the branch prediction circuit test apparatus 1 logs the contents of each register and memory at the end of execution of the instruction sequence. Remember as. Then, for example, the verification unit 13 compares the log information when the random instruction sequence is shifted downward and is executed with the expected value stored in the expected value storage unit 132, and branches based on the comparison result. Verify whether the prediction process has been canceled. Further, the verification unit 13 may, for example, log information when the random instruction sequence shifted and executed in the downward direction is returned to the original instruction sequence before the shift and executed, and the original information before the shift It is determined whether or not the log information when the instruction sequence is executed matches, and the operation of the branch prediction circuit 21 is verified based on the determination result.

  Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment of the present invention, the data defining the branch condition of the branch instruction included in the random instruction sequence is changed every time the random instruction sequence is executed.

  FIG. 10 is a diagram illustrating an example of a test processing flow of the branch prediction circuit according to the third embodiment of the present invention. First, the random instruction generation unit 11 of the branch prediction circuit test apparatus 3 generates a random instruction sequence including the branch instruction X as shown in FIG. 11A (step S21). Referring to the generated instruction sequence shown in FIG. 10A, branch instruction X is stored at address A of instruction storage area 100, and instruction C is stored at address A ', which is an address before address A. Yes. Referring to FIG. 12 showing the processing flow of the instruction C and the branch instruction X, the instruction C is an instruction for loading the data stored in the address C in the data storage area 101 in FIG. The branch instruction X is a branch instruction in which the branch destination is address B when the data value loaded by the instruction C is 0, and the branch destination is address A + 1 when the data value loaded by the instruction C is not 0. .

  Next, the test execution control unit 12 causes the instruction execution unit 22 of the device under test 2 to execute the generated random instruction sequence (step S22). Here, since data A having a value of 0 is stored at address C of the data storage area 101 in FIG. 11A, the value of data loaded by the instruction C is 0. Therefore, when the branch instruction X is executed, the program branches to the B address according to the processing flow shown in FIG. The branch prediction circuit 21 registers the address A, which is the address of the branch instruction X, and the address B, which is the branch destination address branched by the branch instruction X, in the branch prediction management table 211.

  Next, the test execution control unit 12 changes data at address C in the data storage area 101, which is data defining the branch condition of the branch instruction X (step S23). For example, as shown in FIG. 11B, instead of data A, data W having a value of 10 is stored at address C in data storage area 101. Then, the test execution control unit 12 causes the instruction execution unit 22 to execute again the random instruction sequence executed in step S22 (step S24). When the branch instruction X included in the random instruction sequence is executed, the value of the data at the address C that defines the branch condition of the branch instruction X is changed to 10. Therefore, according to the processing flow shown in FIG. Branch to the street address. Since the branch direction of the branch instruction X is changed from the B address to the A + 1 address, the branch prediction process by the branch prediction circuit 21 is cancelled.

  For example, each time a random instruction sequence is executed according to the processing flow shown in FIG. 10 described above, the verification unit 13 of the branch prediction circuit test apparatus 1 logs the contents of each register and memory at the end of execution of the instruction sequence. And the log information is compared with the expected value stored in the expected value storage unit 132, and it is verified whether the branch prediction process is canceled based on the comparison result.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment of the present invention, when a trap occurs during execution of an instruction sequence, log information at the time of the occurrence of the trap is generated, and after the execution of the instruction sequence, the generated log information And the expected value stored in the storage means in advance or the log information generated during the previous test, and the execution result of the instruction sequence is verified based on the comparison result.

  In the fourth embodiment of the present invention, when the random instruction generation unit 11 generates a random instruction sequence, as shown in FIG. 13, for each predetermined instruction number in the random instruction sequence (for example, 1024 instructions). Every time). Then, when the checksum generation unit 131 of the verification unit 13 generates a hard trap or the soft trap during the execution of the random instruction sequence, the contents of each register and memory at the time of the trap generation are used as log information. Remember. Each time a trap occurs, the checksum generation unit 131 generates, for example, an 8-byte checksum based on the contents of each register and memory, and stores the checksum value as log information shown in FIG. You may do it. Further, when the final trap occurs, the checksum generation unit 131 integrates all checksums created each time the trap occurs, and the total checksum (total checksum200) value shown in FIG. And the value of the total checksum 200 may be stored as log information.

  After execution of the random instruction sequence, the comparison unit 133 of the verification unit 13 compares the stored log information with the expected value stored in the expected value storage unit 132 in advance, and based on the comparison result, the random number The execution result of the instruction sequence is verified. For example, the comparison unit 133 compares the total checksum 200 shown in FIG. 13 with the expected value 201 to verify the execution result of the random instruction sequence.

According to an embodiment of the present invention, a plurality of expected values associated with each trap are stored in the expected value storage unit 132 in advance, and the comparison unit 133 checks the checksum generation unit 131 when a trap occurs. The checksum value generated in step (1) may be compared with the expected value associated with the trap among the plurality of expected values stored in the expected value storage unit 132.
Further, according to an embodiment of the present invention, the instruction sequence execution unit 21 repeatedly executes the same instruction sequence, and the comparison unit 133 includes log information generated after execution of a certain instruction sequence and the past of the instruction sequence. The log information generated at the time of execution may be compared, and the execution result of the instruction sequence may be verified based on the comparison result.

Embodiments of the present invention will be described below with reference to FIGS.
FIG. 14 is a diagram illustrating a data configuration example of the expected value storage unit according to the embodiment of the present invention. In this example, the expected value storage unit 132 has data items such as data, shift, and expected value. In the data, the number of data updates that defines the branch condition of the branch instruction included in the instruction sequence to be executed is set. The number of shifts of the instruction sequence is set for the shift. As the expected value, an expected value associated with the data update count and the instruction sequence shift count is set.

  FIG. 15 is a diagram illustrating updating of data stored in the data storage area. The test execution control unit 12 of the branch prediction circuit test apparatus 1 designates each data included in the random data as shown in FIG. 15 by the X pointer, and determines the branch instruction included in the instruction sequence to be executed. Each designated data is set at an address that defines a branch condition. X is a variable indicating an address that defines the branch condition of the branch instruction. Random data is data composed of a plurality of random data. The test execution control unit 12 updates the data defining the branch condition of the branch instruction by sequentially changing the data designated by the X pointer. .

FIG. 16 is a diagram illustrating a test processing flow of the branch prediction circuit of the information processing apparatus according to the embodiment of the present invention. First, the random instruction generation unit 11 generates a random instruction sequence, and the test execution control unit 12 generates random data as shown in FIG. 15 (step S31). Next, the test execution control unit 12 designates the leading data of the random data with the X pointer (step S32). The test execution control unit 12 initializes the data area (step S33). The data area is a work area on the memory when a random instruction is executed.
Then, the instruction sequence execution unit 31 executes a random instruction sequence (step S33). If a trap occurs during the execution of the random instruction sequence, the checksum generator 131 generates a checksum (step S35).

  Next, the comparison unit 133 compares the checksum generated in step S35 with the expected value stored in advance in the expected value storage unit 132 shown in FIG. 14 (step S36). The test execution control unit 12 determines whether or not the random instruction sequence is shifted N times downward and executed (step S37). When the test execution control unit 12 determines that the random instruction sequence is not shifted and executed N times downward, the test execution control unit 12 instructs the random instruction generation unit 11 to start the random instruction sequence. The random instruction sequence is shifted downward by one instruction by adding one nop instruction to (step S38), and the process returns to step S33.

When the test execution control unit 12 determines that the random instruction sequence is shifted N times downward and executed, the test execution control unit 12 initializes the data storage area 101 (step S39), and the instruction execution unit 22 Then, a random instruction sequence is executed (step S40). If a trap occurs during the execution of the random instruction sequence, the checksum generation unit 131 generates a checksum (step S41).
Next, the comparison unit 133 compares the checksum generated in step S41 with the expected value stored in advance in the expected value storage unit 132 shown in FIG. 14 (step S42). The test execution control unit 12 determines whether or not the random instruction sequence has been shifted N times in the upward direction (step S43). When the test execution control unit 12 determines that the random instruction sequence is not shifted and executed N times upward, the test execution control unit 12 instructs the random instruction generation unit 11 to perform a random instruction sequence nop. By deleting one instruction, the random instruction sequence is shifted upward by one instruction (step S44), and the process returns to step S39.

When the test execution control unit 12 determines that the random instruction sequence is shifted N times in the upward direction and executed, the test execution control unit 12 stores the data defining the branch condition of the branch instruction included in the random instruction sequence as M It is determined whether or not it has been updated once (step S45). If the test execution control unit 12 determines that the data defining the branch condition of the branch instruction included in the random instruction sequence has been updated M times, the process ends.
When the test execution control unit 12 determines that the data defining the branch condition of the branch instruction included in the random instruction sequence has not been updated M times, the test execution control unit 12 updates the X pointer ( According to the designation of the X pointer, other data is set to an address that defines the branch condition of the branch instruction), and the process returns to step S33.

As can be understood from the above, the features of the embodiment of the present invention are described as follows.
(Appendix 1) Correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the branch instruction is stored in the storage means. The branch prediction circuit test apparatus in the information processing apparatus having the branch prediction circuit that executes the instruction of the branch destination address registered in the storage means without executing the branch instruction when the address is registered Because
Means for generating a random instruction sequence including branch instructions;
The random instruction sequence is given to the device under test for execution, and after execution of the random instruction sequence, the random instruction sequence is shifted by a predetermined number of instructions, and the address position of the branch instruction included in the executed instruction sequence A test execution control means for generating a new instruction sequence updated and executing the new instruction sequence again;
A test apparatus for a branch prediction circuit of an information processing apparatus, comprising: verification means for verifying an operation of a branch prediction circuit of the device under test based on an execution result of the random instruction sequence by the device under test .

(Appendix 2) The test execution control means further returns the new instruction sequence to the state before the shift after the execution of the new instruction sequence, and receives the instruction sequence that has been returned to the state before the shift. The apparatus for testing a branch prediction circuit of an information processing apparatus according to appendix 1, wherein the apparatus to be tested is executed.

(Additional remark 3) The said test execution control means changes the data which prescribes | regulates the branch conditions of the branch instruction contained in the said instruction sequence every time the said random instruction sequence is executed to the additional notes 1 or 2 A test apparatus for a branch prediction circuit of the information processing apparatus described.

(Appendix 4) The verification means
Log information generating means for generating log information at the time of the occurrence of a trap, triggered by the occurrence of a trap during execution of the instruction sequence;
After the execution of the instruction sequence, the generated log information is compared with the expected value stored in advance in the storage means or the log information generated during the previous test, and the execution result of the instruction sequence is based on the comparison result. 4. A test apparatus for a branch prediction circuit of an information processing apparatus according to appendix 1, 2, or appendix 3, characterized by comprising comparison means for verifying.

(Supplementary Note 5) Correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the branch instruction is stored in the storage means. Branch address prediction circuit test method in an information processing apparatus having a branch prediction circuit that executes an instruction at a branch destination address registered in the storage means without executing the branch instruction when the address is registered Because
Generate a random instruction sequence including branch instructions,
The random instruction sequence is given to the device under test for execution, and after execution of the random instruction sequence, the random instruction sequence is shifted by a predetermined number to update the address position of the branch instruction included in the executed instruction sequence. Generating a new instruction sequence, executing the new instruction sequence again,
A test method for a branch prediction circuit of an information processing device, wherein the operation of the branch prediction circuit of the device under test is verified based on an execution result of the random instruction sequence by the device under test.

(Supplementary note 6) After the new instruction sequence is executed, the new instruction sequence is returned to the state before the shift, and the apparatus under test is executed with the instruction sequence returned to the state before the shift. The test method of the branch prediction circuit of the information processing apparatus according to appendix 5.

(Supplementary note 7) The branch of the information processing apparatus according to Supplementary note 5 or 6, wherein the data defining the branch condition of the branch instruction included in the instruction sequence is changed every time the random instruction sequence is executed. Test method for prediction circuit.

(Supplementary Note 8) Correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the branch instruction is stored in the storage means. Branch address prediction circuit test program in an information processing apparatus having a branch prediction circuit for executing an instruction at a branch destination address registered in the storage means without executing the branch instruction when the address of the information is registered Because
On the computer,
Processing for generating a random instruction sequence including a branch instruction;
The random instruction sequence is given to the device under test for execution, and after execution of the random instruction sequence, the random instruction sequence is shifted by a predetermined number to update the address position of the branch instruction included in the executed instruction sequence. Generating a new instruction sequence and executing the new instruction sequence again;
A test program for a branch prediction circuit of an information processing apparatus, which executes a process of verifying an operation of a branch prediction circuit of the device under test based on an execution result of the random instruction sequence by the device under test.

(Supplementary Note 9) The process of executing the new instruction sequence again is such that after the new instruction sequence is executed, the new instruction sequence is returned to the state before the shift, and returned to the state before the shift. 9. A test program for a branch prediction circuit of an information processing apparatus according to appendix 8, wherein the instruction sequence is executed by a device under test.

(Additional remark 10) The process of re-executing a new instruction sequence changes the data defining the branch condition of the branch instruction included in the instruction sequence every time the random instruction sequence is executed. Or a test program for the branch prediction circuit of the information processing apparatus according to attachment 9.

  As described above, according to the present invention, by shifting the random instruction sequence, the address position of the branch instruction included in the random instruction sequence is updated, and as a result, the original address position of the branch instruction is changed. You can create the same state as overwriting the command. As a result, there is no need to specify a branch point and replace the branch instruction with another instruction, and the branch prediction circuit of the device under test can be verified easily and efficiently. Further, according to the present invention, after the shifted instruction sequence is executed, the new instruction sequence is returned to the state before the shift, and the device under test is executed with the instruction sequence returned to the state before the shift. Therefore, according to the present invention, for example, it is verified whether the log information when the instruction sequence returned to the state before the shift is executed matches the log information when the original instruction sequence is executed. As a result, the operation of the branch prediction circuit of the device under test can be verified with high accuracy.

Further, according to the present invention, the operation of the branch prediction circuit of the device under test can be verified by repeatedly executing the same instruction sequence after changing the data defining the branch condition. As a result, it is possible to efficiently verify the operation of the branch prediction circuit of the device under test.
Further, the present invention stores log information at the time of the occurrence of a trap when a trap occurs during execution of an instruction sequence, and is prepared in advance with the stored log information after execution of the instruction sequence. The expected value or the log information acquired during the previous test is compared, and the execution result of the instruction sequence is verified based on the comparison result. Therefore, according to the present invention, it is possible to automatically verify whether or not the operation of the branch prediction circuit of the device under test is normal.

It is a figure which shows an example of the system configuration | structure of this invention. It is a figure which shows an example of a branch instruction and the branch conditions of the branch instruction. It is a figure explaining the operation | movement process of the branch prediction circuit with which a to-be-tested apparatus is provided. It is a figure which shows an example of the test processing flow of the branch prediction circuit which concerns on the 1st Embodiment of this invention. It is a figure (1) which shows a random instruction sequence. It is a figure (1) which shows the example of the address of a branch instruction registered in a branch prediction management table, and a branch destination address. It is a figure which shows an example of the test processing flow of the branch prediction circuit which concerns on the 2nd Embodiment of this invention. It is a figure (2) which shows a random instruction sequence. It is a figure (2) which shows the example of the address of a branch instruction registered in a branch prediction management table, and a branch destination address. It is a figure which shows an example of the test processing flow of the branch prediction circuit which concerns on the 3rd Embodiment of this invention. It is a figure (3) which shows a random instruction sequence. The figure which shows the processing flow of the instruction C and the branch instruction X It is a figure explaining the 4th Embodiment of this invention. It is a figure which shows the data structural example of the expected value memory | storage part which concerns on the Example of this invention. It is a figure which shows the update of the data stored in the data storage area. It is a figure which shows the test processing flow of the branch prediction circuit of the information processing apparatus which concerns on the Example of this invention. It is a figure which shows the test method of the conventional branch prediction circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Branch prediction circuit test apparatus 11 Random instruction generation part 12 Test execution control part 13 Verification part 21 Branch prediction circuit 22 Instruction execution part 100 Instruction storage area 101 Data storage area 131 Checksum generation part 132 Expected value storage part 133 Comparison part 200 Total checksum
201 Expected value 211 Branch prediction management table

Claims (6)

The correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the address of the branch instruction is registered in the storage means A branch prediction circuit test apparatus in an information processing apparatus having a branch prediction circuit for executing an instruction of a branch destination address registered in the storage means without executing the branch instruction,
Means for generating a random instruction sequence including branch instructions;
A branch instruction included in the executed instruction sequence by shifting the random instruction sequence by a predetermined number of instructions after the random instruction sequence is executed by giving the device under test the random instruction sequence A test execution control means for generating a new instruction sequence in which the address position of is updated and executing the new instruction sequence again;
A test of a branch prediction circuit of an information processing device, comprising: verification means for verifying an operation of a branch prediction circuit of the device under test based on a result of execution of the random instruction sequence by the device under test apparatus. The test execution control unit further returns the new instruction sequence to the state before the shift after the new instruction sequence is executed, and the instruction sequence returned to the state before the shift to the device under test. The branch prediction circuit test apparatus for an information processing apparatus according to claim 1, wherein the test apparatus is executed. 3. The test execution control unit changes data defining a branch condition of a branch instruction included in the instruction sequence every time the random instruction sequence is executed. Test apparatus for branch prediction circuit of information processing apparatus. The verification means is
Log information generating means for generating log information at the time of the occurrence of a trap, triggered by the occurrence of a trap during execution of the instruction sequence;
After the execution of the instruction sequence, the generated log information is compared with the expected value stored in advance in the storage means or the log information generated during the previous test, and the execution result of the instruction sequence is based on the comparison result. 4. A test apparatus for a branch prediction circuit of an information processing apparatus according to claim 1, 2 or 3, further comprising a comparison means for verifying. The correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the address of the branch instruction is registered in the storage means A branch prediction circuit test method in an information processing apparatus having a branch prediction circuit for executing an instruction of a branch destination address registered in the storage means without executing the branch instruction,
Generate a random instruction sequence including branch instructions,
The random instruction sequence is given to the device under test for execution, and after execution of the random instruction sequence, the random instruction sequence is shifted by a predetermined number, and the address position of the branch instruction included in the executed instruction sequence Generate a new instruction sequence updated, and execute the new instruction sequence again.
A test method for a branch prediction circuit of an information processing apparatus, comprising: verifying an operation of a branch prediction circuit of the device under test based on an execution result of the random instruction sequence by the device under test. The correspondence information between the address of the branch instruction and the branch destination address branched by the branch instruction is stored in the storage means, and when executing the branch instruction, the storage means is referred to and the address of the branch instruction is registered in the storage means A branch prediction circuit test program in an information processing apparatus having a branch prediction circuit for executing an instruction of a branch destination address registered in the storage means without executing the branch instruction,
On the computer,
A process for generating a random instruction sequence including a branch instruction;
The random instruction sequence is given to the device under test for execution, and after execution of the random instruction sequence, the random instruction sequence is shifted by a predetermined number, and the address position of the branch instruction included in the executed instruction sequence Generating a new instruction sequence updated and executing the new instruction sequence again;
A test program for a branch prediction circuit of an information processing apparatus, which executes a process for verifying an operation of a branch prediction circuit of the device under test based on an execution result of the random instruction sequence by the device under test .

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