JP4855846B2 - Digital demodulator - Google Patents

Description

  The present invention relates to a digital demodulator that demodulates digital data contained in a modulation signal from a baseband signal obtained by multiplying a modulation signal input from the outside with a reproduction carrier, and more specifically, modulation of MSK or GMSK. The present invention relates to a digital demodulator suitable for demodulating the digital data based on a synchronous detection method using a Costas circuit from a modulated signal obtained by modulating digital data as a frequency shift component by the method.

  Conventionally, when demodulating digital data from a modulated signal modulated with digital data as a frequency shift component by MSK (Minimum Shift Keying) or GMSK (Gaussian-filtered MSK) modulation method, synchronous detection method by Costas circuit is: Since demodulation performance is superior to other detection methods (for example, delay detection method, frequency detection method), it is adopted in digital demodulation devices in many communication devices.

  In this case, the Costas circuit of the digital demodulator generates the first baseband signal by performing synchronous detection by multiplying the input modulation signal by a reproduction carrier having substantially the same frequency as the carrier of the modulation signal. On the other hand, a second baseband signal is generated by performing synchronous detection by multiplying the modulated signal by a signal obtained by shifting the phase of the reproduction carrier by 90 °. Then, the first and second baseband signals are respectively passed through a low-pass filter (LPF), and unnecessary signal components are removed and converted into an I signal and a Q signal.

  The clock recovery unit of the digital demodulator generates a recovered clock that is phase-synchronized with a signal obtained by multiplying the I signal and the Q signal (hereinafter also referred to as an IQ product signal). A frequency-divided clock obtained by frequency-dividing is output to the Costas circuit.

  The phase comparison unit of the Costas circuit generates a voltage corresponding to the phase error between the IQ product signal and the divided clock as a control voltage, and supplies the control voltage to a VCO (voltage controlled oscillator) via the LPF. The VCO outputs a reproduction carrier corresponding to the input control voltage.

  Therefore, in the Costas circuit, a PLL (Phase Locked Loop) circuit related to the reproduced carrier is configured, and the reproduced carrier is phase-synchronized with the carrier of the modulated signal by the PLL circuit, and as a result, the modulated signal is reproduced as the reproduced signal. The frequency can be pulled by the carrier.

  The data reproduction unit of the digital demodulator reproduces (demodulates) digital data from the I signal and the Q signal using the reproduction clock.

  The phase comparison unit described above includes a multiplication type comparison circuit, and a phase error between the IQ product signal and the divided clock, in other words, the transmission clock of the modulation signal included in the IQ product signal and the divided clock. A control voltage corresponding to the phase error is output to the VCO. Therefore, the oscillation frequency (reproduced carrier frequency) of the VCO changes due to a temperature change of the circuit constant of the VCO, aged deterioration of the VCO, etc., and a frequency error between the modulated signal carrier and the regenerated carrier increases. When the frequency of the reproduced carrier is out of synchronization with the frequency of the carrier of the modulated signal, the configuration of the Costas circuit (PLL circuit) cannot synchronize the frequency of the carrier of the modulated signal and the reproduced carrier.

  In view of this, the digital demodulator disclosed in Patent Document 1 monitors the digital data demodulated from the baseband signal and superimposes a predetermined sawtooth voltage on the control voltage when it is determined that frequency synchronization is not achieved. The oscillation frequency (reproduced carrier frequency) of the VCO is corrected by supplying it to the VCO.

JP-A-6-216769

  However, in the digital demodulator disclosed in Patent Document 1, since the sawtooth voltage is a voltage whose voltage value gradually increases with time, the reproduced carrier is frequency-synchronized with the carrier of the modulation signal. May take a long time.

  The present invention provides a correction voltage corresponding to the frequency error when the frequency error between the carrier of the modulation signal and the reproduction carrier becomes large and the frequency of the reproduction carrier is out of synchronization with the frequency of the carrier of the modulation signal. It is an object of the present invention to provide a digital demodulator capable of performing frequency synchronization of the reproduced carrier with the carrier of the modulated signal more reliably and in a short time by detecting uniquely.

  The digital demodulator according to the present invention includes a VCO that outputs a reproduction carrier having substantially the same frequency as the modulation signal in response to the supply of the control voltage, and the modulation signal when the modulation signal is input from the outside. Based on the baseband signal obtained by multiplying the regenerative carrier and performing synchronous detection, the transmission clock of the modulation signal and the frequency division obtained by dividing the regenerative clock necessary for regenerating digital data from the baseband signal In the digital demodulator comprising: a Costas circuit that synchronizes the phase of the carrier of the modulated signal and the regenerated carrier by supplying a voltage corresponding to a phase error with a clock to the VCO as the control voltage. Whether the frequency of the modulated signal is deviated from the frequency of the carrier of the modulated signal. And a frequency correction circuit for supplying a voltage corresponding to a frequency error between the carrier of the modulated signal and the reproduction carrier to the VCO as a correction voltage when the rear and the reproduction carrier are not synchronized in frequency. To do.

  According to this configuration, since the frequency correction circuit directly monitors the frequency of the reproduction carrier, when it is determined that the frequency synchronization of the carrier of the modulation signal and the reproduction carrier is not achieved, The correction voltage can be supplied to the VCO to correct the frequency of the reproduction carrier.

  As a result, the present invention increases the frequency error between the carrier of the modulated signal and the reproduced carrier compared to the prior art that determines the frequency synchronization based on the monitoring of the demodulated digital data, and the carrier of the modulated signal. When the frequency of the reproduction carrier is out of synchronization with the frequency of the reproduction carrier, the correction voltage corresponding to the frequency error is uniquely detected, so that the reproduction carrier can be converted into the carrier of the modulation signal more reliably and in a short time. Frequency synchronization can be achieved.

  Therefore, according to the present invention, it is possible to realize a digital demodulation apparatus of a synchronous detection system that is not easily affected by the temperature change of the circuit constant of the VCO and the secular change of the VCO.

  According to the present invention, when the frequency error between the carrier of the modulation signal and the reproduction carrier becomes large and the frequency of the reproduction carrier is out of synchronization with the frequency of the carrier of the modulation signal, the correction corresponding to the frequency error is performed. By uniquely detecting the voltage, the reproduction carrier can be frequency-synchronized with the carrier of the modulation signal more reliably and in a short time.

  A preferred embodiment of a digital demodulator according to the present invention will be given and described below with reference to the accompanying drawings. Prior to the description, the configuration of the digital demodulator which is a premise of the present embodiment and its problems Will be described with reference to FIGS.

  FIG. 1 is a block diagram of a digital demodulator 10 which is a premise of the present embodiment.

  The digital demodulator 10 demodulates a modulation signal (a signal obtained by modulating the digital data by the MSK or GMSK modulation method) obtained by modulating the digital data as a frequency shift component, and obtains the digital data (not shown). It is a device mounted in the machine and comprises a level conversion unit 12, a Costas circuit 13, a data recovery unit 24, a crystal oscillator 30, and a clock recovery unit 32. The Costas circuit 13 includes multipliers 14, 18, 26, LPF 16 , 20, 34, 90 ° phase shifter 22, phase comparator 28, VCO 36, and level converter 38.

  In the digital demodulator 10, the multipliers 14, 18, 26, the LPFs 16, 20, the 90 ° phase shift unit 22 and the phase comparison unit 28, the data recovery unit 24, and the clock recovery unit 32 included in the Costas circuit 13. Is a digital circuit 40 composed of an integrated circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

  Here, when a modulated signal transmitted from a transmitter (not shown) via radio or the like is received by the receiver, and this modulated signal is input to the digital demodulator 10, the level converter 12 Is converted to a signal level at which the digital circuit 40 can operate (for example, converted from a zero level to a signal level of several [V]) and output to the digital circuit 40. In other words, the analog modulation signal input to the digital demodulator 10 is converted into a digital modulation signal by the level converter 12.

  The VCO 36 outputs a reproduction carrier having a predetermined frequency to the level conversion unit 38 in accordance with the DC control voltage supplied from the digital circuit 40. In this case, the reproduction carrier output from the VCO 36 is an analog signal having substantially the same frequency (oscillation frequency) as the frequency of the carrier of the modulation signal. The level conversion unit 38 converts the reproduction carrier into a signal level at which the digital circuit 40 can operate and outputs the signal level to the digital circuit 40. That is, the reproduction carrier of the analog signal is converted into the reproduction carrier of the digital signal (pulse signal) by the level conversion unit 38 as in the case of the modulation signal.

  The multiplier 14 multiplies the modulation signal input via the level conversion unit 12 and the reproduction carrier input from the VCO 36 via the level conversion unit 38 to generate a first baseband signal. The 90 ° phase shift unit 22 converts the reproduction carrier from the level conversion unit 38 into a signal whose phase is shifted by 90 °, and outputs the signal to the multiplier 18. The multiplier 18 shifts the modulated signal and the 90 ° phase shift by 90 °. The second baseband signal is generated by multiplying the signal from the unit 22. That is, the multipliers 14 and 18 generate the first and second baseband signals from the modulated signal by synchronous detection using the reproduced carrier.

  The first baseband signal is converted to an I signal after unnecessary signal components are removed by the LPF 16 and output to the data reproducing unit 24 and the multiplier 26. The second baseband signal is converted to a Q signal after unnecessary signal components are removed by the LPF 20 and output to the data reproduction unit 24 and the multiplier 26. The multiplier 26 multiplies the I signal and the Q signal to generate an IQ product signal and outputs it to the phase comparison unit 28 and the clock recovery unit 32.

  The crystal oscillator 30 is an oscillator that can generate a pulse signal (clock) having a predetermined oscillation frequency with higher accuracy than the reproduction clock output from the VCO 36, and outputs the clock to the clock reproduction unit 32.

  The clock recovery unit 32 divides the clock input from the crystal oscillator 30 to be phase-synchronized with the I signal (first baseband signal), the Q signal (second baseband signal), and the IQ product signal, and A data reproduction unit 24 generates a reproduction clock necessary for reproducing digital data from the I signal and the Q signal, and outputs the reproduction clock to the data reproduction unit 24 and the outside. In this case, the reproduction clock is a clock pulse that is phase-synchronized with the transmission clock of the modulation signal and has substantially the same frequency fb as the transmission clock. Further, the clock recovery unit 32 divides the recovered clock by two to generate a frequency-divided clock that is phase-synchronized with the IQ product signal and has substantially the same frequency fb / 2 as the IQ product signal. It outputs to the comparison part 28.

  The phase comparator 28 outputs a signal corresponding to the phase error between the IQ product signal from the multiplier 26 and the frequency-divided clock from the clock recovery unit 32 as an error signal. In this case, if the IQ product signal includes a frequency component (fb / 2 frequency component) related to the transmission clock of the modulated signal, the phase comparison unit 28 uses the frequency component of fb / 2 and the frequency fb /. The error signal is generated based on a phase error with respect to the divided clock of 2.

  The error signal is smoothed through the LPF 34 and supplied to the VCO 36 as a DC control voltage. As described above, the VCO 36 outputs a reproduction carrier having substantially the same frequency as the carrier of the modulation signal corresponding to the control voltage to the level conversion unit 38.

  Therefore, the Costas circuit 13 includes multipliers 14 and 18, LPFs 16 and 20, multiplier 26, phase comparison unit 28, LPF 34, VCO 36, level conversion unit 38, and 90 ° phase shift unit 22. A PLL circuit for phase-synchronizing the regenerative carrier with the carrier of the modulation signal, and supplying the error signal (the control voltage) to the VCO 36, thereby making the regenerative carrier a carrier of the modulation signal. In phase synchronization, the modulation signal is frequency-drawn within the frequency range of the reproduction carrier.

  The data reproducing unit 24 performs multi-level identification determination processing based on the reproduction clock input from the clock reproducing unit 32, reproduces digital data (reproduced data) from the I signal and the Q signal, and outputs the data to the outside. .

  Next, problems of the digital demodulator 10 will be described.

  The phase comparison unit 28 includes a multiplication type comparison circuit, and calculates a phase error between the IQ product signal and the divided clock included in a signal obtained by multiplying the IQ product signal and the divided clock. A signal corresponding to this phase error is output as an error signal (control voltage). Therefore, the phase comparison unit 28 calculates the frequency error between the IQ product signal and the divided clock, in other words, the frequency component related to the transmission clock of the modulation signal included in the IQ product signal and the divided clock. It is not a circuit that detects a frequency error and outputs a signal corresponding to the frequency error.

  For this reason, the oscillation frequency of the VCO 36 (reproduced carrier frequency) changes due to the temperature change of the circuit constant of the VCO 36, the aging of the VCO 36, etc., and the frequency error between the modulated signal carrier and the regenerated carrier increases, When the frequency of the reproduced carrier is out of synchronization with the frequency of the carrier of the modulated signal, the above-described Costas circuit 13 (PLL circuit) cannot be frequency-synchronized with the carrier of the modulated signal and the reproduced carrier. Note that the case where the frequency synchronization is not achieved means that the modulation signal is the Costas circuit 13 when the power of the digital demodulation device 10 is turned on or the reception of the modulation signal at the receiver on which the digital demodulation device 10 is mounted. As a result, the IQ product signal is composed only of noise components.

  This problem will be described in detail with reference to FIG. 2. The frequency of the carrier of the modulated signal (center frequency f1 in FIG. 2) is known, and a predetermined frequency range (frequency deviation) centered on the center frequency f1. ) (Range of frequencies f4 to f5 shown in FIG. 2).

  On the other hand, the Costas circuit 13 considers the above-described frequency deviation of the carrier of the modulation signal, and the frequency pull-in range of the modulation signal is a range of frequencies f2 to f3 centered on the center frequency f1 {frequency pull-in range (1)}. The frequency pull-in is surely performed on the modulation signal having the frequency deviation. Note that the frequency pull-in range (1) (frequency f2 to f3) is wider than the frequency deviation (frequency f4 to f5) of the carrier of the modulation signal.

  However, when the oscillation frequency of the VCO 36 (reproduced carrier frequency) changes from the center frequency f1 to the center frequency f6 due to the temperature change of the circuit constants of the VCO 36 constituting the Costas circuit 13, the aging of the VCO 36, or the like, The frequency pull-in range in the Costas circuit 13 also changes from the range (1) (frequency f2-f3 range) to the frequency f7-f8 range {frequency pull-in range (2)}. As a result, among the carrier of the modulation signal, the frequency range of f8 to f5 deviates from the frequency pull-in range (2), and the modulation signal of this frequency range f8 to f5 is input to the digital demodulator 10. In this case, there is a problem that the frequency synchronization of the carrier of the modulation signal and the reproduction carrier cannot be achieved, and the frequency of the modulation signal cannot be drawn. Therefore, when the carrier of the modulation signal is in such a frequency range (frequency f8 to f5), digital data cannot be reliably demodulated (reproduced) from the modulation signal.

  The above is the problem of the digital demodulator 10 which is the premise of the present embodiment.

  Next, the digital demodulator 48 according to the present embodiment will be described with reference to FIG.

  When the digital demodulator 48 is described, the same components as those of the digital demodulator 10 (see FIG. 1) are denoted by the same reference numerals, and detailed description of the operation is omitted.

  As shown in FIG. 3, the digital demodulator 48 includes a frequency correction circuit 50 and an adder 54, a crystal oscillator 30 is arranged in the frequency correction circuit 50, and a clock recovery unit 51 is an edge. It differs from the digital demodulator 10 (see FIG. 1), which is a premise of the present embodiment, in that it has a detection unit 52.

  As shown in FIGS. 3 and 4, the edge detection unit 52 includes a rising / falling detection unit 80, a flip-flop 82, a mask signal generation unit 86, and a one-shot pulse generation unit 84. As shown in the figure, basically, when an IQ product signal is input, the rising and falling detection unit 80 detects the rising and falling of the IQ product signal, and uses the detection result as an edge pulse to make a one-shot pulse. The signal is output from the generator 84 to the frequency correction circuit 50. Each arrow in the IQ product signal in FIG. 5 indicates that the rise / fall detection unit 80 detects the rise and fall of the IQ product signal at the time indicated by each arrow.

  The edge detection unit 52 will be described in more detail. As shown in FIGS. 3 to 6, the rising / falling detection unit 80 detects the rising and falling of the IQ product signal at the time indicated by each arrow in FIG. The detection result is output to the set terminal S of the flip-flop 82. In this case, when the signal indicating the detection result is input from the rise / fall detection unit 80 to the set terminal S, the flip-flop 82 is supplied from the output terminal O to the one-shot pulse generation unit 84 and the mask signal generation unit 86. A level signal is output.

  By the way, if jitter (see FIG. 6) is included in the rise and fall of the IQ product signal, it leads to malfunction of the digital circuit 40 as a whole, and demodulation characteristics (bits related to digital data reproduction in the data reproduction unit 24). (Error rate) may be degraded. In particular, when the level of the modulation signal is relatively low, the deterioration becomes significant.

  Therefore, the edge detection unit 52 (see FIGS. 3 and 4) does not directly output the detection result of the rising / falling detection unit 80 as an edge pulse to the frequency correction circuit 50, but a flip-flop 82, a one-shot pulse generation unit. 84 and the mask signal generation unit 86 are used to output an edge pulse based on the signal subjected to the jitter removal processing in advance to the frequency correction circuit 50.

  That is, the mask signal generation unit 86 generates a mask signal having a cycle of the reciprocal number (1 / fb) of the frequency fb of the recovered clock at the timing when the clock is input from the crystal oscillator 30 and supplies the mask signal to the reset terminal R of the flip-flop 82. Output. In this case, the pulse of the mask signal rises at a time slightly delayed from the rise and fall of the IQ product signal, and the time when ½ fb has elapsed from the rise and fall times of the IQ product signal. (See FIG. 6). Therefore, in the time zone in which the pulse of the mask signal can be output to the reset terminal R, there is no signal output from the output terminal O of the flip-flop 82 (see FIG. 4), and jitter occurs at the rising and falling edges of the IQ product signal. Even if included, such jitter is masked by the mask signal in the flip-flop 82, and as a result, output of the signal component related to the jitter from the flip-flop 82 to the one-shot pulse generator 84 is blocked. The

  The one-shot pulse generator 84 outputs a signal corresponding to the pulse from the output terminal O of the flip-flop 82 to the frequency correction circuit 50 as an edge pulse. In this case, the edge pulse is generated every time the IQ product signal rises and falls, and its pulse width is a time during which the pulse of the mask signal is not generated in the jitter mask width (see FIG. 6). .

  The clock recovery unit 51 has the same configuration and function as the clock recovery unit 32 (see FIG. 1) of the digital demodulator 10 except that the edge detection unit 52 is provided. Based on the clock from 30, a regenerated clock and a divided clock are generated.

  As shown in FIG. 3, the frequency correction circuit 50 includes a crystal oscillator 30, a synchronization state monitoring unit 56, a timer control unit 58, a counter 60, a data conversion unit (ROM) 62, an adder 64, a register 65, and an initial data storage unit. 66, a DA converter 70, and an LPF 72. Among the frequency correction circuit 50, the synchronization state monitoring unit 56, timer control unit 58, counter 60, data conversion unit (ROM) 62, adder 64, register 65, and initial data The storage unit 66 is mounted in the digital circuit 40. The data converter (ROM) 62, the adder 64, the register 65, the initial data storage 66, the DA converter 70, and the LPF 72 constitute a correction voltage generator 73.

  As shown in FIG. 7, the synchronization state monitoring unit 56 includes a timer 90, an OR circuit (reset unit) 92, a frequency counter 94, and a one-shot pulse generation unit 96, and the frequency fe of the edge pulse is a predetermined frequency (for example, When the frequency fb / 2) of the divided clock is exceeded, there is some abnormality in the IQ product signal (I signal and Q signal) corresponding to the edge pulse, specifically, the first signal corresponding to the I signal When the baseband signal is generated by the multiplier 14 (see FIG. 3) and the second baseband signal corresponding to the Q signal is generated by the multiplier 18, the carrier of the modulation signal, the reproduced carrier, It is determined that the first and second baseband signals are generated in a state where the frequency synchronization is not achieved (the first and second baseband signals are within the frequency f8 to f5 range shown in FIG. 2). It determines that the de signal is generated) to the timer control unit 58 as the out-of-sync signal determination result.

  That is, as shown in FIGS. 7 and 8, the timer 90 sends a timer pulse through the OR circuit 92 at a predetermined repetition period (timer period) based on the clock input from the crystal oscillator 30 (see FIG. 3). To the preset terminal of the frequency counter 94.

  The frequency counter 94 receives a pulse (the timer pulse input from the timer 90 or a pulse indicating a flag input from the flag terminal of the frequency counter 94 via the OR circuit 92) from the OR circuit 92 to the preset terminal. From the time when the next pulse is input until the count value in the frequency counter 94 is reset, and when the edge pulse is input from the edge detection unit 52 to the clock enable terminal (CE), Count the number of edge pulses. If the width of the edge pulse is the width of one clock of the clock input from the crystal oscillator 30 to the clock terminal (CLK), the edge pulse is input to the clock terminal.

  In this case, the frequency counter 94 in the synchronization state monitoring unit 56, for example, when the count value of the number of edge pulses becomes the count value N corresponding to fb / 2, in other words, within the time of the timer cycle. When the edge pulse frequency fe is equal to or higher than fb / 2, a pulse indicating a flag is output from the flag terminal to the one-shot pulse generator 96 and the OR circuit 92. The one-shot pulse generator 96 outputs a pulse synchronized with the clock and having a predetermined pulse width to the timer controller 58 (see FIG. 3) as an out-of-synchronization signal with a pulse from the flag terminal as a trigger. On the other hand, when the flag pulse is input to the preset terminal via the OR circuit 92, the count value of the frequency counter 94 is reset to zero.

  Accordingly, when the synchronization state monitoring unit 56 determines that the Costas circuit 13 is out of synchronization with the frequency of the carrier of the modulated signal, the synchronization signal Is output to the timer control unit 58.

  As shown in FIG. 3, when the out-of-synchronization signal is input, the timer control unit 58 counters a pulse (gate pulse) that is synchronized with the clock input from the crystal oscillator 30 and has a predetermined pulse width. It outputs to 60 clock enable terminals (CE). The timer control unit 58 outputs a reset pulse for resetting the count value in the counter 60 to the reset terminal of the counter 60 after a predetermined time has elapsed since the gate pulse was output. Further, the timer control unit 58 also outputs an initialization signal for initializing the register 65 to the register 65.

  As shown in FIGS. 3 and 9, the counter 60 is connected to the clock terminal (CLK) from the VCO 36 via the level converter 38 within the time when the gate pulse is input to the clock enable terminal (CE) of the counter 60. ) Is counted up, and the integrated count value n at the time when the pulse input to the clock enable terminal CE is stopped is output to the data converter 62 of the correction voltage generator 73. The counter 60 resets the count value n to 0 when a reset pulse is input to the reset terminal.

  The data conversion unit 62 associates the count value n with data indicating a voltage value (correction voltage) corresponding to the frequency deviation (frequency deviation from the center frequency f1) of the reproduction carrier corresponding to the count value n. When the count value n is input from the counter 60, the data corresponding to the count value n is retrieved and this data is output to the adder 64.

  The initial data storage unit 66 is a memory that stores, as initial data, data corresponding to a voltage value (correction voltage) corresponding to the center frequency f1 (see FIGS. 2 and 10) or f11 (see FIG. 10) of the reproduction carrier. . As described above, the center frequency f1 is the center frequency of the original frequency pull-in range (1) with respect to the carrier of the modulation signal, and the center frequency f11 is equal to the frequency of the carrier of the modulation signal. When the frequency is out of synchronization, for example, when the frequency pulling range (1) is changed to the frequency pulling range (2), the frequency pulling range (2) is changed to the frequency pulling range (3) (of the frequencies f9 to f10). This is the center frequency when correcting to (range).

  The register 65 reads out and registers the initial data stored in the initial data storage unit 66 or registers the data input from the data conversion unit 62 via the adder 64 and registers the registered data. Is output to the adder 64 and the DA converter 70. When an initialization signal is input from the timer control unit 58, the register 65 is initialized, and the initial data stored in the initial data storage unit 66 is read and registered. When there is no data input from the adder 64, the initial data registered in the register 65 or the currently registered data is output to the adder 64 or the DA converter 70.

  The adder 64 adds the data output from the register 65 and the data output from the data conversion unit 62 and outputs the result to the register 65.

  The DA converter 70 converts the data output from the register 65 into an analog signal. The LPF 72 smoothes the analog signal from the DA converter 70 and outputs it to the adder 54 as a DC voltage (correction voltage).

  The adder 54 superimposes the correction voltage from the LPF 72 on the control voltage from the LPF 34 and outputs it to the VCO 36. In this case, the correction voltage is a DC voltage corresponding to the frequency error between the center frequency f1 and the center frequency f6 or a DC voltage corresponding to the frequency error between the center frequency f11 and the center frequency f6. When the frequency synchronization of the modulated signal carrier and the reproduced carrier is not achieved {when the reproduced carrier frequency range is the frequency pull-in range (2) shown in FIG. 2}, the correction voltage is superimposed on the control voltage. When supplied to the VCO 36, the frequency pulling range is corrected from the frequency pulling range (2) (center frequency f6) shown in FIG. 2 to the frequency pulling range (3) (center frequency f11) shown in FIG.

  Next, in the digital demodulator 48 according to the present embodiment, when demodulating digital data from a modulated signal, when the frequency of the reproduction carrier is out of synchronization with the frequency of the carrier of the modulated signal (the carrier of the modulated signal and The operation of correcting the frequency of the reproduction carrier when the frequency synchronization with the reproduction carrier is not achieved will be described with reference to FIGS.

  Here, when the frequency of the reproduction carrier changes from the frequency pulling range (1) of the center frequency f1 to the frequency pulling range (2) of the center frequency f6 (see FIG. 2), the frequency pulling range (2) is changed to the center frequency f1. A case (see FIG. 10) of correcting to a frequency pull-in range (3) of the nearby center frequency f11 (range of frequencies f9 to f10) will be described.

  Since the operation of the digital demodulator 48 when the frequency of the modulated signal carrier and the reproduced carrier is synchronized is substantially the same as that of the digital demodulator 10 (see FIG. 1), the description thereof is omitted. To do.

  The rise / fall detection unit 80 of the edge detection unit 52 detects the rise and fall of the IQ product signal, and outputs the detection result to the set terminal S of the flip-flop 82. The mask signal generator 86 outputs a mask signal to the reset terminal R of the flip-flop 82 based on the clock from the crystal oscillator 30. The flip-flop 82 outputs a pulse of a signal at a time when the mask signal is not input to the reset terminal R among the signals indicating the detection result input to the set terminal S from the output terminal O to the one-shot pulse generator 84. Output. The one-shot pulse generator 84 outputs a signal corresponding to the pulse from the output terminal O of the flip-flop 82 to the frequency correction circuit 50 as an edge pulse.

  In the synchronization state monitoring unit 56 in the frequency correction circuit 50, the timer 90 outputs a timer pulse to the preset terminal of the frequency counter 94 via the OR circuit 92 for each timer period based on the clock from the crystal oscillator 30. The frequency counter 94 is the time when the edge pulse is input from the edge detection unit 52 to the clock enable terminal (CE), and after one pulse is input from the OR circuit 92 to the preset terminal, the next pulse is The number of the edge pulses is counted within the time until it is input again to the preset terminal.

  The frequency counter 94 indicates a flag from the flag terminal when the count value reaches a predetermined number N during the timer period, in other words, when the frequency fe of the edge pulse exceeds, for example, fb / 2. The pulse is output to the one-shot pulse generator 96 and the OR circuit 92. Thus, when the flag pulse is input to the preset terminal via the OR circuit 92, the count value of the frequency counter 94 is reset to 0, while the one-shot pulse generator 96 triggers the pulse. As a result, a pulse synchronized with the clock and having a predetermined pulse width is output to the timer controller 58 as an out-of-synchronization signal.

  When the out-of-synchronization signal is input, the timer control unit 58 outputs an initialization signal to the register 65 so that the initial data stored in the initial data storage unit 66 (at the reproduction carrier center frequency f1 or f11). Data) is registered in the register 65, and a gate pulse having a predetermined pulse width is output to the clock enable terminal (CE) of the counter 60 in synchronization with the clock from the crystal oscillator 30. .

  The counter 60 counts the number of regenerative carrier pulses input from the VCO 36 to the clock terminal (CLK) via the level converter 38 within the time when the gate pulse is input to the clock enable terminal (CE). The count value n at the time when the pulse input to the clock enable terminal (CE) is stopped is output to the data converter 62 of the correction voltage generator 73.

  The data conversion unit 62 searches the look-up table for data indicating a correction voltage corresponding to the frequency deviation of the reproduced carrier corresponding to the input count value n, and outputs the searched data to the adder 64.

  In this case, since the initial data corresponding to the correction voltage at the center frequency f1 (or f11) is stored in the register 65, the adder 64 performs a data conversion unit on the initial data output from the register 65. The data from 62 is added, and the addition result is output to the register 65. The register 65 registers the addition result as new data instead of the initial data, and outputs the registered new data to the DA converter 70 and the adder 64. As a result, the new data registered in the register 65 has a deviation between the center frequency f1 or f11 and the center frequency f6 when out of synchronization, in other words, from the center frequency f6 to the center frequency f1 or f11. The data corresponds to the correction voltage necessary for correction.

  The DA converter 70 converts the data output from the register 65 into an analog signal, and the LPF 72 smoothes the analog signal from the DA converter 70 and outputs it to the adder 54 as a DC correction voltage. That is, the correction voltage is a DC voltage corresponding to the frequency deviation between the center frequency f1 or f11 and the center frequency f6.

  The adder 54 superimposes the correction voltage from the LPF 72 on the control voltage from the LPF 34 and outputs it to the VCO 36.

  As a result, the VCO 36 outputs a reproduction carrier having a frequency f11 corresponding to the control voltage and the correction voltage. As a result, the frequency pull-in range of the modulation signal in the Costas circuit 13 is the frequency pull-in range (2 ) To the frequency pull-in range (3) shown in FIG.

  The synchronization state monitoring unit 56, the timer control unit 58, and the correction voltage generation unit 73 can reliably correct the above-described frequency pull-in range by repeatedly performing the correction voltage generation operation described above.

  As described above, according to the present embodiment, the frequency correction circuit 50 directly monitors the frequency of the reproduction carrier. Therefore, when it is determined that the reproduction carrier is not frequency-synchronized with the carrier of the modulation signal. Can immediately supply a correction voltage to the VCO 36 to correct the frequency of the reproduction carrier.

  As a result, the present embodiment is more effective when the frequency error between the carrier of the modulation signal and the reproduction carrier becomes larger than in the prior art in which frequency synchronization is determined based on monitoring of demodulated digital data. By uniquely detecting the correction voltage corresponding to the error, the reproduction carrier can be frequency-synchronized with the carrier of the modulation signal more reliably and in a short time.

  Therefore, according to the present embodiment, it is possible to realize the digital demodulator 48 of the synchronous detection system that is hardly affected by the temperature change of the circuit constant of the VCO 36 or the secular change of the VCO 36.

  In the frequency correction circuit 50, the counter 60 counts the number of reproduction carrier pulses sequentially input from the VCO 36 within a predetermined time set by the timer control unit 58, and the correction voltage generation unit 73 determines the counter 60. Since the correction voltage is generated according to the difference between the frequency according to the count value of the pulse and the carrier frequency of the modulation signal, the frequency of the reproduction carrier can be reliably monitored and the modulation signal can be monitored. The correction voltage can be reliably supplied when the frequency synchronization between the carrier and the reproduction carrier is not synchronized.

  Further, in the frequency correction circuit 50, the crystal oscillator 30 outputs a clock having a predetermined frequency, and the timer control unit generates a gate pulse having the predetermined time as a pulse width based on the clock and outputs the gate pulse to the counter 60. . In this case, the crystal oscillator 30 can generate the clock with a frequency accuracy higher than that of the VCO 36, while the counter 60 is capable of generating the reproduction carrier within the predetermined time when the gate pulse is input. Since the number of pulses can be counted, the frequency correction circuit 50 can generate the correction voltage with high accuracy.

  Further, when the frequency component of the IQ product signal exceeds a predetermined frequency (for example, fb / 2), the synchronization state monitoring unit 56 outputs an out-of-synchronization signal indicating that the frequency synchronization is not established to the timer control unit 58. Is arranged in the frequency correction circuit 50, and when the out-of-synchronization signal is input, the timer control unit 58 generates the gate pulse based on the clock and outputs it to the counter 60. At 50, the correction voltage can be generated by reliably monitoring whether the frequency synchronization is achieved by the Costas circuit 13 or not. That is, since the frequency correction circuit 50 generates the correction voltage only when it is determined that the frequency synchronization is not achieved, the modulation signal and the reproduction are not disturbed by preventing the PLL operation of the Costas circuit 13. It becomes possible to perform frequency synchronization with the carrier, and as a result, it is possible to improve the reliability of receiving and demodulating the modulated signal in the receiver on which the digital demodulator 48 is mounted.

  Further, an edge detection unit that removes jitter at the rise and fall of the IQ product signal, detects the rise and fall at the clock timing, and outputs the detection result to the synchronization state monitoring unit 56 as an edge pulse 52 is provided in the clock recovery unit 51, the synchronization state monitoring unit 56 includes a timer 90 that generates a timer pulse having a predetermined period based on the clock, and the number of edge pulses that are sequentially input within the period of the timer pulse. A frequency counter 94 that sets a flag when the count value exceeds a count value corresponding to a predetermined frequency (for example, fb / 2), and generates the out-of-synchronization signal based on the flag to generate a timer control unit 58. The one-shot pulse generator 96 for outputting to the frequency counter and the flag or the timer pulse to the frequency counter 94, the edge detection unit 52 generates an edge pulse based on the IQ product signal and outputs it to the synchronization state monitoring unit 56. The frequency correction circuit 50 can generate the correction voltage with higher accuracy.

  Note that the case where the frequency synchronization is not achieved means that, as described above, for example, when the power of the digital demodulator 48 is turned on or the reception of the modulation signal at the receiver equipped with the digital demodulator 48 is interrupted. The signal is not input to the Costas circuit 13, and as a result, the IQ product signal is composed only of noise components. By operating the frequency correction circuit 50 in such a time zone, the frequency of the reproduced carrier Can be efficiently performed.

  The digital demodulator according to the present invention is not limited to the above-described embodiment, and can of course adopt various configurations without departing from the gist of the present invention.

It is a block diagram of a digital demodulator as a premise of the present embodiment. It is explanatory drawing which shows the frequency drawing range in the digital demodulator of FIG. It is a block diagram of a digital demodulator according to the present embodiment. It is a block diagram of the edge detection part of FIG. It is a time chart which shows operation | movement of the edge detection part of FIG. It is a time chart which shows operation | movement of the edge detection part of FIG. FIG. 4 is a block diagram of a synchronization state monitoring unit in FIG. 3. It is a time chart which shows operation | movement of the synchronous state monitoring part of FIG. It is a time chart which shows the operation | movement of the counter of FIG. It is explanatory drawing which shows the frequency drawing range in the digital demodulator of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 48 ... Digital demodulator 13 ... Costas circuit 14, 18, 26 ... Multiplier 22 ... 90 degree phase shift part 24 ... Data reproduction part 28 ... Phase comparison part 30 ... Crystal oscillator 32, 51 ... Clock reproduction part 36 ... VCO DESCRIPTION OF SYMBOLS 50 ... Frequency correction circuit 52 ... Edge detection part 54 ... Addition part 56 ... Synchronization state monitoring part 58 ... Timer control part 60 ... Counter 62 ... Data conversion part 64 ... Adder 65 ... Register 66 ... Initial data storage part 73 ... Correction voltage Generation unit 80 ... rising / falling detection unit 82 ... flip-flop 86 ... mask signal generation unit 84, 96 ... one-shot pulse generation unit 90 ... timer 92 ... OR circuit 94 ... frequency counter

Claims (1)

A VCO that outputs a reproduction carrier having substantially the same frequency as the modulation signal in response to the supply of the control voltage, and when the modulation signal is input from the outside, the modulation carrier is multiplied by the reproduction carrier to perform synchronous detection. Based on the first baseband signal obtained by the above and the second baseband signal obtained by multiplying the modulation signal by the signal obtained by shifting the phase of the reproduction carrier by 90 ° and performing synchronous detection. A voltage corresponding to a phase error between a transmission clock and a divided clock obtained by dividing a reproduction clock necessary for reproducing digital data from the first and second baseband signals is supplied to the VCO as the control voltage. Thus, in a digital demodulator comprising a Costas circuit that achieves phase synchronization between the carrier of the modulated signal and the reproduced carrier,
A detection unit that detects a product signal obtained by multiplying signals based on the first and second baseband signals , and a jitter removal unit that removes jitter included in the product signal detected by the detection unit; An edge pulse generator that generates an edge pulse according to the period of the product signal from which jitter has been removed ;
Based on the frequency of the edge pulse input from the edge pulse generator, it is monitored whether the frequency of the reproduced carrier is shifted from the frequency of the carrier of the modulated signal, and the frequency of the carrier of the modulated signal and the reproduced carrier When synchronization is not achieved, the pulses of the reproduction carrier for a predetermined period are counted, data based on the count value is processed to generate a voltage, and a frequency error between the carrier of the modulation signal and the reproduction carrier is determined . digital demodulation apparatus characterized by having a frequency correcting circuit for supplying to said VCO as compensation voltage.

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