JP4859191B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to an improvement in a read operation of a semiconductor memory device, particularly a read only memory.

FIG. 2 is a configuration diagram of a conventional semiconductor memory device.
This semiconductor memory device is a nonvolatile read-only memory, and includes a plurality of memory cell arrays 10 ₀ to 10 _n , a column switch 20, a reference potential generation circuit 30, a drain voltage generation circuit 40, a charging circuit 50, and the like.

Each of the memory cell arrays 10 ₀ to 10 _n has the same configuration and uses a MOS transistor having a floating gate as the memory cell MC. The memory cell arrays 10 ₀ to 10 _n intersect with a plurality of word lines WL _{0 to} WL _m arranged in parallel. Have a plurality of drain lines DL1, DL2,... And source lines SL1, SL2,. The drain lines DL1, DL2,... And the source lines SL1, SL2,... Are alternately arranged in parallel, and the drain lines DL1, DL2, ..., the source lines SL1, SL2, ..., and the word lines WL _{0 to} WL. Memory cells MC are arranged so as to be connected to corresponding ones of _m . The control gate of the memory cell MC is connected to the corresponding word line WL, the drain is connected to the corresponding drain line DL, and the source is connected to the corresponding source line SL.

Further, the drain lines DL1, DL2,... Are switch transistors 11 ₁ , 11 that are on / off controlled by cell drain selection signals DSEi, DSOi for selecting each memory cell array 10 _i (where i = 0 to n). ₂ are connected to the drain power supply line 12. On the other hand, the source lines SL1, SL2,... Are connected to the bit lines BL1, BL2 via switching transistors 13 ₁ , 13 ₂ ,... That are on / off controlled by a cell source selection signal SSi that selects each memory cell array 10 _i . Connected to BL2,.

The column switch 20, the memory cell array 10 is read out from the _i the bit lines BL1, BL2 selected from among the output data in parallel to ..., select a pair of data in accordance with a column selection signal Y0~Yk The data is output to the data lines DT1 and DT2.

  The reference potential generating circuit 30 generates the reference potential REF when the enable signal / CE becomes level “L” (for example, the level of the ground potential GND) during data reading. During standby, the enable signal / CE is at level “H” (for example, the level of the power supply potential VCC), the reference potential generation circuit 30 is also in a standby state, and generation of the reference potential REF is stopped.

The drain voltage generation circuit 40 generates a drain voltage MCD (about 0.9 V) to be applied to the memory cell MC based on the reference potential REF supplied from the reference potential generation circuit 30. The drain voltage generation circuit 40 includes, for example, an N-channel MOS transistor (hereinafter referred to as “NMOS”) 41 whose gate is supplied with a reference potential REF. The source of the NMOS 41 is connected to the ground potential GND, and the drain is connected to the drain and gate of a P-channel MOS transistor (hereinafter referred to as “PMOS”) 42 and the gate of the PMOS 43. The sources of the PMOSs 42 and 43 are connected to a power supply potential VCC (for example, 3V), and the drain of the PMOS 43 is connected to the ground potential GND via the NMOS 44. The gate of the NMOS 44 is connected to the node N40, and the node N40 is connected to the power supply potential VCC via the NMOS 45 and the PMOS 46 connected in series. The gate of the NMOS 45 is connected to the drain of the NMOS 44, and the gate of the PMOS 46 is connected to the ground potential GND. Then, the drain voltage MCD is outputted from the node N40, is adapted to be applied to the drain power supply line 12 of each memory cell array 10 _i.

The charging circuit 50 is for rapidly charging the drain power supply line 12 of each memory cell array 10 _i to the drain voltage MCD when the standby state is released. The charging circuit 50 has, for example, a PMOS 51 whose gate is supplied with an enable signal / CE. The source of the PMOS 51 is connected to the power supply potential VCC, and the drain is connected to the node N 40 via the NMOS 52.

Further, the charging circuit 50 has a PMOS 54 which is supplied to the gate after the enable signal / CE is inverted by the inverter 53. The source of the PMOS 54 is connected to the power supply potential VCC, and the drain is connected to the node N50. Node N50 is connected to ground potential GND via NMOS 55, and signal S50 of node N50 is applied to the gate of NMOS 52. On the other hand, the potential of the drain power supply line 12 of the memory cell array 10 _i is supplied to the gate of the NMOS 55 as the drain voltage detection signal MCDS via the resistor 61.

  FIG. 3 is a signal waveform diagram showing the operation of FIG. The operation of FIG. 2 will be described below with reference to FIG.

  In the standby state, the enable signal / CE is “H”. As a result, the operation of the reference potential generation circuit 30 is stopped, the reference potential REF is 0V, and the drain voltage MCD output from the drain voltage generation circuit 40 is also 0V. On the other hand, in the charging circuit 50, the PMOS 51 is turned off and the PMOS 54 is turned on. Further, since the drain voltage detection signal MCDS given to the NMOS 55 is 0V, the NMOS 55 is off. Therefore, the signal S50 at the node N50 is “H”. Further, the word line WL, the drain line DL, and the source line SL become “L”, and the non-selected bit lines BL are in a floating state.

  The standby state is released by setting the enable signal / CE to “L”, thereby starting the charging operation.

  When the enable signal / CE becomes “L”, the reference potential REF output from the reference potential generation circuit 30 rises slowly, and the drain voltage MCD of the drain voltage generation circuit 40 also rises accordingly. On the other hand, in the charging circuit 50, the PMOS 51 is turned on and the PMOS 54 is turned off. Immediately after the release of the standby state, the drain voltage detection signal MCDS is “L”, so that the NMOS 55 remains off and the signal S50 is held at “H” for a while. As a result, the drain voltage MCD rises rapidly through the PMOS 51 and NMOS 52 of the charging circuit 50. When the drain voltage MCD rises and the potentials of the word line WL, the drain line DL, and the source line SL rise and exceed the threshold value of the memory cell, the potential of the bit line BL also starts to rise. Further, when the drain voltage detection signal MCDS rises due to a sudden rise in the drain voltage MCD, the NMOS 55 of the charging circuit 50 is turned on, the signal S50 becomes “L”, and the NMOS 52 is turned off. Thereby, charging circuit 50 is disconnected from node N40 of drain voltage generation circuit 40, and drain voltage MCD of node N40 is supplied by this drain voltage generation circuit 40 until reference potential REF settles to a predetermined potential.

  Then, when a predetermined time has elapsed and the reference potential REF has settled, a data read operation is started.

JP 2004-247026 A JP-A-2005-190626

However, the semiconductor memory device has the following problems.
The normal standby state is released in a relatively short time, and the data read operation is repeated again. For this reason, charges remain in the bit line BL that is in a floating state in the standby state, and does not drop to the complete ground potential GND. In this case, the rise of the reference potential REF when the standby state is released is slow, but the drain voltage MCD is rapidly charged to the vicinity of the predetermined voltage by the charging circuit 50. As a result, the read operation can be performed when the reference potential REF has settled to a predetermined voltage.

  However, if the standby period becomes longer, the charge on the bit line BL does not leak, and the potential of the bit line BL decreases to the ground potential GND as shown by the broken line in FIG. For this reason, when the standby state is released after a long period of time, the drain voltage MCD is rapidly charged to a vicinity of a predetermined voltage during the rapid charging by the charging circuit 50, but the drain voltage detection signal MCDS rises. When the charging circuit 50 is disconnected, the drain voltage MCD is connected to the bit line BL through the selected memory cell immediately thereafter, and the drain voltage MCD is greatly reduced. When the read operation is performed at this timing, there is a problem that an error occurs in the read data.

  In addition, in order to detect a reading failure after a long standby period in the product test process, it is necessary to perform a test after leaving it in a standby state for a long period of time. Further, since the charge leakage time varies, it is not clear how much time it should actually be left in the standby state, and it is difficult to detect a reading failure.

  An object of the present invention is to provide a semiconductor memory device that can perform a normal read operation even after a long standby period.

The present invention includes a plurality of word lines arranged in parallel, a plurality of drain lines and source lines arranged crossing the word lines, memory cells connected to these word lines, drain lines and source lines, and A memory cell array having a drain power supply line for supplying a drain voltage to the drain line, and a plurality of bits provided corresponding to the plurality of source lines of the memory cell array and connected to the source line via a switching transistor A column switch that selects a signal of the bit line in accordance with a column selection signal and outputs the selected signal to the data line, and generates a drain voltage when a read operation is specified by an enable signal to generate a drain power source of the memory cell array When a read operation is designated by the drain voltage generation circuit applied to the line and the enable signal, In the semiconductor memory device, the drain voltage generation circuit including a charging circuit that is turned on and charges the drain power supply line of the memory cell array from the power supply potential until the drain voltage is monitored and rises to a predetermined potential of the output side, as well as connected through a resistor to the drain power supply line of said memory cell array, the potential of the drain power supply line through the resistor, and characterized by being configured to provide a monitoring voltage of the charging circuit .

  In the present invention, a drain voltage is applied by connecting the output side of the drain voltage generation circuit to a drain power supply line via a resistor, and the potential of the drain power supply line via this resistor is monitored by a charging circuit. As a result, the rise in the potential of the drain power supply line is delayed and the time for supplying the drain voltage from the charging circuit is lengthened, so that the memory cell array can be reliably charged to the drain voltage.

  The resistance value of the resistor connecting the output side of the drain voltage generation circuit and the drain power supply line is the time constant of the integrating circuit composed of this resistor and the stray capacitance connected to the drain power supply line of the memory cell array. The value is set to a range of 40 to 60% of the access standard value.

  FIG. 1 is a configuration diagram of a semiconductor memory device showing Embodiment 1 of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

The semiconductor memory device is a nonvolatile read-only memory, and includes a plurality of memory cell arrays 10 _i (where i = 0 to n), a column switch 20, a reference potential generation circuit 30, a drain voltage generation circuit 40, a charging circuit 50, and the like. have.

Each memory cell array 10 _i uses a MOS transistor having a floating gate as a memory cell MC. A plurality of word lines WL _{0 to} WL _m arranged in parallel and a plurality of drain lines DL 1 arranged intersecting with the word lines WL _{0 to} WL _m are used. , DL2,... And source lines SL1, SL2,. The drain lines DL1, DL2,... And the source lines SL1, SL2,... Are alternately arranged in parallel, and the drain lines DL1, DL2, ..., the source lines SL1, SL2, ..., and the word lines WL _{0 to} WL. Memory cells MC are arranged so as to be connected to the corresponding ones of _m . The control gate of the memory cell MC is connected to the corresponding word line WL, the drain is connected to the corresponding drain line DL, and the source is connected to the corresponding source line SL.

Further, the drain lines DL1, DL2,... Are connected to drain power supplies via switching transistors 11 ₁ , 11 ₂ ,... That are on / off controlled by cell drain selection signals DSEi, DSOi for selecting each memory cell array 10 _i. Connected to line 12. On the other hand, the source lines SL1, SL2,... Are connected to the bit lines BL1, BL2 via switching transistors 13 ₁ , 13 ₂ ,... That are on / off controlled by a cell source selection signal SSi that selects each memory cell array 10 _i . Connected to BL2,.

Column switch 20, the memory cell array 10 is read out from the _i the bit lines BL1, BL2 selected from among the output data in parallel to ..., select a pair of data in accordance with a column selection signal Y0~Yk The data is output to the data lines DT1 and DT2.

  The reference potential generation circuit 30 generates the reference potential REF when the enable signal / CE becomes level “L” during data reading. During standby, the enable signal / CE is at level “H”, the reference potential generation circuit 30 is also in a standby state, and generation of the reference potential REF is stopped.

The drain voltage generation circuit 40 generates a drain voltage MCD (approximately 0.9 V) to be applied to the memory cell based on the reference potential REF supplied from the reference potential generation circuit 30. The drain voltage generation circuit 40 includes, for example, an NMOS 41 whose gate is supplied with a reference potential REF. The source of the NMOS 41 is connected to the ground potential GND, and the drain is connected to the drain and gate of the PMOS 42 and the gate of the PMOS 43. The sources of the PMOSs 42 and 43 are connected to a power supply potential VCC (for example, 3V), and the drain of the PMOS 43 is connected to the ground potential GND via the NMOS 44. The gate of the NMOS 44 is connected to the node N40, and the node N40 is connected to the power supply potential VCC via the NMOS 45 and the PMOS 46 connected in series. The gate of the NMOS 45 is connected to the drain of the NMOS 44, and the gate of the PMOS 46 is connected to the ground potential GND. Then, the output is the drain voltage MCD from node N40, the drain voltage MCD is, through the resistor 62 is adapted to be applied to one end of the drain power supply line 12 of each memory cell array 10 _i.

Note that the resistance value of the resistor 62 is the access standard value of the enable signal / CE (for example, 100 ns) based on the time constant of the integrating circuit formed by the stray capacitance connected to the drain power supply line 12 of each memory cell array 10 _i. ) Of about 50 ns (that is, about 50 ns).

The charging circuit 50 is for rapidly charging the drain power supply line 12 of each memory cell array 10 _i to the drain voltage MCD when the standby state is released. The charging circuit 50 has, for example, a PMOS 51 whose gate is supplied with an enable signal / CE. The source of the PMOS 51 is connected to the power supply potential VCC, and the drain is connected to the node N 40 via the NMOS 52. The charging circuit 50 further includes a PMOS 54 that is inverted by an inverter 53 and applied to the gate of the enable signal / CE. The source of the PMOS 54 is connected to the power supply potential VCC, and the drain is connected to the node N50. Node N50 is connected to ground potential GND via NMOS 55, and signal S50 of node N50 is applied to the gate of NMOS 52. On the other hand, the gate of the NMOS 55 is connected via a resistor 61 to the other end of the drain power supply line 12 of each memory cell array 10 _i (that is, opposite to one end to which the drain voltage MCD is applied). As a result, the potential of the drain power supply line 12 is supplied as the drain voltage detection signal MCDS via the resistor 61.

  FIG. 4 is a signal waveform diagram showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG. In FIG. 4, the conventional signal waveform of FIG. 3 is indicated by a broken line for comparison.

  In the standby state, the enable signal / CE is “H”. As a result, the operation of the reference potential generation circuit 30 is stopped, the reference potential REF is 0V, and the drain voltage MCD output from the drain voltage generation circuit 40 is also 0V. On the other hand, in the charging circuit 50, the PMOS 51 is turned off and the PMOS 54 is turned on. Further, since the drain voltage detection signal MCDS given to the NMOS 55 is 0V, the NMOS 55 is off. Therefore, the signal S50 at the node N50 is “H”. Further, the word line WL, the drain line DL, and the source line SL become “L”, and the non-selected bit lines BL are in a floating state.

  The standby state is released by setting the enable signal / CE to “L”, thereby starting the charging operation.

  When the enable signal / CE becomes “L”, the reference potential REF output from the reference potential generation circuit 30 rises slowly, and the drain voltage MCD of the drain voltage generation circuit 40 also rises accordingly. On the other hand, in the charging circuit 50, the PMOS 51 is turned on and the PMOS 54 is turned off. Immediately after the release of the standby state, the drain voltage detection signal MCDS is “L”, so that the NMOS 55 remains off and the signal S50 is held at “H” for a while. As a result, the drain voltage MCD rises rapidly through the PMOS 51 and NMOS 52 of the charging circuit 50.

Drain voltage MCD Since applied via resistor 62 to the memory cell array 10 _i, a voltage actually applied to the drain power supply line 12 of each memory cell array 10 _i, the drain of the resistor 62 and each of the memory cell array 10 _i It rises according to the time constant of the integration circuit due to the stray capacitance of the power line 12 and the like. Therefore, the rise of the drain voltage detection signal MCDS is slower than the rise of the drain voltage MCD. For this reason, the timing when the signal S50 of the charging circuit 50 becomes “L” is also delayed compared to the conventional timing.

  On the other hand, when the potential of the word line WL, the drain line DL, and the source line SL rises due to the rise of the drain voltage MCD and exceeds the threshold value of the memory cell, the potential of the bit line BL also starts to rise. At this time, since the signal S50 is still “H”, the drain voltage MCD is supplied from the charging circuit 50.

  Here, if the charge remains on the bit line BL, the drain voltage detection signal MCDS rises quickly, and if no charge remains, the drain voltage detection signal MCDS rises slowly. Further, when the drain voltage detection signal MCDS rises due to the rise of the drain voltage MCD, the NMOS 55 of the charging circuit 50 is turned on, the signal S50 becomes “L”, and the NMOS 52 is turned off. Thereby, charging circuit 50 is disconnected from node N40 of drain voltage generation circuit 40, and drain voltage MCD of node N40 is supplied by this drain voltage generation circuit 40 until reference potential REF settles to a predetermined potential.

  Then, when a predetermined time has elapsed and the reference potential REF has settled, the selection of the memory cell MC and the data read operation from the selected memory cell MC are started.

As described above, in the semiconductor memory device according to the first embodiment, the drain voltage MCD generated by the drain voltage generation circuit 40 and the charging circuit 50 is applied to one end of the drain power supply line 12 of each memory cell array 10 _i via the resistor 62. together they give, and the potential of the other end of the drain power supply line 12 for each of these memory cell array 10 _i, so as to feedback to the charging circuit 50 as the drain voltage detection signal MCDS. Thus, the drain voltage MCD can be supplied from the charging circuit 50 to each memory cell array 10 _i until the potential of the drain power supply line 12 rises to a predetermined potential. be charge-discharge, it is possible to provide the proper drain voltage MCD to each memory cell array 10 _i, there is an advantage that it is possible to prevent a data read error immediately after the standby state is released.

If the resistance value of the resistor 62 is small, the time for supplying the drain voltage MCD from the charging circuit 50 to each memory cell array 10 _i is shortened, and the same problem as in the conventional case occurs. On the other hand, if it is too large, the rise of the drain voltage MCD applied to each memory cell array 10 _i is delayed and the read operation cannot be started at a predetermined time. Therefore, the resistance value of the resistor 62 is equal to the access standard value of the enable signal / CE (for example, 100 ns), which is the time constant of the integrating circuit composed of the stray capacitance connected to the drain power supply line 12 of each memory cell array 10 _i. A value in the range of 40 to 60% is optimal.

  FIG. 5 is a configuration diagram of a semiconductor memory device showing Embodiment 2 of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  In this semiconductor memory device, a charging circuit 50A having a slightly different configuration is provided in place of the charging circuit 50 in the semiconductor memory device of FIG.

  The charging circuit 50A has a PMOS 51 whose gate is supplied with an enable signal / CE. The source of the PMOS 51 is connected to the power supply potential VCC, and the drain is connected to the node N 40 via the NMOS 52. The charging circuit 50 further includes a delay element (DLY) 56 that delays the enable signal / CE by a predetermined time and applies the delayed signal to the inverter 53. For example, the delay element can be realized by cascading a plurality of inverters. The delay time by the delay element 56 is set to a time corresponding to the strobe for standby state release access.

The output side of the inverter 53 is connected to the gate of the PMOS 54. The drain of the PMOS 54 is connected to the node N 50, and this node N 50 is connected to the ground potential GND through the NMOS 55 and is connected to the gate of the NMOS 52. The gate of the NMOS 55 is supplied with the potential of the drain power supply line 12 of the memory cell array 10 _i as the drain voltage detection signal MCDS via the resistor 61.

  On the other hand, the source of the PMOS 54 is connected to the power supply potential VCC through a plurality of PMOSs 57a to 57c connected in series. The gates of the PMOSs 57a to 57c are connected to the ground potential GND, and these PMOSs 57a to 57c are set to an on state. Further, the connection points of the PMOSs 57a to 57c are connected to the power supply potential VCC via the fuses 58a and 58b. Other configurations are the same as those in FIG.

  FIG. 6 is a signal waveform diagram showing the operation of FIG. Hereinafter, the operation of FIG. 5 will be described with reference to FIG. In FIG. 6, the conventional signal waveform of FIG. 3 is indicated by a broken line for comparison.

  The standby state is released by setting the enable signal / CE to “L”, whereby the NMOS 51 of the charging circuit 50A is turned on and the charging operation is started. On the other hand, since the enable signal / CE is supplied to the gate of the NMOS 54 via the delay element 53 and the inverter 53, the NMOS 54 is turned off after the delay time by the delay element 53 has elapsed.

  When the drain voltage MCD rises due to the charging operation, and the drain voltage detection signal MCDS rises accordingly, the PMOSs 57a to 57c set to the on state from the power supply potential VCC and the NMOS 55 via the PMOS 54 still in the on state. Current begins to flow. Thus, the charging operation is continued while the signal S50 of the node N50 is gradually lowered. Then, after the delay time by the delay element 53 elapses, the PMOS 54 is turned off and the charging operation is stopped, and the through current flowing through the PMOSs 57a to 57c and 54 and the NMOS 55 is stopped.

As described above, the semiconductor memory device according to the second embodiment includes the charging circuit 50A having the delay element 56 that delays the charge stop timing. Since this makes it possible to supply the drain voltage MCD from the charging circuit 50A to each of the memory cell array 10 _i, the same merits as in Example 1. Further, the charging circuit 50A includes PMOSs 57a to 57c as resistance elements for gently changing the signal S50 of the node N50, so that a rapid change in the drain voltage MCD is suppressed and the reading operation is stabilized. There is an advantage that you can. Furthermore, since the resistance values of the PMOSs 57a to 57c can be changed depending on whether or not the fuses 58a and 58b are cut, variation can be individually adjusted.

  If the delay element 56 is also configured to be trimmed by cutting a fuse or the like, an optimum delay time can be set individually after the wafer process is completed. It goes without saying that resistors and other resistance elements can be used in place of the PMOSs 57a to 57c. Further, it goes without saying that the transistors constituting the charging circuit may be other conductivity type transistors as long as the above operation can be realized.

  FIG. 7 is a configuration diagram of a semiconductor memory device showing Embodiment 3 of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  This semiconductor memory device is obtained by adding a test circuit 70 to the semiconductor memory device of FIG. The test circuit 70 has a terminal 71 to which a test signal TST for designating a test mode is applied, and a resistor 72 that pulls down the terminal 71.

The test circuit 70 has OR gates 73 _{0 to} 73 _k for controlling column selection signals Y _{0 to} Yk supplied to the column switch 20. Column selection signals Y0 to Yk are supplied to the first input sides of the OR gates 73 _{0 to} 73 _k , respectively, and a test signal TST is supplied to the second input side. The output sides of the OR gates 73 _{0 to} 73 _k are connected to the column switch 20.

Further, the test circuit 70 includes NMOSs 74 ₁ and 74 ₂ for connecting the data lines DL1 and DL2 to the ground potential GND in the test mode. That is, the drains of the NMOSs 74 ₁ and 74 ₂ are connected to the data lines DL1 and DL2, respectively, and the sources are connected to the ground potential GND. The gates of the NMOSs 74 ₁ and 74 ₂ are connected to the terminal 71 so that a test signal TST is given.

In this semiconductor memory device, when the terminal 71 is not connected or is “L”, the OR gates 73 _{0 to} 73 _k are merely buffers, and the NMOSs 74 ₁ and 74 ₂ are in an off state, so that a normal operation is performed.

On the other hand, when the test signal TST of “H” is applied to the terminal 71, all the column selection signals Y0 to Yk applied to the column switch 20 become “H”, and all the bit lines BL1, BL2,. Connected to DL2. Further, the data lines DL1 and DL2 are connected to the ground potential GND through the NMOSs 74 ₁ and 74 ₂ in the on state. As a result, all bit lines BL1, BL2,... Are connected to the ground potential GND.

  As described above, in the semiconductor memory device according to the third embodiment, all the bit lines BL1, BL2,... Are forcibly connected to the ground potential GND by the test signal TST, and these bit lines BL1, BL2,. A test circuit 70 for completely discharging is provided. Thereby, since the same conditions as the long standby state can be formed in a short time, there is an advantage that the test time for testing the read failure after the long standby time can be shortened.

  Note that the configuration of the test circuit 70 is not limited to the configuration of the third embodiment, and any configuration that can forcibly discharge the charges of all the bit lines BL1, BL2,. Further, a logic circuit that does not provide the terminal 71 and outputs the test signal TST by a combination of specific input signals that cannot be performed in the normal operation may be used.

  In the first to third embodiments, the semiconductor memory device using the MOS transistor having the floating gate as the memory cell MC has been described. However, the present invention is applicable to all semiconductor memory devices including the drain voltage generating circuit and the charging circuit. Can do. The number of the memory cell arrays 10 may be singular or plural.

1 is a configuration diagram of a semiconductor memory device showing Embodiment 1 of the present invention. It is a block diagram of the conventional semiconductor memory device. FIG. 3 is a signal waveform diagram illustrating the operation of FIG. 2. It is a signal waveform diagram which shows the operation | movement of FIG. It is a block diagram of the semiconductor memory device which shows Example 2 of this invention. FIG. 6 is a signal waveform diagram illustrating the operation of FIG. 5. It is a block diagram of the semiconductor memory device which shows Example 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory cell array 12 Drain power supply line 20 Column switch 40 Drain voltage generation circuit 50 Charging circuit 62 Resistance 70 Test circuit BL Bit line DL Drain line DT Data line MC Memory cell SL Source line WL Word line

Claims (4)

A plurality of word lines arranged in parallel, a plurality of drain lines and source lines arranged crossing the word lines, memory cells connected to these word lines, drain lines and source lines, and the drain lines A memory cell array having a drain power supply line for supplying a drain voltage;
A plurality of bit lines provided corresponding to a plurality of source lines of the memory cell array and connected to the source lines via switching transistors;
A column switch that selects the signal of the bit line according to a column selection signal and outputs the selected signal to the data line;
A drain voltage generating circuit that generates the drain voltage and applies it to the drain power supply line of the memory cell array when a read operation is designated by an enable signal;
When a read operation is specified by the enable signal, a charging circuit that is in an on state and charges the drain power supply line of the memory cell array from the power supply potential until the drain voltage is monitored and rises to a predetermined potential In a semiconductor memory device comprising:
The output side of the drain voltage generation circuit is connected to the drain power supply line of the memory cell array through a resistor, and the potential of the drain power supply line through the resistor is provided as a monitoring voltage of the charging circuit. A semiconductor memory device.   The resistance value of the resistor is such that the time constant of the integrating circuit composed of the stray capacitance connected to the drain power supply line of the memory cell array is in the range of 40 to 60% of the access standard value of the enable signal. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is set. A plurality of word lines arranged in parallel, a plurality of drain lines and source lines arranged crossing the word lines, memory cells connected to these word lines, drain lines and source lines, and the drain lines A memory cell array having a drain power supply line for supplying a drain voltage;
A plurality of bit lines provided corresponding to a plurality of source lines of the memory cell array and connected to the source lines via switching transistors;
A column switch that selects the signal of the bit line according to a column selection signal and outputs the selected signal to the data line;
A drain voltage generating circuit that generates the drain voltage and applies it to the drain power supply line of the memory cell array when a read operation is designated by an enable signal;
When a read operation is specified by the enable signal, a charging circuit that is in an on state and charges the drain power supply line of the memory cell array from the power supply potential until the drain voltage is monitored and rises to a predetermined potential In a semiconductor memory device comprising:
The charging circuit is
A first first conductivity type MOS transistor connected between a power supply potential and a first node and turned on by the enable signal;
A first second conductivity type MOS transistor connected between the first node and the drain power supply line, the conduction state of which is controlled by the potential of the second node;
A delay element for delaying and inverting the enable signal;
A second first-conductivity-type MOS transistor connected between the second node and a third node connected to a power supply potential via a resistance means, and turned off by the delayed and inverted enable signal;
A second second-conductivity-type MOS transistor connected between the second node and a ground potential, the conduction state of which is controlled by the drain voltage;
A semiconductor memory device comprising:   4. The semiconductor memory device according to claim 3, wherein the resistance means is configured such that a resistance value can be adjusted by cutting a fuse.

Images