JP4859503B2 - Video circuit - Google Patents

Description

  The present invention relates to a video circuit including a video processing circuit and a charge pump circuit, and in particular, when a negative voltage is generated by a charge pump circuit and the negative voltage is used as a negative power supply voltage of the video processing circuit, the negative voltage is provided. The present invention relates to a video circuit in which no noise is included in the video signal quality so that the video signal quality is not deteriorated.

  FIG. 9 shows a configuration of a video circuit configured to supply a negative voltage generated by the charge pump circuit to the video processing circuit as a negative power supply voltage. The video processing circuit 10 performs various image processing (hue adjustment, contrast adjustment) on the video signal output from the clamp circuit 11 for clamping the sync chip and the pedestal level of the input video signal S51 including the synchronization signal. , Enlargement, reduction, edge enhancement, and other processing), and an output drive circuit 13 that amplifies the output signal of the video signal processing circuit 12 to a video drive signal and supplies it to a load of 75Ω, for example. . The output drive circuit 13 is supplied with a positive power supply voltage + V and a negative power supply voltage −V as power supplies in order to expand the dynamic range. C1 is a DC cut capacitor. The positive power supply voltage + V and the ground voltage GND are applied to the clamp circuit 11 and the video signal processing circuit 12.

  Reference numeral 60 denotes a free-run oscillator that generates pulses having a frequency of around 100 KHz. A charge pump circuit 20 receives a free run signal S52 output from the free run oscillator 60 and generates a drive control signal S53, and an output circuit 22 that is driven and controlled by the drive control signal S53. Thus, the negative voltage −V output from the output circuit 22 is supplied as a negative power supply voltage to the output drive circuit 13 of the video processing circuit 10.

  As shown in FIG. 11, the output circuit 22 includes a charging capacitor C2, an output capacitor C3, and switches SW1 to SW4. When the signal S53 is H level, the switches SW1 and SW2 are turned on by the drive control signal S53. The switches SW3 and SW4 are turned off, and when they are at the L level, the switches SW1 and SW2 are turned off, and the switches SW3 and SW4 are turned on. V is generated.

  On the other hand, using the free-run oscillator 60, a synchronization signal is extracted from the input video signal, a continuous pulse is generated based on the synchronization signal, and this continuous pulse is input to the charge pump circuit to generate a negative voltage. There is an amplifier described in Patent Document 1 in which this negative voltage is supplied to a main amplifier (corresponding to the output drive circuit 13 in FIG. 9).

According to the video circuit shown in FIG. 9 and the amplifier shown in Patent Document 1, since the positive power supply voltage + V and the negative power supply voltage −V are applied to the output drive circuit 13, the dynamic range can be expanded. Can do.
JP 2005-151468 A

  However, in the video circuit of FIG. 9, the drive control signal S53 is generated based on the free run signal S52 generated by the free run oscillator 60, and the switches SW1 to SW4 of the output circuit 22 are continuously turned on / off by this drive control signal S53. Therefore, noise and ripple are superimposed on the generated negative voltage −V even in the video period of the input video signal S51, and the influence appears in the output video signal S54 (see FIG. 10). The beat noise etc. are generated above.

  Also, in the amplifier of Patent Document 1, since the charge pump circuit is driven by continuous pulses, the noise and ripple are superimposed on the output video signal and beat noise is generated on the screen as in the video circuit of FIG. Etc. will be generated.

  An object of the present invention is to provide a video circuit in which the quality of an output video signal is improved by preventing noise and ripple from being superimposed on the supplied negative voltage during the video period.

In order to achieve the above object, the invention according to claim 1 is a video processing circuit that clamps a sync chip or pedestal of an input video signal including a synchronization signal by a clamp circuit, performs video processing, and outputs it as a video drive signal; And a charge pump circuit that generates a negative voltage for a negative voltage power source required for the video processing circuit, comprising: a synchronization signal detecting means for detecting a synchronization signal from an output signal of the clamp circuit; The pump circuit inputs the synchronization signal and charges the charging capacitor only during the pulse period of the synchronization signal, and discharges the charge capacitor to the output capacitor during a period other than the pulse period of the synchronization signal. It was made to do.
The invention according to claim 2 is required for a video processing circuit that clamps a sync chip or a pedestal of an input video signal including a synchronization signal by a clamp circuit, performs video processing, and outputs it as a video drive signal, and the video processing circuit In a video circuit having a charge pump circuit for generating a negative voltage for a negative voltage power supply, a synchronizing signal detecting means for detecting a synchronizing signal from an output signal of the clamp circuit, and a synchronizing signal detected by the synchronizing signal detecting means with a pulse width extension means for decompressing so that there is no the video period signal period of said charge pump circuit, only stretched pulse duration to be output from the pulse width expanding unit executes charging of the Chi Yaji capacitor, said extension this period other than the pulse duration which is adapted to discharge the output capacitor charge of the charging capacitor The features.
According to a third aspect of the present invention, there is provided a video processing circuit that clamps a pedestal of an input video signal not including a synchronization signal by a clamp circuit, performs video processing, and outputs the video driving signal, and a negative voltage required for the video processing circuit A video circuit having a charge pump circuit for generating a negative voltage for power supply, comprising clamp pulse input means for inputting a clamp pulse to the clamp circuit, wherein the charge pump circuit receives the clamp pulse and inputs the clamp The charging capacitor is charged only during the pulse period of the pulse, and the charge of the charging capacitor is discharged to the output capacitor during a period other than the pulse period of the clamp pulse .
According to a fourth aspect of the present invention, there is provided a video processing circuit that clamps a pedestal of an input video signal not including a synchronization signal by a clamp circuit, performs video processing, and outputs the video driving signal, and a negative voltage required for the video processing circuit In a video circuit having a charge pump circuit for generating a negative voltage for power supply, a clamp pulse input means for inputting a clamp pulse to the clamp circuit, and a pulse width for extending the signal period of the clamp pulse so as not to be in the video period comprising a stretching means, the charge pump circuit is only stretched pulse duration to be output from the pulse width expanding unit executes charging of the Chi Yaji capacitor, a period other than the stretched pulse duration charge of the charging capacitor It is characterized by discharging to the output capacitor .

  According to the present invention, since the charge pump circuit is not driven within the video period of the input video signal, noise and ripple are not superimposed on the negative voltage generated in the charge pump circuit. Even if it is supplied to the processing circuit, the quality of the video signal output from the video processing circuit does not deteriorate due to the negative voltage.

[First embodiment]
FIG. 1 is a block diagram showing the configuration of a video circuit according to the first embodiment of the present invention, and FIG. 2 is an operation waveform diagram thereof. Similarly to the configuration of FIG. 9, the video processing circuit 10 performs various operations on the clamp circuit 11 that clamps the sync chip and pedestal level of the input video signal S <b> 11 including the synchronization signal, and various video signals output from the clamp circuit 11. A video signal processing circuit 12 to which image processing (hue adjustment, contrast adjustment, enlargement, reduction, edge enhancement, other processing) is applied, and an output signal of the video signal processing circuit 12 is amplified to a video drive signal, for example, to a load of 75Ω An output drive circuit 13 is provided. The output drive circuit 13 is supplied with a positive power supply voltage + V and a negative power supply voltage −V as power supplies in order to expand the dynamic range. C1 is a DC cut capacitor. The positive power supply voltage + V and the ground voltage GND are applied to the clamp circuit 11 and the video signal processing circuit 12.

  Reference numeral 30 denotes a synchronization signal detection circuit as synchronization signal detection means, which detects the synchronization signal S12 based on the leading edge and the trailing edge of the sync tip portion clamped by the clamp circuit 11. A charge pump circuit 20 includes a drive control circuit 21 that receives the synchronization signal S12 and generates the drive control signal S13, and an output circuit 22 that is controlled by the drive control signal S13. The voltage −V is supplied to the output drive circuit 13 of the video processing circuit 10 as a negative power supply voltage.

  As shown in FIG. 11, the output circuit 22 includes a charging capacitor C2, an output capacitor C3, and switches SW1 to SW4. When the signal S13 is at H level, the switches SW1 and SW2 are turned on by the drive control signal S13. The switches SW3 and SW4 are turned off, and when they are at the L level, the switches SW1 and SW2 are turned off and the switches SW3 and SW4 are turned on. As a result, the capacitors C2 and C3 are charged with the charges of the polarity shown in FIG. V is generated.

  As described above, in this embodiment, since the charging capacitor C2 of the output circuit 22 of the charge pump circuit 20 is charged only during the synchronization signal period, the negative voltage −V accumulated in the output capacitor C3 is equal to (d ). That is, the negative voltage −V does not pulsate during the video period of the input video signal S11, and noise and ripple are not superimposed on the output video signal and beat noise or the like is not generated on the screen.

[Second embodiment]
FIG. 3 is a block diagram showing the configuration of a video circuit according to the second embodiment of the present invention, and FIG. 4 is an operation waveform diagram thereof. Here, in the video circuit described with reference to FIG. 1, a detection time constant circuit 40 and a comparison circuit 50 as pulse width expansion means are inserted between the synchronization signal detection circuit 30 and the charge pump circuit 20. The detection time constant circuit 40 receives the synchronization signal S22 detected by the synchronization signal detection circuit 30, and generates a detection time constant signal S23 whose delay is delayed. When the threshold Vth is set and the falling edge of the detection time constant signal S23 falls below the threshold Vth, the comparison circuit 50 extends the pulse width of the detection synchronization signal S22 by reducing the output level. However, the extension time is a time that does not take the video period of the input video signal S21. For this reason, the pulse width of the drive control signal S25 is expanded.

  Therefore, in the video circuit of the second embodiment, not only can the negative voltage −V be prevented from pulsating during the video period of the input video signal S21, but also the time during which the switches SW1 and SW2 of the output circuit 22 are on. Is longer than in the case of the video circuit of the first embodiment (FIGS. 1 and 2), the amount of charge charged in the capacitor C2 increases accordingly, and the replenishment amount for the consumed charge can be increased. And drive capability can be increased. In addition, since the amount of charge stored in the capacitor C2 can be increased in this way, the amount of charge to be replenished when it is consumed can be reduced, and the size when the switches SW1 and SW2 are formed of transistors can be reduced. And the IC area can be reduced.

[Third embodiment]
FIG. 5 is a block diagram showing a configuration of a video circuit according to the third embodiment of the present invention, and FIG. 6 is an operation waveform diagram thereof. Here, a video signal (one of RGB signals) S31 not including a synchronization signal is input to the clamp circuit 11A, and a clamp pulse S32 for the video signal is input from an input terminal 111 as a clamp pulse input means. The pedestal clamp operation is performed in the clamp circuit 11A. In this case, in place of the synchronization signal S12 described in the first embodiment (FIGS. 1 and 2), the clamp pulse S32 is input to the charge pump circuit 20, so that the input is similar to the first embodiment. A negative voltage −V that does not pulsate during the video period of the video signal S31 can be generated.

[Fourth embodiment]
FIG. 7 is a block diagram showing a configuration of a video circuit according to the fourth embodiment of the present invention, and FIG. 8 is an operation waveform diagram thereof. Also here, a video signal (one of RGB signals) S41 not including a synchronization signal is input to the clamp circuit 11A, and a clamp pulse S42 for the video signal is input from an input terminal 111 as a clamp pulse input means. The pedestal clamp operation in the clamp circuit 11 is performed. In this case, in place of the synchronization signal S22 described in the second embodiment (FIGS. 3 and 4), the clamp pulse S42 is input to the detection time constant circuit 40, and as in the second embodiment, A negative voltage −V that does not pulsate during the video period of the input video signal S41 can be generated, and the drive capability of the charge pump circuit 20 can be increased and the area can be reduced.

[Other examples]
In each of the above embodiments, the negative voltage generated in the charge pump circuit 20 is supplied only to the output drive circuit 13 of the video processing circuit 10, but when the video signal processing circuit 12 is a positive and negative power source system, Supply it there. Further, the output capacitor C3 of the charge pump circuit 20 may be externally attached to the video processing circuit 10 side. Furthermore, an n-channel video processing circuit may be provided, and 1 to n output circuits may be provided as a charge pump circuit that supplies a negative voltage to the output drive circuit.

It is a block diagram which shows the structure of the video circuit of a 1st Example. FIG. 2 is an operation waveform diagram of the video circuit in FIG. 1. It is a block diagram which shows the structure of the video circuit of a 2nd Example. FIG. 4 is an operation waveform diagram of the video circuit of FIG. 3. It is a block diagram which shows the structure of the video circuit of a 3rd Example. FIG. 6 is an operation waveform diagram of the video circuit in FIG. 5. It is a block diagram which shows the structure of the video circuit of a 4th Example. FIG. 8 is an operation waveform diagram of the video circuit in FIG. 7. It is a block diagram which shows the structure of the conventional video circuit. FIG. 10 is an operation waveform diagram of the video circuit of FIG. 9. It is a circuit diagram of the output circuit of a charge pump circuit.

Explanation of symbols

10: Video processing circuit, 11, 11A: Clamp circuit, 111: Clamp pulse input terminal, 12: Video signal processing circuit, 13: Output drive circuit, 20: Charge pump circuit, 21: Drive control circuit, 22: Output circuit 30 : Sync signal detection circuit 40: Detection time constant circuit 50: Comparison circuit 60: Free-run oscillator

Claims (4)

A video processing circuit that clamps a sync chip or pedestal of an input video signal including a synchronization signal by a clamp circuit, processes the video, and outputs it as a video drive signal, and a negative voltage for a negative voltage power source required for the video processing circuit In a video circuit having a charge pump circuit for generating
Synchronizing signal detecting means for detecting a synchronizing signal from the output signal of the clamp circuit, the charge pump circuit inputs the synchronizing signal and charges the charging capacitor only during a pulse period of the synchronizing signal , A video circuit characterized in that the charge capacitor is discharged to an output capacitor during a period other than the pulse period of the synchronizing signal . A video processing circuit that clamps a sync chip or pedestal of an input video signal including a synchronization signal by a clamp circuit, processes the video, and outputs it as a video drive signal, and a negative voltage for a negative voltage power source required for the video processing circuit In a video circuit having a charge pump circuit for generating
The charge pump comprising: synchronization signal detection means for detecting a synchronization signal from the output signal of the clamp circuit; and pulse width extension means for extending the signal period of the synchronization signal detected by the synchronization signal detection means so as not to reach the video period. circuit, only the stretched pulse duration to be output from the pulse width expanding unit executes charging of the Chi Yaji capacitor, a period other than the stretched pulse duration to discharge the output capacitor charge of the charging capacitor A video circuit characterized by that. Clamps the pedestal of the input video signal that does not include the sync signal by the clamp circuit, processes the video, and outputs it as a video drive signal, and generates a negative voltage for the negative voltage power source required for the video processing circuit In a video circuit having a charge pump circuit
Clamp pulse input means for inputting a clamp pulse to the clamp circuit, wherein the charge pump circuit inputs the clamp pulse and charges the capacitor for charging only during the pulse period of the clamp pulse. An image circuit characterized in that the charge capacitor is discharged to an output capacitor during a period other than a pulse period . Clamps the pedestal of the input video signal that does not include the sync signal by the clamp circuit, processes the video, and outputs it as a video drive signal, and generates a negative voltage for the negative voltage power source required for the video processing circuit In a video circuit having a charge pump circuit
Clamp pulse input means for inputting a clamp pulse to the clamp circuit, and pulse width expansion means for extending the signal period of the clamp pulse so as not to reach the video period, and the charge pump circuit outputs from the pulse width expansion means only stretched pulse duration, perform the charging of the Chi Yaji capacitor, a period other than the stretched pulse duration video circuit, characterized in that so as to discharge the output capacitor charge of the charging capacitor.

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