JP4861216B2 - Drive power circuit - Google Patents

Description

  The present invention relates to a drive power supply circuit for a device that can be regarded as a capacitive load.

As this type of capacitive load, for example, there is a MEMS (MicroElectro Mechanical System). As a drive power supply circuit for driving the MEMS, a charge pump type voltage converter is known (see, for example, Patent Document 1).
Japanese Patent No. 3558976

  By the way, a drive device that drives a capacitive load such as MEMS with a voltage requires a high-power drive power supply circuit with high drive capability for high-voltage drive at a high frequency and response improvement.

  However, since the charge pump type voltage converter used in the conventional high voltage circuit is connected in the order of coils, switches, diodes, and capacitors, it can be controlled from a low voltage to a high voltage, but from a high voltage to a low voltage. In order to lower the voltage, it is necessary to wait for the discharge, and thus there is a problem that high-speed control cannot be supported.

  Accordingly, an object of the present invention is to provide a drive power supply circuit capable of realizing a drive power supply circuit capable of obtaining a high voltage at a high speed with small energy.

  In order to solve the above-described problem, the present invention provides a drive power supply circuit that drives a device with the voltage by applying a voltage from a power supply circuit to a device that can be regarded as a capacitive load. Is provided so that it can be applied to the device via a coil and a diode, and the diode and the device are grounded via a single switching element, and a control means for controlling ON / OFF of the switching element is provided. A power supply circuit is provided.

  According to the configuration of the present invention, it is possible to realize a drive power supply circuit capable of obtaining a high voltage at a high speed with small energy.

A device drive voltage control circuit that can be regarded as a capacitive load according to an embodiment of the present invention will be described below with reference to the drawings.
[Constitution]
FIG. 1 schematically shows a parallel plane type electrostatic actuator 1 which is a MEMS as an example of a capacitive load. The electrostatic actuator 1 includes conductive fixing portions 2 and 2 provided at intervals, a square and conductive flat mirror (mirror) 3 disposed between the fixing portions 2 and 2, and It has shaft-like and conductive torsion springs 4 and 4 for attaching the plane mirror 3 to the fixing portions 2 and 2. At least one of the fixing portions 2 and 2 is grounded. In addition, planar lower electrodes 5 and 6 are disposed below the plane mirror 3.

  Here, as shown in FIG. 2, when no torque acts on the torsion springs 4 and 4, the plane mirror 3 is in a state indicated by a broken line. Assuming a virtual plane 7 that passes through the center line (axis) O of the torsion springs 4 and 4 in this state and is perpendicular to the plane mirror 3 indicated by the broken line, the lower electrodes 5 and 6 are positioned on the left and right sides of the virtual plane 7. ing. That is, the lower electrodes 5, 6 are arranged below the plane mirror 3 by dividing the lower electrodes 5, 6 into the left and right with the portion below the center line of the torsion springs 4, 4 as the center.

  In this initial state (VR = VL), the plane mirror 3 and the lower electrodes 5 and 6 are parallel, and the plane mirror 3 is inclined in the direction of A1 when VR <VL, and conversely when VR> VL. become.

  Since the lower electrodes 5 and 6 and the plane mirror 3 can be regarded as capacitive loads as shown in FIG. 3, capacitors CL and CR are formed, and the capacitors CL and CR have the driving shown in FIG. A drive voltage from the power supply circuits 8 and 8 'is applied.

  The drive power supply circuit 8 includes an amplifier 9 for amplifying a voltage, a coil 10 having one end connected to the output side of the amplifier 9, a diode 11 having an anode connected to the other end of the coil 10, and a cathode of the diode 11. One FET (switching element) 12 having a drain connected to the side is provided. The cathode side of the diode 11 is connected to the lower electrode 5 constituting the capacitor CL, and the source of one FET 12 is grounded (grounded).

  Further, the drive power supply circuit 8 ′ has a diode 11 ′ similar to the diode 11 of the drive power supply circuit 8. The cathode side of the diode 11 'is connected to the lower electrode 6 constituting the capacitor CR. Since the drive power supply circuit 8 ′ is configured in the same manner as the drive power supply circuit 8, the reference numerals assigned to the drive power supply circuit 8 are denoted by “′” and description thereof is omitted.

  The drive power supply circuits 8 and 8 'are controlled in operation by a control circuit (control means) 13.

  The control circuit 13 includes a personal computer 14 in which a load control program is installed, an FPGA (Field Programmable Gate Array) 15 in which control content is written by the control program of the personal computer 14, and a gate driver whose operation is controlled by the control content from the FPGA 15. 16 The gate driver 16 applies a control voltage (control signal) to the gates of the FETs 12 and 12 ′ of the drive power supply circuits 8 and 8 ′ based on the control contents from the FPGA 15.

The control circuit 13 also converts a digital control content from the FPGA 15 into an analog signal, and a level conversion circuit 18 that outputs a control voltage based on the control content from the digital / analog conversion circuit 17. Have The level conversion circuit 18 inputs a control voltage to the amplifiers 9 and 9 'of the drive power supply circuits 8 and 8'.
[Action]
Next, the operation of the drive voltage control circuit having such a configuration will be described.

  From the personal computer 14, voltage data corresponding to an angle at which the plane mirror 3 is desired to be controlled is input to the FPGA 15. This data may be transmitted to the D / A 17 as it is, or may be converted into a form according to a certain rule and transmitted to the D / A 17.

  After receiving the data from the personal computer 14 or receiving the conversion start command, the FPGA 15 updates the data of the D / A 17 to the data CD1 at the timing t1 in FIG. 4, and at the timing t2 to t3. Output a write command.

  The level conversion circuit 18 generates signals V1 and V2 that are symmetric with respect to a certain bias level according to the output of the D / A 17.

  The FPGA 15 outputs a t4-t6 switch timing signal to the gate driver 16 in consideration of the conversion time of the level conversion circuit 18.

  This is because the stability of the voltage value created by the charge-up can be increased by setting the state of t5 to be in the first half between t4 and t6.

  During the period from t4 to t6, the capacitors CL and CR as loads are cleared and the coils 10 and 10 'are charged with energy.

  The experimental machine requires a time of about 350 nsec, but varies depending on the capacity of the coil and capacitor.

  From t6 to t7 when switching ends, the energy charged in the coil moves to the capacitors CL and CR, and output voltages VL and VR are generated.

  Furthermore, since the waveform of FIG. 4 shows a case where the plane mirror 3 is set in a parallel state after t8 as CD2, V1 and V2 are both Bias Level, and the output voltages VL and VR are also Bias Level.

In this CD2, VR = VL, so that the plane mirror 3 returns to the position of the broken line and is in a parallel state.
(Modification)
Further, as shown in FIG. 5, a buffer circuit 20 is interposed between the drain of the FET 12 of the drive power supply circuit 8 and the lower electrode 5 of the capacitor CL, and the drain of the FET 12 'of the drive power supply circuit 8' and the capacitor CR. A buffer circuit 20 ′ may be interposed between the lower electrode 6 and the lower electrode 6.

  The buffer circuits 20 and 20 ′ can be regarded as push-pull amplifiers that output the voltages input to the capacitors C1 and C1 ′ as they are. For this reason, the same effect as the structure of FIG. 3 can be acquired by regarding capacitor | condenser C1, C1 'as a load.

  As described above, the drive power supply circuit (8, 8 ') according to the embodiment of the present invention applies the voltage from the power supply circuit to the devices (capacitors CL, CR) that can be regarded as capacitive loads, The device (capacitors CL and CR) is driven by the voltage. In addition, the voltage from the power supply circuit can be applied to the devices (capacitors CL, CR) via the coils (10, 10 ') and diodes (11, 11'), and the diodes (11, 11 ') The device (capacitors CL, CR) is grounded via one switching element (FET12, 12 '), and control means (control circuit 13) controls the switching element (FET12, 12') ON / OFF. ).

  According to this configuration, a high voltage can be obtained at high speed with small energy.

  The electrostatic actuator 1 that is a MEMS has been described as an example of the capacitive load. However, the capacitive load controlled by the drive power supply circuit described above is not limited to this. For example, the drive power supply circuit described above can be applied to other drive devices that drive capacitive loads such as piezoelectric drive devices and electro-optic modulators with voltage.

It is a schematic perspective view which shows an example of the capacitive load driven with the drive power supply circuit which concerns on this invention. It is sectional drawing which follows the B1-B1 line | wire of FIG. FIG. 3 is a circuit diagram illustrating an example of a drive voltage control circuit for the capacitive load of FIGS. 1 and 2. It is a time chart of operation | movement description by the drive voltage control circuit of FIG. FIG. 3 is a circuit diagram showing another example of a drive voltage control circuit diagram of the capacitive load of FIGS. 1 and 2.

Explanation of symbols

8, 8 '... drive power supply circuit VL, VR ... capacitor (capacitive load, device)
10, 10 '... coil 11, 11' ... diode 12, 12 '... FET (switching element)
13 ... Control circuit (control means)

Claims (1)

In a drive power supply circuit that applies a voltage from a power supply circuit to a device that can be regarded as a capacitive load, and drives the device with the voltage,
A voltage from the power supply circuit is provided to be able to be applied to the device via a coil and a diode, and the diode and the device are grounded via a single switching element, and the switching element is ON / OFF controlled. A drive power supply circuit comprising a control means.

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