JP4863306B2 - Vector image drawing apparatus, vector image drawing method and program - Google Patents

Description

  The present invention relates to a vector image drawing apparatus, a vector image drawing method, and a program for displaying a vector image.

The image is displayed on the display by performing processing such as vector scan (processing that draws a figure on the screen with a laser) or raster scan (processing that draws pixels sequentially with scanning lines) on the data image. As a technique for drawing the data image, there is vector graphics. According to the vector graphics, vector images such as straight lines, Bezier curves, elliptical arcs are converted into data, and a vector image is drawn.
As an apparatus for drawing a vector image, there is a drawing apparatus including a pipe in which a plurality of stages perform a series of processes in response to a received drawing command. A pipe having a stage for performing processing such as vector graphic enlargement / reduction processing and vector graphic rotation is disclosed.

  Further, there are the following techniques for improving the drawing speed of vector images.

  For example, Patent Document 4 discloses an image processing apparatus that includes a plurality of rasterizers that can perform parallel processing on each other to render drawing data into bitmap data, and a control device that passes a character drawing command to each rasterizer. In this image processing apparatus, the control device sends a drawing command to the rasterizer for which the character generation processing has been completed, thereby preventing waiting for processing in each rasterizer.

Patent Document 5 discloses an apparatus provided with a plurality of pipes that process different objects and a topology sorter that sorts the order of the stages of each pipe. In this apparatus, the topology sorter reduces the pipe processing time by sorting the order of the stages of each pipe so that the processes are executed at all stages of each pipe.
JP 2006-251311 A JP 2006-338504 A JP 11-339023 A Japanese Patent Laid-Open No. 10-228269 JP 2001-184500 A

  Reference 1 (Open VG Specification Version 1.01 January 26, 2007, pp.4-6) describes an example of a vector image drawing device. The configuration of this drawing device is shown in FIG. To be interpreted. The drawing device 60 shown in FIG. 7 includes a vector graphics application 61, a vector graphics library 62, a driver 63, and a vector graphics accelerator 64. The vector graphics library 62 includes DMA (Direct Memory Access) command generation means 65. In this drawing device 60, the vector graphics application 61 stores information 6 (hereinafter referred to as a path 6), a coordinate transformation matrix 7, and attributes 8 for forming a vector graphic such as a straight line, a Bezier curve, and an elliptical arc in the vector graphics library 62. send.

  The DMA command generation means 65 of the vector graphics library 62 creates a DMA command A that is an instruction-type command to the vector graphics accelerator 64 from the information. Then, the vector graphics library 62 sends a DMA command A to the driver 63. The driver 63 sends the received DMA command A to the vector graphics accelerator 64 sequentially.

  The vector graphics accelerator 64 sequentially processes the received DMA command A, and performs a drawing process of a vector figure for drawing a vector image. The vector graphics accelerator 64 is a pipe having a plurality of stages for performing a series of processing on the DMA command A. In response to the DMA command A moving to a lower stage and the initial stage becoming a standby state, A new DMA command A is input to the initial stage.

  Here, in the pipe for drawing a vector graphic, the time for each stage to process the DMA command is proportional to the size of the vector graphic (hereinafter, the vector graphic to be drawn) drawn by the DMA command processing. For this reason, when DMA commands having greatly different vector graphics sizes to be drawn are continuously input to the pipe, the time required for the upper stage to process the preceding DMA command and the subsequent DMA command. There is a large difference between the time when the lower stage processes the command. As a result, the DMA command is not quickly moved to the lower stage, and the total waiting time of each stage in the pipe is increased. As a result, the problem that the processing time of the whole pipe becomes long arises.

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a vector image drawing apparatus, a vector image drawing method, and a program capable of reducing pipe drawing processing time.

In order to achieve the above object, a vector image drawing apparatus according to the first aspect of the present invention includes:
A region figure generating means for generating a bounding box is a figure that surrounds the base compactors figure for drawing the vector image,
Area calculating means for calculating the area of the bounding box generated by the area graphic generating means;
A command for executing the drawing process of the vector graphic is arranged in a queue, and the difference in the area of the bounding box surrounding the vector graphic to be drawn is set for each of the two adjacent commands in the queue. A driver that changes the order of the commands in the queue so that the sum of the absolute values is minimized.
An accelerator that receives the commands arranged in the queue in order from the top command and performs the drawing process of the vector graphic;
It is characterized by providing.

A vector image drawing method according to a second aspect of the present invention includes:
A drawing method in which a vector image drawing apparatus performs drawing processing of a vector figure in order to draw a vector image,
An area graphic generation means for generating a bounding box that is a graphic surrounding a vector graphic for drawing a vector image ;
An area calculating means for calculating an area of the bounding box generated in the region graphic generating step;
The driver places a command for executing the drawing process of the vector graphic in the queue, and for each of the two adjacent commands in the queue, the driver includes the bounding box surrounding the vector graphic to be drawn. A command placement step of obtaining an absolute value of the difference in area and changing the order of the commands in the queue so that the sum of the absolute values is minimized;
A drawing step in which an accelerator receives the commands arranged in the queue in order from the top command, and performs drawing processing of the vector graphic;
It is characterized by providing.

A program according to a third aspect of the present invention provides a computer,
Area graphic generation means for generating a bounding box that is a graphic surrounding a vector graphic for drawing a vector image ;
Area calculating means for calculating the area of the bounding box generated by the area graphic generating means ;
A command for executing the drawing process of the vector graphic is arranged in a queue, and the difference in the area of the bounding box surrounding the vector graphic to be drawn is set for each of the two adjacent commands in the queue. A driver that changes the order of the commands in the queue so that the sum of the absolute values is minimized.
An accelerator that receives the commands arranged in the queue in order from the top of the commands and performs the drawing process of the vector graphic;
It is made to function as.

  According to the vector image drawing apparatus of the present invention, the order of drawing processes in the queue is set to an order that minimizes the sum of the differences in bounding box areas between adjacent processes. The difference in the size of the vector graphic to be drawn between matching processes is reduced. As a result, the change in the size of the vector figure that the pipe continuously processes can be kept small, so that variations in the processing time at each stage of the pipe can be kept small, and drawing processing from the upper stage to the lower stage can be performed quickly. The total waiting time of each stage in the pipe becomes smaller. As a result, the pipe drawing processing time is shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. Hazuki

  FIG. 1 is a block diagram showing an example of a configuration of a vector image drawing apparatus 1 according to an embodiment of the present invention.

  The vector image drawing apparatus 1 includes a vector graphics (hereinafter referred to as VG) application 2, a VG library 3, a driver 4, and a VG accelerator 5.

  The VG library 3 includes a bounding box calculation unit 31, a coordinate conversion unit 32, and a DMA command generation unit 33. The driver 4 includes a DMA command rearrangement unit 41.

  Next, the operation of the vector image drawing apparatus 1 will be described with reference to FIG.

  The VG application 2 generates a path 6, which is information forming a vector graphic such as a straight line, a Bezier curve, and an elliptical arc, a coordinate transformation matrix 7, and attributes 8 such as colors and line widths, and sends them to the VG library 3.

  When the VG library 3 receives the path 6, the bounding box calculation unit 31 analyzes the path 6 and generates the bounding box 10. FIG. 2 shows an example of the bounding box 10. In FIG. 2, 9 indicates a vector graphic formed by the path 6, and a bounding box 10 is generated so as to surround the vector graphic 9.

  Referring to FIG. 1, the coordinate conversion unit 32 multiplies each of the coordinates of the four corner vertices 10 a (see FIG. 2) of the bounding box 10 generated by the bounding box calculation unit 31 by the coordinate conversion matrix 7. Coordinate conversion of the vertexes 10a at the four corners is performed. By this coordinate conversion, the bounding box 10 is enlarged / reduced / rotated / moved. The coordinate transformation matrix 7 is a combination of a transformation matrix for enlarging and reducing the bounding box 10, a transformation matrix for rotating the bounding box 10, and a transformation matrix for moving the bounding box 10.

  Then, the coordinate conversion unit 32 calculates the area S of the bounding box after the coordinate conversion based on the four corner vertices of the bounding box after the coordinate conversion.

  Further, the DMA command generation unit 33 converts the path 6, the coordinate conversion matrix 7, and the attribute 8 into a DMA command A that is an instruction format command to the VG accelerator 5.

  Then, the VG library 3 passes the bounding box area S coordinate-converted by the coordinate converter 32 and the DMA command A generated by the DMA command generator 33 to the driver 4. At this time, the DMA command A passed from the VG library 3 to the driver 4 is placed in the queue B for setting the processing order of the VG accelerator 5. Hereinafter, for a specific DMA command A, the bounding box area S sent from the VG library 3 to the driver 4 together with the DMA command A will be referred to as the bounding box area S corresponding to the DMA command A as appropriate.

  Then, the VG accelerator 5 receives the DMA command A arranged in the queue B in order from the first DMA command A and performs the drawing process of the vector graphic.

  Here, the VG accelerator 5 is a pipe having a plurality of stages for performing a series of processes for the DMA command A. This pipe includes a stage for performing coordinate conversion processing of a vector graphic to be drawn by the DMA command A. In subsequent stages, processing is executed for the vector graphic for which the coordinate conversion processing has been performed. It has become so.

  The bounding box whose coordinates of the four corners 10a are converted by the coordinate conversion unit 32 surrounds the vector figure subjected to the coordinate conversion process. Based on this, in the present embodiment, the area S of the bounding box subjected to the coordinate conversion is positioned as an index representing the size of the vector graphic subjected to the coordinate conversion process, and the vector graphic processed continuously by the VG accelerator 5 The order of the DMA commands A in the queue B is rearranged according to the area S of the bounding box in order to reduce the change in the size of the queue B. Specifically, when the driver 4 receives the bounding box area S and the DMA command A, the DMA command rearrangement unit 41 receives the bounding box area S received by the driver 4 and the DMA that the VG accelerator 5 is processing. The order of the DMA commands A in the queue B is changed based on the bounding box area S corresponding to the command A and the bounding box area S corresponding to the DMA command A already arranged in the queue B. To do. More specifically, the DMA command rearrangement unit 41 includes the area S of the bounding box of the DMA commands A adjacent to each other in the queue B, including the DMA command A that the VG accelerator 5 last received from the driver 4. The order of DMA commands A in queue B is changed so that the sum of the differences is minimized.

  FIG. 3 is a block diagram illustrating an example of a physical configuration of the vector image drawing apparatus 1 according to the present embodiment. The vector image drawing apparatus 1 according to the present invention can be realized by a hardware configuration similar to a general computer apparatus. As shown in FIG. 3, the vector image drawing apparatus 1 includes a control unit 51, a main storage unit 52, an external storage unit 53, an operation unit 54, a display device 55, and an input / output unit 56. The main storage unit 52, the external storage unit 53, the operation unit 54, the display device 55, and the input / output unit 56 are all connected to the control unit 51 via the internal bus 50.

  The control unit 51 includes a CPU (Central Processing Unit) and the like, and executes processing for drawing a vector image in accordance with a program stored in the external storage unit 53.

  The main storage unit 52 includes a RAM (Random-Access Memory) or the like, loads a program stored in the external storage unit 53, and is used as a work area for the control unit 51. The path 6, the coordinate transformation matrix 7, the attribute 8, the area S, and the DMA command A illustrated in FIG. 1 are stored in the main storage unit 52.

  The external storage unit 53 includes a non-volatile memory such as a flash memory, a hard disk, a DVD-RAM (Digital Versatile Disc Random Access Memory), a DVD-RW (Digital Versatile Disc ReWritable), and the above processing is performed by the control unit 51. A program to be executed is stored in advance, and in accordance with an instruction from the control unit 51, data stored in the program is supplied to the control unit 51, and data supplied from the control unit 51 is stored.

  The operation unit 54 includes a pointing device such as a keyboard and a mouse, and an interface device that connects the keyboard and pointing device to the internal bus 50. An instruction for creating, inputting, and transmitting / receiving a vector image, designation of a vector image to be displayed, a range of a drawing area, an enlargement ratio, a position of the drawing area on a display device, and the like are input via the operation unit 54, and Supplied.

  The display device 55 includes a CRT (Cathode Ray Tube) or an LCD (Liquid Crystal Display), and displays a drawn vector image.

  The input / output unit 56 includes a wireless transceiver, a wireless modem or network termination device, and a serial interface or a LAN (Local Area Network) interface connected thereto. The vector image can be received and transmitted via the input / output unit 56.

  A vector image drawing apparatus 1 according to the present invention is configured as an electronic circuit by mounting a circuit composed of hardware parts such as LSI (Large Scale Integration) incorporating a circuit for realizing the function of drawing the vector image. can do.

  Further, the vector image drawing apparatus 1 according to the present invention may be mounted with an FPGA (Field Programmable Gate Array) which is an LSI capable of realizing the function of drawing the vector image by programming.

  Moreover, the vector image drawing apparatus 1 which implement | achieves each said function is performed by the control part 51 on a computer processing apparatus, The vector image drawing apparatus 1 is realizable like software. In that case, the CPU of the control unit 51 loads the vector image drawing program stored in the external storage unit 53 to the main storage unit 52 and executes it, and controls the operation of each unit to perform the above functions. Thus, the vector image drawing apparatus 1 is realized by software.

  Next, the algorithm of the DMA command A rearrangement process executed by the DMA command rearrangement unit 41 of the driver 4 will be specifically described. Note that the rearrangement process of the DMA command A is performed by the vector image drawing program using the main storage unit 52, the external storage unit 53, the operation unit 54, the display device 55, and the input / output unit 56 as resources. Do by working with.

  FIG. 4 is a flowchart showing an example of the operation of the rearrangement process of the DMA command A, and FIG. 5 is a diagram for explaining the rearrangement operation by the process of FIG.

  FIG. 5 shows a state in which DMA commands A2, A3, and A4 are sequentially sent to the queue B when the VG accelerator 5 processes the DMA command A1. In the following, the rearrangement process shown in FIG. 4 will be described by taking an example of the process executed when DMA commands A2, A3, A4 are sent to queue B as shown in FIG. In FIG. 5, the depth of the queue B is three stages (a state where three DMA commands A can be arranged in the queue B). The number displayed inside the square indicating the DMA command A indicates the area S of the bounding box sent to the driver 4 simultaneously with each DMA command A. The bounding box areas S corresponding to the DMA commands A1, A2, A3, and A4 are 5, 1, 3, and 2, respectively.

  First, as shown by 301 in FIG. 5, when the DMA command A2 is sent to the queue B, that is, when the driver 4 receives the DMA command A2 (step S201), the DMA command rearrangement unit 41 determines that the queue B is It is determined whether or not it is empty (step S202). At this time, in step S202, it is determined YES because the queue B is empty, the DMA command A2 is placed at the head of the queue B (step S203), and the processing shown in FIG.

  Next, as indicated by 302 in FIG. 5, when the DMA command A3 is sent to the queue B, that is, when the driver 4 receives the DMA command A3 (step S201), in the subsequent step S202, the DMA is transferred to the queue B. Since the command A2 is already arranged, it is determined as NO and the process proceeds to step S204.

  Next, the DMA command rearrangement unit 41 extracts all the orders of the DMA commands A that can be arranged in the queue B (step S204). A pattern P1 shown in FIG. 6 indicates the order of the DMA commands A extracted at this time. In the order shown in the first line L1 of the pattern P1, the DMA command A2 that has already been placed in the queue B is positioned at the head of the queue B, and the DMA command A3 that is newly sent to the queue B is the queue. B is the second position. In the order shown in the second line L2 of the pattern P1, the order in the queue B is opposite to the order shown in the first line L1, the DMA command A3 is located at the head, and the DMA command A2 is 2 Is located in th. The numbers in parentheses shown in FIG. 6 indicate the bounding box area S to which each DMA command A corresponds.

  Referring to FIG. 4, when step S204 is executed, DMA command rearrangement unit 41 sets the first line L1 of pattern P1 as the order of calculating the difference in bounding box area S between adjacent DMA commands A. Is selected (step S205).

  Next, the DMA command rearrangement unit 41 converts the DMA command A2 positioned at the head of the queue B in the order selected in step S205 (the order indicated by the first line L1 of the pattern P1) between the adjacent DMA commands A. Is selected as a reference DMA command for calculating the area difference of the bounding box (hereinafter referred to as an area difference calculation reference DMA command) (step S206).

  Next, the DMA command rearrangement unit 41 determines whether or not the area difference calculation reference DMA command A2 selected in step S206 is positioned at the head of the queue B (step S207). At this time, since the DMA command A2 is located at the head of the queue B in the order indicated by the first line L1 of the pattern P1, YES is determined in step S207, and the process proceeds to step S208.

  The DMA command rearrangement unit 41 then calculates the bounding box area S (1) corresponding to the area difference calculation reference DMA command A2 and the bounding box area S (1) corresponding to the DMA command A1 being processed by the VG accelerator 5. The area difference from 5) is calculated (step S208). At this time, an area difference of 4 is calculated from the calculation of | 5-1 | = 4.

  Next, the DMA command rearrangement unit 41 calculates all the differences in the bounding box area S between adjacent DMA commands A in the order in which the bounding box area difference is calculated (the order indicated by the first line L1 of the pattern P1). It is determined whether or not the calculation has been performed (step S209). At this time, since the difference between the bounding box area S (1) corresponding to the DMA command A2 and the bounding box area S (3) corresponding to the DMA command A3 is not calculated, the DMA command rearranging unit 41 , NO, and the process proceeds to step S210.

  Then, the DMA command rearranging unit 41 changes the area difference calculation reference DMA command A (step S210). Specifically, the DMA command A3 is changed to the DMA command A3 positioned immediately after the DMA command A2 in the queue B in the order of calculating the area difference of the bounding box (the order indicated by the first line L1 of the pattern P1). .

  Next, the DMA command rearrangement unit 41 proceeds to the process of step S207 again. At this time, in the order shown in the first line L1 of the pattern P1, since the DMA command A3 as the area difference calculation reference is located second in the queue B, the DMA command rearrangement unit 41 determines NO. Then, the process proceeds to step S211.

  In step S211, the DMA command rearrangement unit 41 determines the bounding box area S (3) corresponding to the DMA command A3 and the bounding box area S corresponding to the DMA command A2 located immediately before the DMA command A. The area difference from (1) is calculated. At this time, the area difference of 2 is calculated from the calculation of | 3-1 | = 2.

  Next, the DMA command rearrangement unit 41 proceeds to step S209. At this time, in the order shown in the first line of the pattern P1, since the difference in the area S of the bounding box between the adjacent DMA commands A has already been calculated, the DMA command rearrangement unit 41 determines YES. Then, the process proceeds to step S212.

  Then, the DMA command rearrangement unit 41 determines whether or not the bounding box area difference has been calculated for all the orders extracted in step S204 (step S212). At this time, since the area difference of the bounding box is not calculated for the order shown in the second line L2 of the pattern P1, the DMA command rearrangement unit 41 determines NO and proceeds to step S213.

  Then, the DMA command rearrangement unit 41 changes the order of calculating the bounding box area difference (step S213). Specifically, the order is changed to the order shown in the second line L2 which has not yet been selected as the order for calculating the area difference of the bounding box among all the orders extracted in step S203 (the order shown in the pattern P1).

  Then, the DMA command rearrangement unit 41 proceeds to the process of step S206 again.

  Thereafter, the above-described processing of S207 (YES) → S208 → S209 (NO) → S210 → S207 (NO) → S211 → S209 (YES) → S212 is executed with respect to the order shown in the second line L2 of the pattern P1. Is done. By this processing, the area difference between the bounding box area S (3) corresponding to the DMA command A3 and the bounding box area S (5) corresponding to the DMA command A1 is calculated from | 3-5 | = 2. 2 is calculated, and an area difference between the bounding box area S (1) corresponding to the DMA command A2 and the bounding box area S (3) corresponding to the DMA command A3 is | 1-3 | = 2. 2 is calculated from the above calculation.

  When the DMA command rearrangement unit 41 calculates all the differences in the bounding box area S between the adjacent DMA commands A in the order indicated by the second line L2 of the pattern P1, the DMA command rearrangement unit 41 determines YES in step S212. The process proceeds to step S214.

  In step S214, the DMA command rearrangement unit 41 calculates the total bounding box area difference for all the orders extracted in step S204 (step S214). At this time, the total area difference in the order indicated by the first line L1 of the pattern 1 is calculated from 4 + 2 = 6, and the total area difference in the order indicated by the second line L2 is calculated by 2 + 2 = 4. To 4 is calculated.

  Next, the DMA command rearrangement unit 41 rearranges the order of the DMA command A in the queue B into the order in which the total difference in the bounding box area is the smallest of the orders extracted in step S204 (step S215). At this time, in the order shown in the pattern P1 of FIG. 6, the total area difference in the order shown in the first line L1 is 6, and the total area difference in the order shown in the second line L2 is 4. The rearrangement unit 41 rearranges the order of the DMA commands A in the queue B in the order shown in the second line L2. As a result, in the queue B, the DMA command A3 is positioned at the head and the DMA command A2 is positioned at the second.

  After that, as shown by 303 in FIG. 5, when the DMA command A4 whose corresponding bounding box area is 2 is sent to the queue B, the processing shown in FIG. Executed. A pattern P2 shown in FIG. 6 shows all of the orders of the DMA commands A extracted in step S204 of this process and the total area difference in each order calculated in step S214. In the pattern P2, the order L3 shown in the sixth line L3 has the smallest total area difference of the bounding box. For this reason, the order of the DMA commands in the queue B is changed to the order shown in the sixth line L3 by the process of step S215. 304 of FIG. 5 shows a state in which the order of the DMA commands in the queue B is rearranged in the order shown in the sixth line L3.

  Note that in steps S208 and 211 shown in FIG. 4, the area difference between the bounding boxes has only to be obtained with an accuracy that allows the rearrangement of the DMA commands A in step S215. For example, when the vector graphic to be drawn by the vector accelerator is a Bezier curve or elliptical arc, the number S of dividing lines that approximately represent the Bezier curve or the like is reduced to calculate the bounding box area S. Becomes easier.

  As described above, according to the present embodiment, the order of the DMA commands A in the queue B is set to the order in which the sum of the differences of the bounding box areas S between the adjacent DMA commands A is minimized. The difference in the size of the vector graphic to be drawn between the DMA commands A adjacent in B becomes small. For this reason, since the change in the size of the vector graphic processed continuously by the VG accelerator 5 becomes small, the variation in the processing time of each stage in the VG accelerator 5 can be suppressed small. As a result, the DMA command A quickly shifts from the upper stage to the lower stage, and the total waiting time of each stage in the VG accelerator 5 is reduced. As a result, the drawing processing time of the VG accelerator 5 is shortened.

  In this embodiment, the DMA command A in the queue is minimized so that the sum of the difference in the bounding box area between adjacent processes, including the DMA command A last input to the VG accelerator 5, is minimized. The order is changed. For this reason, even when a new DMA command A is sent to the queue B during the processing of the vector graphics accelerator, the change in the size of the vector graphic to be continuously processed by the VG accelerator 5 can be suppressed. I can do it.

  The present invention has been described above with reference to preferred embodiments. However, the present invention is not necessarily limited to the above embodiments, and various modifications can be made within the scope of the technical idea. it can.

  For example, in the above-described embodiment, the bounding box generated by the bounding box calculation unit 31 is coordinate-converted to generate the bounding box surrounding the vector figure after the coordinate conversion process. A bounding box surrounding the vector figure may be generated by the bounding box calculation unit 31. In this case, the coordinate conversion of the bounding box by the coordinate conversion unit 32 is omitted, and the coordinate conversion unit 32 calculates the area of the bounding box generated by the bounding box calculation unit 31 and sends it to the driver 4.

  The following configurations are included as preferable modifications of the present invention.

About the vector image drawing device according to the first aspect of the present invention, preferably,
The region figure generating means, and generating a bounding rectangle of the vector graphic as the bounding box.

More preferably,
Coordinate conversion means for converting the bounding box coordinates,
The drawing process of the vector graphic includes a coordinate conversion process of the vector graphic,
It said area calculation means, and calculating the area of the bounding box of After coordinate transformation in the previous SL coordinate transformation means.

More preferably,
The region figure generating means calculates the bounding box surrounding the vector graphic before coordinate transformation,
The coordinate conversion means performs coordinate conversion of the bounding box generated by the area graphic generation means.

More preferably,
The driver includes a difference in area of the bounding box surrounding the vector graphic to be drawn for each of the two adjacent commands in the queue, including the last command placed in the queue. An absolute value is obtained, and the order of the commands in the queue is changed so that the sum of the absolute values is minimized .

Regarding the vector image drawing method according to the second aspect of the present invention, preferably,
In the area graphic generation step , the area graphic generation means generates a rectangle surrounding the vector graphic as a bounding box.

More preferably,
The coordinate conversion means includes a coordinate conversion step for converting the bounding box.
The drawing process of the vector graphic includes a coordinate conversion process of the vector graphic,
In the area calculation step , the area calculation means calculates the area of the bounding box after the coordinate conversion in the coordinate conversion step.

More preferably,
In the region figure generating step, the region figure generating means calculates a bounding box surrounding the vector graphics before coordinate transformation,
In the coordinate conversion step , the coordinate conversion means performs coordinate conversion of the bounding box generated in the area graphic generation step.

More preferably,
In the command placement step, the driver includes the bounding surrounding the vector graphic to be drawn for every two adjacent commands in the queue, including the last command placed in the queue. The absolute value of the difference in the area of the boxes is obtained, and the order of the commands in the queue is changed so that the sum of the absolute values is minimized .

  The above hardware configuration and flowchart are examples, and can be arbitrarily changed and modified.

  In addition, a central part that performs processing of the vector image drawing apparatus 1 including the control unit 51, the main storage unit 52, the external storage unit 53, the operation unit 54, the input / output unit 56, the internal bus 50, etc. Regardless of the system, it can be realized using a normal computer system. For example, a computer program for executing the above operation is stored and distributed in a computer-readable recording medium (flexible disk, CD-ROM, DVD-ROM, etc.), and the computer program is installed in the computer. Thus, the vector image drawing apparatus 1 that executes the above-described processing may be configured. Alternatively, the vector image drawing apparatus 1 may be configured by storing the computer program in a storage device included in a server device on a communication network such as the Internet and downloading it by a normal computer system.

  Further, when the function of the vector image drawing apparatus 1 is realized by sharing an OS (operating system) and an application program, or by cooperation between the OS and the application program, only the application program portion is stored in a recording medium or a storage device. It may be stored.

  It is also possible to superimpose a computer program on a carrier wave and distribute it via a communication network. For example, the computer program may be posted on a bulletin board (BBS, Bulletin Board System) on a communication network, and the computer program distributed via the network. The computer program may be started and executed in the same manner as other application programs under the control of the OS, so that the above-described processing may be executed.

It is a block diagram which shows an example of a structure of the vector image drawing apparatus which concerns on embodiment of this invention. It is a figure which shows the example of a bounding box. It is a block diagram which shows an example of the physical structure of the vector image drawing apparatus which concerns on this Embodiment. It is a flowchart which shows an example of operation | movement of the rearrangement process of the DMA command which concerns on embodiment of this invention. It is a figure explaining rearrangement operation. FIG. 6 illustrates the order of DMA commands that can be placed in a queue. It is a block diagram which shows an example of a structure of the vector image drawing apparatus different from the vector image drawing apparatus of this invention.

Explanation of symbols

1 Vector image drawing device 5 Vector graphics accelerator (pipe)
31 area figure generation part (bounding box calculation means)
32 Coordinate converter (area calculation means, coordinate conversion means)
41 DMA command rearrangement unit (rearrangement means)
51 Control Unit 52 Main Storage Unit 53 External Storage Unit 56 Input / Output Unit A DMA Command (Drawing Process)
B Queue S Bounding box area

Claims (11)

A region figure generating means for generating a bounding box is a figure that surrounds the base compactors figure for drawing the vector image,
Area calculating means for calculating the area of the bounding box generated by the area graphic generating means;
A command for executing the drawing process of the vector graphic is arranged in a queue, and the difference in the area of the bounding box surrounding the vector graphic to be drawn is set for each of the two adjacent commands in the queue. A driver that changes the order of the commands in the queue so that the sum of the absolute values is minimized.
An accelerator that receives the commands arranged in the queue in order from the top command and performs the drawing process of the vector graphic;
A vector image drawing apparatus comprising: The region figure generating means, the vector image drawing device according to claim 1, characterized in that generating a bounding rectangle of the vector graphic as the bounding box. Coordinate conversion means for converting the bounding box coordinates,
The drawing process of the vector graphic includes a coordinate conversion process of the vector graphic,
The area calculation unit, the vector image drawing device according to claim 1 or 2, characterized in that to calculate the area of the bounding box of After coordinate transformation in the previous SL coordinate transformation means. The region figure generating means calculates the bounding box surrounding the vector graphic before coordinate transformation,
4. The vector image image apparatus according to claim 3, wherein the coordinate conversion means performs coordinate conversion of the bounding box generated by the area graphic generation means. The driver includes a difference in area of the bounding box surrounding the vector graphic to be drawn for each of the two adjacent commands in the queue, including the last command placed in the queue. 5. The vector image according to claim 1 , wherein an absolute value is obtained and the order of the commands in the queue is changed so that a sum of the absolute values is minimized. Drawing device. A drawing method in which a vector image drawing apparatus performs drawing processing of a vector figure in order to draw a vector image,
An area graphic generation means for generating a bounding box that is a graphic surrounding a vector graphic for drawing a vector image ;
An area calculating means for calculating an area of the bounding box generated in the region graphic generating step;
The driver places a command for executing the drawing process of the vector graphic in the queue, and for each of the two adjacent commands in the queue, the driver includes the bounding box surrounding the vector graphic to be drawn. A command placement step of obtaining an absolute value of the difference in area and changing the order of the commands in the queue so that the sum of the absolute values is minimized;
A drawing step in which an accelerator receives the commands arranged in the queue in order from the top command, and performs drawing processing of the vector graphic;
A vector image drawing method comprising: The vector image drawing method according to claim 6, wherein, in the region graphic generation step , the region graphic generation unit generates a rectangle surrounding the vector graphic as a bounding box. The coordinate conversion means includes a coordinate conversion step for converting the bounding box.
The drawing process of the vector graphic includes a coordinate conversion process of the vector graphic,
8. The vector image drawing method according to claim 6, wherein, in the area calculation step , the area calculation means calculates an area of a bounding box after coordinate conversion in the coordinate conversion step. In the region figure generating step, the region figure generating means calculates a bounding box surrounding the vector graphics before coordinate transformation,
9. The vector image drawing method according to claim 8, wherein in the coordinate conversion step , the coordinate conversion means performs coordinate conversion of the bounding box generated in the area graphic generation step. In the command placement step, the driver includes the bounding surrounding the vector graphic to be drawn for every two adjacent commands in the queue, including the last command placed in the queue. 10. The absolute value of the difference in box area is obtained, and the order of the commands in the queue is changed so that the sum of the absolute values is minimized. The vector image drawing method according to the item. The computer,
Area graphic generation means for generating a bounding box that is a graphic surrounding a vector graphic for drawing a vector image ;
Area calculating means for calculating the area of the bounding box generated by the area graphic generating means ;
A command for executing the drawing process of the vector graphic is arranged in a queue, and the difference in the area of the bounding box surrounding the vector graphic to be drawn is set for each of the two adjacent commands in the queue. A driver that changes the order of the commands in the queue so that the sum of the absolute values is minimized.
An accelerator that receives the commands arranged in the queue in order from the top of the commands and performs the drawing process of the vector graphic;
A program characterized by functioning as

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