JP4865367B2 - Semiconductor integrated circuit, display device, and electronic device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device having a negative voltage booster circuit that generates a negative voltage lower than the power supply voltage based on the power supply voltage, and a positive voltage booster circuit that generates a positive voltage higher than the power supply voltage based on the power supply voltage. The present invention relates to a display device including the device and an electronic apparatus including the display device. In particular, the present invention relates to a technique for stably starting a negative voltage booster circuit and a positive voltage booster circuit.

As the power supply voltage is lowered, a semiconductor integrated circuit device used for displaying a liquid crystal panel is required to have a booster circuit that generates a high voltage for driving the liquid crystal. As a built-in conventional booster circuit, means for boosting a power supply voltage applied from the outside using a capacitor by using charge and discharge is well known. (See Patent Document 1). In particular, in a semiconductor integrated circuit device used for displaying a liquid crystal panel, a negative voltage booster circuit that generates a negative voltage lower than a power supply voltage applied from the outside, and a positive voltage booster circuit that generates a positive voltage higher than the power supply voltage A configuration in which both are incorporated is widely known.
JP 62-150597 A

  In a semiconductor integrated circuit device that incorporates both a negative voltage booster circuit that generates a negative voltage lower than a power supply voltage applied from the outside and a positive voltage booster circuit that generates a positive voltage higher than the power supply voltage, as described above. The negative voltage is connected to the substrate of the semiconductor integrated circuit and the voltage generated from the negative voltage booster circuit is supplied to the substrate of the semiconductor integrated circuit.

  In particular, a liquid crystal driving semiconductor integrated circuit device for displaying a liquid crystal panel has a built-in negative voltage booster circuit that multiplies the power supply voltage by an integer, and generates a negative voltage whose polarity is inverted by multiplying the power supply voltage by an integer. And supply. The positive voltage booster circuit generates a positive voltage higher than the power supply voltage with reference to a voltage arbitrarily generated between the negative voltage generated from the negative voltage booster circuit and the power supply voltage and the ground potential.

  In the process in which the positive voltage booster circuit starts boosting, an excessive current generated to accumulate charges in the boosting capacitor is instantaneously applied to the boosted output of the negative voltage booster circuit. There is a problem that the voltage of the boost output of the circuit fluctuates, and the negative voltage boost circuit and the positive voltage boost circuit cannot be normally started.

  In addition, when the positive voltage booster circuit starts the boosting operation, an excessive current generated by turning on the parasitic bipolar transistor that is parasitically present is instantaneously applied to the boosted output of the negative voltage booster circuit, and the excessive voltage is increased. There is a problem that the voltage of the boost output of the negative voltage booster circuit fluctuates due to the generation of current, and the negative voltage booster circuit and the positive voltage booster circuit cannot be started up normally.

  The configuration and operation of a conventional negative voltage booster circuit that generates a negative voltage lower than a power supply voltage applied from the outside and a positive voltage booster circuit that generates a positive voltage higher than the power supply voltage will be described with reference to FIG. .

  In FIG. 7, GND is a ground potential, and VDD is a power supply voltage applied from the outside. In the example of this figure, the negative voltage booster circuit 11 is a circuit that generates a voltage VSUB whose polarity is inverted by doubling the power supply voltage VDD.

  The negative voltage booster circuit 11 includes an inverter 111 and an inverter 112 configured between the power supply voltage VDD and the ground potential GND, MOS transistors Q1, Q2, and Q3, and boost capacitors C1, C2, and C3. Clock signals CLK1, CLK2, CLK3, CLK4, and CLK5 for controlling the boosting operation are generated by a circuit (not shown) incorporated in the semiconductor integrated circuit device, and are respectively input terminal of inverter 111, input terminal of inverter 112, and gate of MOS transistor Q1. It is input to the electrode, the gate electrode of Q2, and the gate electrode of Q3. The source electrode of the MOS transistor is connected to the ground potential GND. The output terminal of inverter 111 is connected to one side electrode (node n1) of boosting capacitor C1, and the other electrode (node n2) of C1 is connected to the drain electrode of transistor Q1 and the source electrode of transistor Q2. The output terminal of inverter 112 is connected to one side electrode (node n3) of boosting capacitor C2, and the other electrode (node n4) of boosting capacitor C2 is connected to the drain electrode of transistor Q2 and the drain electrode of transistor Q3. The source electrode (node n5) of the transistor Q3 is connected to one side electrode of the boosting capacitor C3, and the other electrode of the boosting capacitor C3 is connected to the ground potential GND. The node n5 is a boost output signal of the negative voltage booster circuit, which is connected to a substrate (here, P substrate) of a semiconductor integrated circuit device incorporating the negative voltage booster circuit, although not shown.

  The reference voltage generating circuit 12 for the positive voltage booster circuit is a circuit arranged between the power supply voltage VDD and the voltage VSUB of the boosted output signal (node n5) of the negative voltage booster circuit, and is based on the ground potential GND. A reference voltage signal (node n6) is generated.

  The positive voltage booster circuit 13 generates a boost output signal (node n9) obtained by inverting the polarity of the voltage VREF of the reference voltage signal (node n6) with reference to the ground potential GND.

  The positive voltage booster circuit 13 includes MOS transistors Q4, Q5, Q6, Q7 and boosting capacitors C4, C5. Clock signals CLK6, CLK7, CLK8, and CLK9 for controlling the boosting operation are generated by a circuit (not shown) built in the semiconductor integrated circuit device, and the gate electrode of MOS transistor Q4, the gate electrode of Q5, the gate electrode of Q6, and the gate electrode of Q7, respectively. Input to the gate electrode.

  One side electrode (node n7) of boost capacitor C4 is connected to the drain electrode of MOS transistor Q4 and the source electrode of MOS transistor Q5, and the other electrode (node n8) of C4 is the drain electrode of MOS transistor Q6 and the drain electrode of MOS transistor Q7. Connected to the electrode. The drain electrode of MOS transistor Q5 and the source electrode of MOS transistor Q6 are connected to ground potential GND. The source electrode (node n9) of MOS transistor Q4 is connected to one side electrode of boosting capacitor C5. The other electrode of the boost capacitor C5 is connected to the ground potential GND. The drain electrode of the MOS transistor Q7 is connected to the reference voltage signal (node n6) generated by the positive voltage booster circuit reference voltage generation circuit 12. Node n9 is a boosted output signal of the positive voltage booster circuit and outputs voltage VCH.

  Here, the operation when the negative voltage booster circuit 11, the positive voltage booster circuit reference voltage generation circuit 12, and the positive voltage booster circuit 13 start operation will be described with reference to the timing chart of FIG. When the clock signals CLK1 to CLK5 start operating at timing t1 shown in FIG. 8, the negative voltage booster circuit 11 starts boosting operation. FIG. 8 shows a representative signal CLK1 among the clock signals CLK1 to CLK5.

  In the negative voltage booster circuit 11, the logic of the output (node n1) of the inverter 111 is H (high), the logic of the output (node n3) of the inverter 112 is L (low), and the MOS transistor The phase when Q1 and Q3 are on and the MOS transistor Q2 is off, the logic of the output of the inverter 111 (node n1) is L (low), and the logic of the output of the inverter 112 (node n3) is H (high) In addition, by alternately repeating the phases in which the MOS transistors Q1 and Q3 are turned off and the MOS transistor Q2 is turned on, the boosting operation is started, and the voltage VSUB is generated in the negative voltage boosted output signal (node n6). Although the negative voltage boost output signal (node n6) is not shown here, it is connected to the substrate (here, P substrate) of the semiconductor integrated circuit device incorporating the negative voltage boost circuit, so that the substrate potential is changed to the voltage VSUB. Biased. When the negative voltage boost output signal (node n6) generates the voltage VSUB, the positive voltage boost circuit reference voltage generation circuit 12 configured between the power supply voltage VDD and the voltage VSUB is a reference voltage signal (referenced to the ground potential GND). Node n6) is generated, and voltage VREF is generated at node n6.

  When the clock signals CLK6 to CLK9 start operating at timing t2 shown in FIG. 8, the positive voltage booster circuit 13 starts boosting operation. FIG. 8 shows a typical signal CLK6 among the clock signals CLK6 to CLK9.

  The positive voltage booster circuit 13 starts the boost operation by alternately repeating the phase in which the MOS transistors Q5 and Q7 are turned on and the phase in which the MOS transistors Q4 and Q6 are turned on in response to the clock signals CLK6 to CLK9. The output signal (node n9) generates a voltage VCH. Until the voltage VCH reaches a steady value, the voltages VREF and VSUB fluctuate temporarily.

  Here, when the positive voltage booster circuit 13 starts operating at the timing t2 shown in FIG. 8 with reference to FIGS. 9 and 10, the bipolar transistor that exists parasitically in the semiconductor integrated circuit device is turned ON. A problem that prevents the positive voltage booster circuit 13 and the voltage booster circuit 11 from starting normally will be described.

  FIG. 9 is a timing chart when the positive booster booster circuit 13 starts operating at timing t2. FIG. 10 is a diagram showing the device structure of the MOS transistor Q6.

  In a period T1 shown in FIG. 9, the MOS transistors Q5 and Q7 are turned on, the node n7 and the ground potential GND are electrically short-circuited, and the node n8 and the node n6 are electrically short-circuited. Accordingly, the voltage of each electrode of the boosting capacitor C4 is set to GND and the voltage VREF, and the boosting capacitor C4 is charged with a charge determined by the capacitance value and the voltage VREF.

  In a period T2 shown in FIG. 9, the MOS transistors Q4 and Q6 are turned on, the node n7 and the node n9 are electrically short-circuited, and the node n8 and GND are electrically short-circuited. Accordingly, the voltage of each electrode of the boosting capacitor C4 is set to the voltages VCH and GND, and a part of the charge charged in the boosting capacitor C4 in the period T1 is transferred to the capacitor C5, and the output signal of the positive voltage booster circuit 13 The voltage VCH rises.

  In a period T3 shown in FIG. 9, the state is set to the same state as in the period T1, and the boosting capacitor C4 performs an operation of replenishing the charge delivered to the capacitor C5 in the period T2.

  In a period T4 shown in FIG. 9, the state is set to be the same as that in the period T2, and an operation of transferring a part of the charge charged in the boosting capacitor C4 to the capacitor C5 in the period T3 is performed.

  By repeating the above-described operations sequentially, a positive voltage boosting operation is realized, and ideally, a voltage obtained by inverting the polarity of the voltage VREF of the reference voltage signal (node n6) is output and stabilized.

  In the period T1 and the period T3, the voltage of each electrode of the boosting capacitor C4 is set to GND and the voltage VREF, and the boosting capacitor C4 is charged, but this charge current is negative voltage boosted via the node n6. It is supplied from the boosted output signal node n5 of the circuit 11.

  At the timing when the period T3 is switched to the period T4, the source electrode (GND) and the drain electrode (node n8) of the MOS transistor Q6 are caused by the ON resistance of the MOS transistor Q6 and the current generated by the movement of charges from the capacitors C4 to C5. A voltage is generated between the node n8 and the node n8 is higher than the GND potential.

  The operation at this time will be described with reference to the device structure diagram of P channel MOS transistor Q6 shown in FIG. The drain electrode (node n8) of the P channel MOS transistor Q6 is connected to P + diffusion, the bulk electrode N well 201 of the P channel MOS transistor Q6 is short-circuited with the source electrode of the P channel MOS transistor Q6, and the GND voltage is applied. . Since N well 201 is manufactured on a P substrate of a semiconductor integrated circuit device, a P-N-P connection transistor is parasitic between drain electrode (node n8) of P channel MOS transistor Q6, N well 201 and P substrate. It is configured.

  In the above operation, if the drain electrode (node n8) of the P-channel MOS transistor Q6 becomes higher than the GND potential, the parasitic transistor connected to the PNP connection is turned on, and an excessive current flows from the node n8 to the P substrate. Occurs.

  The P substrate of the semiconductor integrated circuit device is connected to the boosted output signal (node n5) of the negative voltage booster circuit 11 and is biased to the voltage VSUB, but an excessive current to the P substrate is generated, so that the voltage VSUB of the P substrate is generated. There is a problem that the voltage of the negative voltage booster circuit 11 and the positive voltage booster circuit 13 does not start normally because the voltage fluctuates greatly and becomes higher than the ground potential GND depending on conditions.

  Further, when the positive voltage booster circuit starts the boosting operation, the operation of transferring the charge charged to the boosting capacitor C3 by the negative voltage booster circuit 11 through the capacitor C4 to the capacitor C5 is sequentially repeated. When the voltage booster circuit 13 tries to generate a large voltage at the node n9, an excessive current for charging is generated, and the voltage VSUB of the output signal node n5 of the negative voltage booster circuit 11 fluctuates greatly. There is a problem that the negative voltage booster circuit 11 and the positive voltage booster circuit 13 are not normally started up.

  The present invention has been made in view of such a problem, and has a negative voltage booster circuit for generating a negative voltage lower than the power supply voltage in the substrate or well region based on the power supply voltage. An object of the present invention is to stably start a negative voltage booster circuit or a positive voltage booster circuit in a semiconductor integrated circuit having a positive voltage booster circuit for generating a positive voltage higher than a power supply voltage in a well region.

  In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a negative voltage booster circuit that generates a negative voltage lower than the power supply voltage in the substrate or well region based on the power supply voltage, and a reference supplied to the positive voltage booster circuit. A semiconductor integrated circuit device comprising: a reference voltage generation circuit for a positive voltage booster circuit for generating a voltage; and a positive voltage booster circuit for generating a positive voltage higher than the power supply voltage in a well region based on the power supply voltage, The reference voltage generating circuit for the positive voltage booster circuit receives a reset signal for initializing the circuit and a clock signal for counting up an n-bit counter circuit (one or a plurality of bit counter circuits) provided therein, and After the voltage booster circuit starts the boosting operation, the counter signal is counted up by controlling the reset signal and the clock signal, so that the positive voltage The output voltage of the booster circuit reference voltage generation circuit and the output voltage of the positive voltage booster circuit are gradually increased as absolute values, and the logic of the output signal of the n-bit counter circuit is set in a circuit The counter circuit is stopped from counting up, and the output voltage of the reference voltage generating circuit for the positive voltage booster circuit and the output voltage of the positive voltage booster circuit are stabilized.

  The clock signal for counting up the n-bit counter circuit is generated from a signal obtained by dividing the clock signal for operating the positive voltage booster circuit.

  According to the means described above, a clock signal is input to the reference voltage generating circuit for the positive voltage booster circuit, and the input signal is pulse-driven at a certain timing to output the output voltage of the reference voltage generating circuit for the positive voltage booster circuit and the positive voltage. With the function to increase the output voltage of the voltage booster circuit as an absolute value in steps, the overcurrent generated to accumulate charge in the booster capacitor when the positive voltage booster circuit starts boosting is negative. The problem that the negative voltage booster circuit and the positive voltage booster circuit cannot be started normally is prevented before the voltage booster output of the voltage booster circuit is instantaneously applied to the booster output of the voltage booster circuit and the voltage of the booster output of the negative voltage booster circuit fluctuates. It becomes possible. Further, when the positive voltage booster circuit starts the boosting operation, an excessive current generated by turning on the parasitic bipolar transistor that is parasitically present is instantaneously applied to the boosted output of the negative voltage booster circuit, and the excessive voltage is increased. It is possible to prevent the problem that the voltage of the boost output of the negative voltage booster circuit fluctuates due to the generation of current, and the negative voltage booster circuit and the positive voltage booster circuit cannot be normally started.

  In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a negative voltage booster circuit that generates a negative voltage lower than the power supply voltage in the substrate or well region based on the power supply voltage, and a reference supplied to the positive voltage booster circuit. A semiconductor integrated circuit device comprising: a reference voltage generation circuit for a positive voltage booster circuit for generating a voltage; and a positive voltage booster circuit for generating a positive voltage higher than the power supply voltage in a well region based on the power supply voltage, The reference voltage generation circuit for the positive voltage booster circuit includes a reset signal for initializing the circuit, a clock signal for counting up an n-bit counter circuit (one or a plurality of bit counter circuits) provided therein, and a positive voltage booster circuit. After an n-bit selection signal for setting the output voltage to a predetermined voltage is input and the positive voltage booster circuit starts the boosting operation, the reset signal and the clock are set. By controlling the signal and counting up the counter circuit, the output voltage of the reference voltage generating circuit for the positive voltage booster circuit and the output voltage of the positive voltage booster circuit are gradually increased as absolute values, and the n Detecting that the logic of the output signal of the bit counter circuit coincides with the logic of the n-bit selection signal, stopping counting up of the counter circuit, and outputting the output voltage of the reference voltage generating circuit for the positive voltage booster circuit and the The output voltage of the positive voltage booster circuit was stabilized.

  The clock signal for counting up the n-bit counter circuit is generated from a signal obtained by dividing the clock signal for operating the positive voltage booster circuit.

  The semiconductor integrated circuit device according to the present invention includes a first booster circuit that inputs and boosts and outputs a power supply voltage, and an output of the first booster circuit based on an output of the first booster circuit. A second booster circuit that outputs an opposite polarity to a reference voltage, and inputs a boosted voltage of the first booster circuit from a ground potential to the boosted voltage. A semiconductor integrated circuit device comprising a reference voltage generation circuit for outputting to the second booster circuit while controlling the output voltage stepwise in a range.

  Further, the reference voltage generation circuit includes a counter that counts a clock and outputs a count value, a reference voltage generation circuit that generates a plurality of reference voltages, and the count value from the plurality of reference voltages corresponding to the count value. And a selection circuit that selects a reference voltage corresponding to the reference voltage, and outputs a voltage based on the reference voltage selected by the selection circuit.

  Further, the selection circuit sets a preset value to select a predetermined count value and a predetermined reference voltage corresponding thereto, and the reference voltage generation circuit outputs based on the reference voltage. be able to.

  A display device including the above-described semiconductor integrated circuit device can be configured.

  An electronic device including the above display device can be formed.

  According to the present invention, the clock signal is input to the reference voltage generating circuit for the positive voltage booster circuit, and the input signal is pulse-driven at a certain timing to output the output voltage of the reference voltage generating circuit for the positive voltage booster circuit and the output of the positive voltage booster circuit. With the function to increase the voltage step by step as an absolute value, an excessive current generated to accumulate electric charge in the boosting capacitor when the positive voltage boosting circuit starts boosting will cause the negative voltage boosting circuit to It is possible to prevent a problem in which the negative voltage booster circuit and the positive voltage booster circuit cannot be started normally because the voltage of the booster output of the negative voltage booster circuit fluctuates due to the occurrence of an excessive current that is instantaneously applied to the booster output. . Furthermore, when the positive voltage booster circuit starts the boosting operation, an excessive current generated by turning on the parasitic bipolar transistor that is parasitically present is instantaneously applied to the boosted output of the negative voltage booster circuit and the excessive voltage is increased. It is possible to prevent a problem that the voltage of the boost output of the negative voltage booster circuit fluctuates due to the current generation, and the negative voltage booster circuit and the positive voltage booster circuit cannot be normally started.

  Further, when the semiconductor integrated circuit device of the present application is applied to a liquid crystal drive display LSI that drives a liquid crystal panel using, for example, a thin film transistor (Thin Film Transistor), the output voltage of the positive voltage booster circuit is set to a predetermined voltage. The selection signal to be set can be set to a predetermined value according to the TFT characteristics of the panel to be used, and the boost output VCH must be set to a high voltage according to the TFT characteristics. Even in this case, the positive voltage booster circuit first boosts and outputs a relatively small voltage as an absolute value, and then performs an operation in which the boosted voltage gradually increases, so that the boosting operation can be started stably. In addition, even in an electronic device equipped with this display device, the operation of the electronic device is stabilized.

  The effects obtained in the present invention include the following. A semiconductor integrated circuit device according to the present invention includes a negative voltage booster circuit for generating a negative voltage lower than a power supply voltage in a substrate or a well region based on a power supply voltage, and a positive voltage higher than the power supply voltage based on the power supply voltage in a well region A semiconductor integrated circuit device comprising a positive voltage booster circuit for generating a positive voltage and a reference voltage generator circuit for a positive voltage booster circuit for generating a reference voltage to be supplied to the positive voltage booster circuit, the reference voltage generator circuit for a positive voltage booster circuit Since the positive voltage booster circuit has a function of changing the voltage of the reference voltage signal for the positive voltage booster circuit step by step after the operation of the positive voltage booster circuit, when the positive voltage booster circuit starts boosting, When the overcurrent generated to accumulate charges in the boosting capacitor or when the positive voltage booster circuit starts the boosting operation, the parasitic bipolar transistor that exists parasitically turns on. Boosting the output voltage of the negative voltage booster circuit is varied by excessive current generated can be prevented problems that the negative voltage booster circuit and a positive voltage booster circuit can not be started properly.

(Embodiment 1)
A semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic block diagram of a semiconductor integrated circuit device according to Embodiment 1 of the present invention.

  GND is a ground potential, and VDD is a power supply voltage applied from the outside. In the example of this figure, the negative voltage booster circuit 11 is a circuit that generates a voltage VSUB whose polarity is inverted by doubling the power supply voltage VDD.

  The reference voltage generation circuit 12 for the positive voltage booster circuit is a circuit configured between the power supply voltage VDD and the voltage VSUB of the boost output signal (node n5) of the negative voltage booster circuit. The constant voltage signal Vconst generated by the constant voltage generation circuit built in the circuit device is input, and the signal RESET for initializing the reference voltage generation circuit 12 for the positive voltage booster circuit and the internal counter circuit are counted up. A clock signal CLK10 is input.

  A voltage VREF of a reference voltage signal (node n6) with reference to the ground potential GND is set by a logic circuit having the constant voltage signal Vconst, the reset signal RESET, and the clock signal CLK10 as inputs.

  The positive voltage booster circuit 13 generates a voltage VCH as a boosted output signal (node n9) obtained by inverting the polarity of the voltage VREF of the reference voltage signal (node n6) with respect to the ground potential GND.

  FIG. 2 shows a specific circuit example of the reference voltage generating circuit 12 for the positive voltage booster circuit shown in FIG. The reference voltage generation circuit 12 for the positive voltage booster circuit includes a bleeder resistor 13, an impedance converter composed of an operational amplifier AMP1, an inverting amplifier circuit composed of an operational amplifier AMP2 and resistors R101 and R102, an n-bit counter circuit 16, and an arbitrary data detection circuit. 17 and a decoder circuit 20.

  The configuration and operation of the positive voltage booster reference voltage generating circuit 12 according to the first embodiment of the present invention will be described below.

  In FIG. 2, resistors R1 to R (m) constitute a bleeder resistor 13 formed between the ground potential GND and the constant voltage signal Vconst. The constant voltage signal Vconst and each signal divided by the bleeder resistor 13 are connected to one-side electrodes of the MOS switches SW1 to SW (m), respectively. The other electrodes of the MOS switches SW1 to SW (m) are all connected to the node n10. The AMP1 having the node n10 as an input has a function of impedance-converting the signal of the node n10, and outputs a signal (node n11) obtained by impedance-converting the node n10. AMP2 and resistors R101 and R102 constitute an inverting amplifier circuit. The voltage VOUT1 of the input signal (node n11) of AMP2 is multiplied by a coefficient determined by the ratio of the resistors R101 and R102 with reference to the ground potential GND, and a signal whose polarity is inverted is a node. Output to n6. At this time, the voltage VREF of the node n6 has a voltage value of VREF = − (R102 / R101) × (VOUT1).

  The counter circuit 16 that controls the voltage VREF of the reference voltage signal (node n6) receives the counter reset signal RESET and the clock signal CLK10 for counting up. When the clock signal CLK10 changes, the counter circuit 16 counts up and outputs n bits. Signals CNT1 to CNT (n) are output.

  The data match detection circuit 17 includes a NAND circuit 18 that receives the output signals CNT1 to CNT (n) of the n-bit counter circuit 16, and a 2-input AND circuit 19 that receives the output signal n12 of the NAND circuit 18. The The clock signal CLK10 is input to the other input of the AND circuit 19.

  In FIG. 2 showing a specific circuit example of the first embodiment of the present invention, a circuit that detects that all the logics of the output signals CNT1 to CNT (n) of the counter circuit 16 are H (high) is taken as an example. ing. The data coincidence detection circuit 17 is a circuit that detects that a predetermined input value set by a logic circuit that receives the output signals CNT1 to CNT (n) of the counter circuit 16 is input, and changes the predetermined logic value. Can be realized by changing the logic circuit shown by the NAND circuit 18.

  The counter circuit 16 performs a count-up operation when the clock signal CLK10 changes, and outputs counter values of n-bit output signals CNT1 to CNT (n). When the output signals CNT1 to CNT (n) match a predetermined value set by the logic circuit, the logic of the output signal node n12 of the NAND circuit 18 becomes L (low), and the output signal n13 of the AND circuit 19 is the clock signal CLK10. Regardless of the change, the counter circuit 16 is fixed at the low level and stops the count-up operation.

  The decoder circuit 20 receives the n-bit output signals CNT1 to CNT (n) of the counter circuit 16 and outputs m-bit signals DEC1 to DEC (m) obtained by decoding the signals CNT1 to CNT (n).

  The m-bit output signals DEC1 to DEC (m) of the decoder circuit 20 are connected to the MOS switches SW1 to SW (m), respectively, and the output signals CNT1 to CNT (n) of the counter circuit 16 are input to output m-bits. The values of the signals DEC1 to DEC (m) change and only one of the MOS switches SW1 to SW (m) is turned on.

  FIG. 3 is a timing chart showing the operation timing of the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 3, the output signals CNT1 to CNT (n) of the n-bit counter circuit 16 for controlling the voltage VREF of the reference voltage for the positive voltage booster circuit are n = 2, and the m-bit signals DEC1 to DEC (m ) Represents the operation when m = 4.

  When the clock signals CLK1 to CLK5 for operating the negative voltage booster circuit 11 start operating at the timing t1 shown in FIG. 3, the negative voltage booster circuit 11 starts the boost operation, and after a certain period, the voltage level is set to the level from the ground potential GND. A low stable voltage VSUB is output to the node n5. FIG. 3 shows a representative signal CLK1 among the clock signals CLK1 to CLK5. At timing t1, the logic of the reset signal RESET is set to H (high), the counter circuit 16 is initialized, and the output signal of the 2-bit counter circuit 16 is set to CNT1 = L (low) and CNT2 = L (low). The set 4-bit output signals DEC1 to DEC4 of the decoder circuit 20 turn on only the MOS switch SW1, and the voltage VOUT1 at the node n11 and the voltage VREF at the node n6 are generated as relatively small voltages.

  At timing t2 shown in FIG. 3, when the clock signals CLK6 to CLK9 for operating the positive voltage booster circuit 13 start operating, the positive voltage booster circuit 13 starts boosting operation. FIG. 3 shows a representative signal CLK6 among the clock signals CLK6 to CLK9. At the timing t2, the logic of the reset signal RESET changes from H (high) to L (low), but the voltage VOUT1 of the node n11 and the voltage VREF of the node n6 are absolute values until the clock signal CLK10 starts operating. A relatively small voltage is generated. The positive voltage booster circuit 13 starts the boosting operation with reference to the ground potential GND based on the relatively small voltage VREF as the absolute value of the node n6. After a certain period of time, the positive voltage booster circuit 13 applies a relatively small stable voltage VCH as the absolute value to the node n9. To output.

  When the clock signal CLK10 operates at the timing t3 shown in FIG. 3, the counter circuit 16 counts up and the output signal of the 2-bit counter circuit 16 is set to CNT1 = H (high) and CNT2 = L (low). Then, the 4-bit output signals DEC1 to DEC4 of the decoder circuit 20 turn on only the MOS switch SW2, and the voltage VOUT1 at the node n11 and the voltage VREF at the node n6 have voltages that increase as absolute values with respect to the voltage at the timing t2. The positive voltage booster circuit 13 starts the boosting operation with reference to the ground potential GND based on the voltage VREF of the node n6, which has become large as an absolute value, and after a certain period, the positive voltage booster circuit 13 increases the voltage at the timing t2. On the other hand, a stable voltage VCH, which is increased in absolute value, is output to node n9. To.

  At this time, the arbitrary data detection circuit 17 sets the signal node n12 for stopping the count-up operation of the counter circuit 16 to H (high) because the output signals CNT1 to CNT2 do not match the predetermined logic value set in the circuit. The count-up operation does not stop because it is set to).

  The operation at the timing t4 shown in FIG. 3 is the same as the operation at the timing t3.

  At timing t5 shown in FIG. 3, when the clock signal CLK10 operates, the counter circuit 16 counts up, and the output signal of the 2-bit counter circuit 16 becomes CNT1 = H (high) and CNT2 = H (high). The set 4-bit output signals DEC1 to DEC4 of the decoder circuit 20 turn on only the MOS switch SW4, and the voltage VOUT1 of the node n11 and the voltage VREF of the node n6 increase as absolute values with respect to the voltage at the timing t4. The positive voltage booster circuit 13 starts the boosting operation with reference to the ground potential GND based on the voltage VREF of the node n6, which has become large as an absolute value, and after a certain period of time, at the timing t4 A stable voltage VCH, which is increased as an absolute value with respect to the voltage, is supplied to the node n9. To output.

  However, at this time, the arbitrary data detection circuit 17 detects that the output signals CNT1 to CNT2 and the values set in a circuit form (CNT1 = H (high) and CNT2 = H (high) in the circuit example of FIG. 2) are obtained. Then, the signal node n12 for stopping the count-up operation of the counter circuit 16 is changed to L (low).

  Therefore, at the timing t6 shown in FIG. 3, since the signal node n12 for stopping the count-up operation of the data matching circuit 17 is set to L (low) even when the clock signal CLK10 operates, the counter circuit 16 counts. Without performing the up operation, the output signals CNT1 and CNT2 are fixed at values set in a circuit until the reset signal RESET becomes H (high).

  As described above, the positive voltage booster circuit 13 starts the boosting operation based on the ground potential GND based on the relatively small voltage VREF as an absolute value, and the boosted output VCH is stabilized under the condition, and then a certain time has elapsed. Every time the voltage VREF is gradually increased as an absolute value, the step-up operation is repeated with the ground potential GND as a reference based on the voltage VREF.

  In the semiconductor integrated circuit device according to the first embodiment of the present invention, the voltage VREF becomes stable when the output signals CNT1 to CNT (n) of the counter circuit 16 become equal to the circuit-set value, and the voltage VREF is maintained. At the same time, the output VCH of the positive voltage booster circuit 13 that performs the boosting operation with reference to the ground potential GND is also stabilized.

  In the semiconductor integrated circuit device according to the first embodiment of the present invention, the count-up clock signal CLK10 input to the positive voltage booster circuit reference voltage generation circuit 12 is input to the positive voltage booster circuit 13. The clock signals CLK6 to CLK9 for boosting operation may be constituted by signals divided by a frequency dividing circuit (not shown).

  As described above, in the semiconductor integrated circuit device according to the first embodiment, the clock signal CLK10 for controlling the voltage VREF of the reference voltage for the positive voltage booster circuit is input to the reference voltage generation circuit for the positive voltage booster circuit, and the input signal is provided. In order to accumulate charges in the boosting capacitor when the positive voltage boosting circuit starts boosting by providing a function to increase the reference voltage for the positive voltage boosting circuit stepwise as an absolute value by pulse driving at the timing The generated excessive current is instantaneously applied to the boost output of the negative voltage booster circuit, and the boost output voltage of the negative voltage booster circuit fluctuates due to the generation of the excessive current, and the negative voltage booster circuit and the positive voltage booster circuit cannot be started normally. The problem can be prevented. Further, when the positive voltage booster circuit starts the boosting operation, an excessive current generated by turning on the parasitic bipolar transistor that is parasitically present is instantaneously applied to the boosted output of the negative voltage booster circuit, and the excessive voltage is increased. The boosted output voltage of the negative voltage booster circuit fluctuates due to the generation of current, and it is possible to prevent a problem that the negative voltage booster circuit and the positive voltage booster circuit cannot be started normally.

(Embodiment 2)
A semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a schematic block diagram of a semiconductor integrated circuit device according to the second embodiment of the present invention.

  GND is a ground potential, and VDD is a power supply voltage applied from the outside. In the example of this figure, the negative voltage booster circuit 11 is a circuit that generates a voltage VSUB whose polarity is inverted by doubling the power supply voltage VDD.

  The reference voltage generation circuit 12 for the positive voltage booster circuit is a circuit configured between the power supply voltage VDD and the voltage VSUB of the boost output signal (node n5) of the negative voltage booster circuit. A constant voltage signal Vconst generated by a constant voltage generation circuit incorporated in the circuit device is input, and n-bit selection signals ASEL1 to ASEL (n for selecting one of a plurality of voltages obtained by dividing Vconst by resistance. ) Is entered. Further, a signal RESET for initializing the inside of the reference voltage generating circuit 12 for the positive voltage booster circuit and a clock signal CLK10 for counting up the internal counter circuit are input.

  The voltage VREF of the reference voltage signal (node n6) with reference to the ground potential GND is set by the logic of the voltage Vconst, the selection signals ASEL1 to ASEL (n), the reset signal RESET, and the clock signal CLK10. The positive voltage booster circuit 13 generates a voltage VCH as a boosted output signal (node n9) obtained by inverting the polarity of the voltage VREF of the reference voltage signal (node n6) with respect to the ground potential GND.

  FIG. 5 shows a specific circuit example of the reference voltage generating circuit 12 for the positive voltage booster circuit shown in FIG. The reference voltage generation circuit 12 for the positive voltage booster circuit includes a bleeder resistor 13, an impedance converter composed of an operational amplifier AMP1, an inverting amplifier circuit composed of an operational amplifier AMP2 and resistors R101 and R102, an n-bit counter circuit 16, and a data match detection circuit. 17 and a decoder circuit 20.

  The configuration and operation of the positive voltage booster reference voltage generating circuit 12 according to the second embodiment of the present invention will be described below.

  In FIG. 5, resistors R1 to R (m) constitute a bleeder resistor 13 connected in series between the ground potential GND and the voltage Vconst. Each signal divided by the bleeder resistor 13 is connected to one side electrodes of the MOS switches SW1 to SW (m). The other electrodes of the MOS switches SW1 to SW (m) are all connected to the node n10 and the operational amplifier AMP1 having the node n10 as an input has a function of impedance-converting the signal of the node n10, and a signal obtained by impedance-converting the signal of the node n10 (node The voltage VOUT1 is output to n11). The operational amplifier AMP2 and the resistors R101 and R102 constitute an inverting amplifier circuit. The voltage VOUT1 at the node n11 is multiplied by a coefficient determined by the ratio of the resistors R101 and R102 with respect to the ground potential GND, and a signal whose polarity is inverted is output to the node n6. . The voltage VREF at the node n6 has a voltage value of VREF = − (R102 / R101) × VOUT1.

  The counter circuit 16 that controls the voltage VREF of the reference voltage signal (node n6) receives the counter reset signal RESET and the clock signal CLK10 for counting up. When the clock signal CLK10 changes, the counter circuit 16 performs a count up operation and performs n-bit counting. Output signals CNT1 to CNT (n) are output. Detects that the combination of output signals CNT1 to CNT (n) matches the combination of n-bit selection signals ASEL1 to ASEL (n) for selecting one of a plurality of voltages obtained by resistance-dividing voltage Vconst. The data coincidence detection circuit 17 to be input has n EXNOR circuits, a NAND circuit 18 that receives the output signals COMP1 to COMP (n) of the n-bit EXNOR circuit, and a 2-input that receives the output signal n12 of the NAND circuit 18. It consists of an AND circuit 19. The clock signal CLK10 is input to the other input of the AND circuit 19.

  When the clock signal CLK10 changes, the counter circuit 16 performs a count-up operation and outputs the count values of the n-bit output signals CNT1 to CNT (n). When the combinations of the output signals CNT1 to CNT (n) and the selection signals ASEL1 to ASEL (n) match, the output signals COMP1 to COMP (n) of the EXNOR circuit all become H (high), and the output signal n13 of the AND circuit 19 is the clock signal. Regardless of the change of CLK10, the counter circuit 16 is fixed at the low level and stops the count-up operation. The decoder circuit 20 receives the n-bit output signals CNT1 to CNT (n) of the counter circuit 16, and outputs m-bit signals DEC1 to DEC (m) obtained by decoding the signals CNT1 to CNT (n).

  The m-bit output signals DEC1 to DEC (m) of the decoder circuit 20 are connected to the MOS switches SW1 to SW (m), respectively, and an m-bit output is obtained by combining the output signals CNT1 to CNT (n) of the counter circuit 16. The combination of the signals DEC1 to DEC (m) changes, and only one of the MOS switches SW1 to SW (m) is turned on.

  FIG. 6 is a timing chart showing the operation timing of the semiconductor integrated circuit device according to the second embodiment of the present invention. In FIG. 6, the output signals CNT1 to CNT (n) of the n-bit counter circuit 16 that controls the voltage VREF of the reference voltage for the positive voltage booster circuit are n = 3, and the m-bit signals DEC1 to DEC (m) of the decoder circuit 20 ) Represents the operation when m = 8.

  In FIG. 6, n-bit selection signals ASEL1 to ASEL (n) represent operations when ASEL1 = H (high), ASEL2 = H (high), and ASEL3 = L (low). Yes. When the clock signals CLK1 to CLK5 for operating the negative voltage booster circuit 11 start operation at the timing t1 shown in FIG. 6, the negative voltage booster circuit 11 starts the boost operation, and after a certain period, the voltage level is lower than the ground potential GND. A stable voltage VSUB is output to node n5.

  FIG. 6 shows a representative signal CLK1 among the clock signals CLK1 to CLK5. At timing t1, the logic of the reset signal RESET is set to H (high), the counter circuit 16 is initialized, and the output signals of the 3-bit counter circuit 16 are CNT1 = L (low), CNT2 = L (low), CNT3 = L (low) is set, and the 8-bit output signals DEC1 to DEC8 of the decoder circuit 20 turn on only the MOS switch SW1, and the voltage VOUT1 of the node n11 and the voltage VREF of the node n6 have relatively small voltages as absolute values. Generated.

  When the clock signals CLK6 to CLK9 for operating the positive voltage booster circuit 13 start operation at the timing t2 shown in FIG. 6, the positive voltage booster circuit 13 starts the boost operation. FIG. 6 shows a representative signal CLK6 among the clock signals CLK6 to CLK9. At the timing t2, the logic of the reset signal RESET changes from H (high) to L (low), but the voltage VOUT1 at the node n11 and the voltage VREF at the node n6 are absolute values until the clock signal CLK10 starts operating. A relatively small voltage is generated.

  The positive voltage booster circuit 13 starts a boosting operation with reference to the ground potential GND based on a relatively small voltage VREF as an absolute value of the node n6, and after a certain period, a relatively small stable voltage VCH as an absolute value is Output to n9.

  When the clock signal CLK10 operates at the timing t3 shown in FIG. 6, the counter circuit 16 counts up and the output signals of the 3-bit counter circuit 16 are CNT1 = H (high), CNT2 = L (low), and CNT3 = The 8-bit output signals DEC1 to DEC8 of the decoder circuit 20 set to L (low) turn on only the MOS switch SW2, and the voltage VOUT1 at the node n11 and the voltage VREF at the node n6 are absolute with respect to the voltage at the timing t2. A voltage that increases as a value is generated, and the positive voltage booster circuit 13 starts a boosting operation with reference to the ground potential GND based on the voltage VREF of the node n6 that has increased as an absolute value. , A stable voltage VC increased as an absolute value with respect to the voltage at timing t2. And outputs to the node n9. At this time, since the combination of the output signals CNT1 to CNT3 and the selection signals ASEL1 to ASEL3 do not match, the data match detection circuit 17 sets the node n12 to H (high) because the signal for stopping the count-up operation of the counter circuit 16 The count-up operation does not stop because it is set.

  The operation at timing t4 shown in FIG. 6 is the same as the operation at timing t3. At timing t5 shown in FIG. 6, when the clock signal CLK10 operates, the counter circuit 16 counts up, and the output signal of the 3-bit counter circuit 16 is CNT1 = H (high), CNT2 = H (high), CNT3 = L (low) and the 8-bit output signals DEC1 to DEC8 of the decoder circuit 20 turn on only the MOS switch SW4, and the voltage VOUT1 of the node n11 and the voltage VREF of the node n6 are compared with the voltage at the timing t4. A voltage that increases as an absolute value is generated, and the positive voltage booster circuit 13 starts a boosting operation with reference to the ground potential GND based on the voltage VREF of the node n6 that has increased as an absolute value. After that, the stable voltage V increased as an absolute value with respect to the voltage at the timing t4. And it outputs the H to node n9. However, at this time, the data coincidence detection circuit 17 detects that the combination of the output signals CNT1 to CNT3 and the selection signals ASEL1 to ASEL3 coincides, and sends a signal for stopping the count-up operation of the counter circuit 16 to the node n12 at L (low) Change. Accordingly, at the timing t6 shown in FIG. 6, the counter circuit 16 counts up because the signal node n12 for stopping the count-up operation of the data coincidence detection circuit 17 is set to L (low) even when the clock signal CLK10 operates. Without operation, the output signals CNT1 to CNT3 are fixed at the same value as the selection signals ASEL1 to ASEL3 until the reset signal RESET becomes H (high).

  As described above, the positive voltage booster circuit 13 starts the boosting operation with reference to the ground potential GND based on the relatively small voltage VREF as an absolute value, and the boosted output VCH is stabilized under the condition, and then a certain time passes. Every time, the operation of increasing the voltage VREF as an absolute value in steps is repeated, and the boosting operation is started again based on the ground potential GND based on the voltage VREF. In the semiconductor integrated circuit device according to the second embodiment of the present invention, the n-bit selection signals ASEL1 to ASEL (n) for selecting any one of the plurality of voltages divided by the resistance are input to the counter circuit 16. When the output signals CNT1 to CNT (n) are equal, the voltage VREF is stabilized, and the output VCH of the positive voltage booster circuit 13 that performs a boosting operation based on the ground potential GND based on the voltage VREF is also stabilized.

  In the semiconductor integrated circuit device according to the second embodiment of the present invention, the count-up clock signal CLK10 input to the positive voltage booster reference voltage generating circuit 12 is input to the positive voltage booster circuit 13. Alternatively, the clock signals CLK6 to CLK9 may be divided by a frequency dividing circuit (not shown).

  The case where the semiconductor integrated circuit device according to the second embodiment is applied to a liquid crystal display LSI for driving a liquid crystal panel using, for example, a thin film transistor (TFT) will be described below. When the boosted output VCH of the positive voltage booster circuit 13 is used as the gate voltage of the TFT of the TFT panel, the voltage VCH needs to be set to a voltage that matches the characteristics of the TFT used. When a high voltage of, for example, +15 V is required as the voltage VCH, in the conventional technique, an excessive current is generated when the positive voltage booster circuit 13 starts a boost operation, and the boosted output voltage of the negative voltage booster circuit 11 fluctuates. There was a problem that the negative voltage booster circuit 11 and the positive voltage booster circuit 13 could not start up normally. However, if the semiconductor integrated circuit device according to the second embodiment is used, the selection signals ASEL1 to ASEL (n) can be set to a predetermined value in accordance with the TFT characteristics of the panel using the selection signals ASEL1 to ASEL (n). At the same time, even when it is necessary to set the boost output VCH to a high voltage, the positive voltage boost circuit 13 first boosts and outputs a relatively small voltage as an absolute value, and then the boost voltage gradually increases. Since the operation is performed, the boosting operation can be started stably.

  As described above, in the semiconductor integrated circuit device according to the second embodiment, the clock signal CLK10 for controlling the voltage VREF of the reference voltage for the positive voltage booster circuit is input to the reference voltage generation circuit for the positive voltage booster circuit, and the input signal is given timing. In order to accumulate charges in the boosting capacitor when the positive voltage boosting circuit starts boosting, it has the function of increasing the reference voltage for the positive voltage boosting circuit stepwise as an absolute value. The generated excessive current is instantaneously applied to the boost output of the negative voltage booster circuit, and the boost output voltage of the negative voltage booster circuit fluctuates due to the generation of the excessive current, and the negative voltage booster circuit and the positive voltage booster circuit cannot be started normally. The problem can be prevented. Further, when the positive voltage booster circuit starts the boosting operation, an excessive current generated by turning on the parasitic bipolar transistor that is parasitically present is instantaneously applied to the boosted output of the negative voltage booster circuit, and the excessive voltage is increased. It is possible to prevent a problem in which the boosted output voltage of the negative voltage booster circuit fluctuates due to the generation of current and the negative voltage booster circuit and the positive voltage booster circuit cannot be normally started.

1 is a schematic block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a specific circuit example of a reference voltage generating circuit for a positive voltage booster circuit in the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is a timing chart showing the operation timing of the semiconductor integrated circuit device according to the first embodiment of the present invention. It is a schematic block diagram of the semiconductor integrated circuit device by Embodiment 2 of this invention. FIG. 6 is a circuit diagram showing a specific circuit example of a reference voltage generating circuit for a positive voltage booster circuit in a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 10 is a timing chart showing the operation timing of the semiconductor integrated circuit device according to the second embodiment of the present invention. It is a schematic block diagram of a negative voltage booster circuit that generates a negative voltage lower than a power supply voltage applied from the outside and a positive voltage booster circuit that generates a positive voltage higher than the power supply voltage. It is a timing chart showing the operation timing of a conventional semiconductor integrated circuit device. It is a timing chart explaining the operation | movement used as the subject of the conventional semiconductor integrated circuit device. It is a figure which shows the structure of the P channel MOS transistor of the semiconductor integrated circuit device of this invention.

Explanation of symbols

11 Negative voltage booster circuit 12 Reference voltage generation circuit for positive voltage booster circuit 13 Positive voltage booster circuit 16 Counter circuit 17 Data coincidence detection circuit 20 Decoder circuits CLK1, CLK2, CLK3, CLK4 Clocks CLK5, CLK6, CLK7 of the negative voltage booster circuit, CLK8 Clock of positive voltage booster circuit CLK10 Clock of reference voltage generation circuit for positive voltage booster circuit Reset signal R1-R (m) Resistor SW1-SW (m) Switch circuit AMP1, AMP2 Operational amplifier circuit

Claims (9)

A negative voltage booster circuit for generating a negative voltage lower than the power supply voltage in the substrate or well region based on the power supply voltage; a reference voltage generation circuit for a positive voltage booster circuit for generating a reference voltage to be supplied to the positive voltage booster circuit; a reference voltage of the reference voltage generating circuit for positive voltage booster circuit in the semiconductor integrated circuit device provided with a positive voltage boosting circuit for generating a high positive voltage than the power supply voltage based on the well region, for the positive voltage booster circuit The reference voltage generation circuit receives a reset signal for initializing the circuit and a clock signal for counting up an n-bit counter circuit provided therein, and after the positive voltage booster circuit starts a boost operation, By controlling the clock signal and counting up the counter circuit, the output voltage of the reference voltage generating circuit for the positive voltage booster circuit and the positive voltage booster The output voltage of the circuit is gradually increased as an absolute value, and it is detected that the logic of the output signal of the n-bit counter circuit becomes a logic set in a circuit, and the count-up of the counter circuit is stopped. A semiconductor integrated circuit device characterized in that an output voltage of the reference voltage generating circuit for the positive voltage booster circuit and an output voltage of the positive voltage booster circuit are stabilized.   2. The semiconductor integrated circuit device according to claim 1, wherein the clock signal for counting up the n-bit counter circuit is generated from a signal obtained by dividing the clock signal for operating the positive voltage booster circuit.   A negative voltage booster circuit for generating a negative voltage lower than the power supply voltage in the substrate or well region based on the power supply voltage; a reference voltage generation circuit for a positive voltage booster circuit for generating a reference voltage to be supplied to the positive voltage booster circuit; A semiconductor integrated circuit device comprising a positive voltage booster circuit for generating a positive voltage higher than a power supply voltage in a well region based on an output voltage and a power supply voltage of the negative voltage booster circuit, the reference voltage for the positive voltage booster circuit The generator circuit includes a reset signal for initializing the circuit, a clock signal for counting up an n-bit counter circuit provided therein, and an n-bit selection signal for setting the output voltage of the positive voltage booster circuit to a predetermined voltage. The positive voltage booster circuit is input, and after the positive voltage booster circuit starts the boosting operation, the counter signal is counted up by controlling the reset signal and the clock signal. The output voltage of the voltage booster circuit reference voltage generation circuit and the output voltage of the positive voltage booster circuit are gradually increased as absolute values, and the logic of the output signal of the n-bit counter circuit is the n-bit selection signal. The counter circuit stops counting up and stabilizes the output voltage of the reference voltage generation circuit for the positive voltage booster circuit and the output voltage of the positive voltage booster circuit. A semiconductor integrated circuit device.   4. The semiconductor integrated circuit device according to claim 3, wherein the clock signal for counting up the n-bit counter circuit is generated from a signal obtained by dividing the clock signal for operating the positive voltage booster circuit. A first booster circuit that inputs a power supply voltage and outputs a negative voltage lower than the ground potential;
A reference voltage circuit that inputs a negative voltage of the first booster circuit and outputs a reference voltage that gradually decreases in a range from the ground potential to the negative voltage;
A second booster circuit that outputs a positive voltage obtained by inverting and boosting with reference to the ground potential based on the reference voltage;
The reference voltage circuit reliably starts the second booster circuit by gradually decreasing the reference voltage after the second booster circuit starts the boosting operation.
The semiconductor integrated circuit device, characterized in that. The reference voltage circuit is
A counter that counts the clock and outputs a count value;
A reference voltage generating circuit for generating a plurality of reference voltages;
A selection circuit that selects a reference voltage corresponding to the count value from the plurality of reference voltages corresponding to the count value;
6. The semiconductor integrated circuit device according to claim 5, wherein a voltage based on a reference voltage selected by the selection circuit is output. The selection circuit, by setting the preset value, selects a predetermined reference voltage and the corresponding predetermined count value, the reference voltage generating circuit is characterized in that the output based on the reference voltage The semiconductor integrated circuit device according to claim 6.   A display device comprising the semiconductor integrated circuit device according to claim 1.   An electronic apparatus having the display device according to claim 8.

Images