JP4867452B2 - Image processing apparatus and printing apparatus - Google Patents

Description

  The present invention relates to an image processing apparatus, a printing apparatus, and an image processing method.

An apparatus that performs image processing by parallel processing using a plurality of processors has been proposed (see, for example, Patent Document 1).

Normally, when accessing a RAM (Random Access Memory) outside the processor from the processor, a large latency is generated in comparison with the required time per instruction of the processor. As a result, the processor stalls and does not proceed to the next process after the access request to the external RAM is issued based on the memory access instruction until the access process is completed. Therefore, in the case of a shared memory type device, the bus connected to the external RAM is common to a plurality of processors, so that the number of processors tends to increase as compared with the case of one processor.

To deal with this problem, if there is a cache, write buffer (store buffer), etc. for write processing, the processor completes the write processing and starts the next processing when data is written to the cache, write buffer, etc. Therefore, there are relatively few problems.

On the other hand, with respect to read processing, it is possible to reduce processor stall due to latency to some extent by providing a cache. For example, if the cache line size is 128 bits and the unit of access to the cache is 32 bits, a continuous area can be obtained by reading the cache for 128 bits in one access to the external RAM. Since the number of accesses when reading data from the memory is reduced, the stall period of the processor is shortened.

JP-A-2005-260424 (specifications, etc.)

However, in the case of a shared memory type device having a plurality of processors, even if such a cache is used, a processor stall period during read processing occurs. In particular, this problem becomes significant when image processing is performed by appropriately reading a table having a size larger than the size of the processor cache or internal RAM from the external RAM. In particular, when the image data to be processed is larger than the size of the cache or internal RAM of the processor, it is necessary to repeatedly read the data from the external RAM, so that the processor is likely to stall due to latency. .

The present invention has been made in view of the above problems, and in a shared memory type apparatus having a plurality of processors, an image processing apparatus capable of shortening the stall period of the processor and shortening the time required for image processing. And an image processing method, and a printing apparatus using the image processing method.

  In order to solve the above problems, the present invention is configured as follows.

An image processing apparatus according to the present invention is an image processing apparatus that includes a plurality of arithmetic processing means, a memory, and a bus that connects each of the plurality of arithmetic processing means and the memory. Any one of the arithmetic processing means, the arithmetic processing means for sequentially performing image processing on a series of image data using a table, and the arithmetic processing means operate independently of the image processing means. In parallel with the first memory access means for obtaining the image data from the memory via the bus and supplying it to the arithmetic processing means without going through the bus, the arithmetic processing means operates independently of the image processing of the arithmetic processing means. And second memory access means for obtaining a table from the memory via the bus and supplying the table to the arithmetic processing means without going through the bus.

As a result, since the memory access means executes data read from the shared memory, the processor stall period is shortened and the time required for image processing is shortened regardless of the shared memory type device having a plurality of processors. Can do.

In addition to the image processing apparatus described above, the image processing apparatus according to the present invention may be configured as follows. That is, in this case, the second memory access means acquires the lookup table from the memory via the bus and supplies the lookup table to the arithmetic processing means without going through the bus, and the arithmetic processing means uses the lookup table. Then, color conversion processing is performed on the image data.

As a result, since the memory access means executes data read from the shared memory, the stall period of the processor is shortened and the time required for the color conversion process is shortened regardless of the shared memory type device having a plurality of processors. be able to.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. That is, in this case, the second memory access means acquires the table used for halftone processing from the memory via the bus and supplies the table to the arithmetic processing means without going through the bus. Is used to perform halftone processing on the image data.

As a result, since the memory access means executes data reading from the shared memory, the processor stall period is shortened and the time required for the halftone process is shortened regardless of the shared memory type device having a plurality of processors. be able to.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In other words, in this case, the first memory access unit obtains the data queue that the arithmetic processing unit can read without going through the bus, and the start address from the arithmetic processing unit.
And a control circuit for acquiring image data from the memory in order from the head address via a bus and storing the image data in a data queue.

As a result, since the first memory access means reads the input data from the shared memory, the processor stall period is shortened and image processing is required regardless of the shared memory type device having a plurality of processors. Time can be shortened.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In other words, in this case, the second memory access means is stored in the address queue in which the arithmetic processing means can write without going through the bus, the data queue in which the arithmetic processing means can read without going through the bus, and the address queue. And a control circuit that acquires data at the address in the table from the memory via a bus and stores the data in a data queue.

As a result, the second memory access means executes the process of randomly reading the table from the shared memory, so that the processor stall period can be shortened and image processing can be performed regardless of the shared memory type apparatus having a plurality of processors. The time required can be shortened.

The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In other words, in this case, the arithmetic processing means has an internal memory having at least two banks. Then, when the second memory access means acquires the start address from the arithmetic processing means, it acquires data of a predetermined length from the start address from the memory via the bus, and either the one bank or the other bank of the internal memory. Store alternately.

Thus, since the second memory access means executes the process of sequentially reading the table from the shared memory, the processor stall period is shortened regardless of the shared memory type apparatus having a plurality of processors. Can be shortened.

A printing apparatus according to the present invention includes any one of the above-described image processing apparatuses, and performs printing processing based on data obtained by performing image processing by the image processing apparatus.

As a result, since the memory access means executes data reading from the shared memory, the processor stall period is shortened and the time required for image processing, and thus the printing time, regardless of the shared memory type device having a plurality of processors. Can be shortened.

An image processing method according to the present invention is an image processing method using an image processing apparatus including a plurality of arithmetic processing means, a memory, and a bus connecting each of the plurality of arithmetic processing means and the memory. A step of sequentially performing image processing on a series of image data using a table by any one of the arithmetic processing means, and a bus in parallel with the image processing of the arithmetic processing means. Acquiring the image data from the memory via the bus and supplying it to the arithmetic processing means without going through the bus, and acquiring the table from the memory via the bus in parallel with the image processing of the arithmetic processing means without going through the bus And supplying to the arithmetic processing means.

As a result, the data read from the shared memory is executed independently of the processor, so that the processor stall period is shortened and the time required for image processing is shortened regardless of the shared memory type device having a plurality of processors. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a hardware configuration of the image processing apparatus according to Embodiment 1 of the present invention. This image processing apparatus is built in a printing apparatus such as an ink jet printer, and is a shared memory type parallel processing apparatus that generates binarized data from image data such as RGB data.

In FIG. 1, a processor 1 is an arithmetic processor that controls the processors 2, 6, and 7 and controls the flow of image processing. The processor 2 is an arithmetic processing unit that controls the processors 3, 4, and 5 to execute image data decoding processing and image correction processing, and also executes resizing processing and layout processing. The decoding process is JPEG (Joint Picture Expert
s Group) is a process for decoding encoded image data such as data and generating RGB data. The resizing process is a process for converting the resolution of the RGB data. In the layout process, an image based on the resized RGB data is arranged in accordance with the printing paper.
This is a process for generating GB data. The processor 3 is an arithmetic processor that executes the first stage of the decoding process, and the processor 4 is an arithmetic processor that executes the latter stage of the decoding process. The processor 5 is an arithmetic processing unit that executes image correction processing.

The processor 6 is an arithmetic processing unit as arithmetic processing means for executing encoding processing of color conversion processing and halftone processing. CPU 6a is processor 6
It is the arithmetic processing circuit built in. The internal RAM 6b is an internal memory built in the processor 6 and connected to the CPU 6a without passing through the bus 9. A high-speed memory such as a static RAM is used for the internal RAM 6b.

In the first embodiment, as a halftone process, for example, a process disclosed in Japanese Patent Application Laid-Open No. 2004-297451 is executed. In this process, for example, an encoding table is used for each pixel block such as 4 × 2, and the pixel block is converted into the number of one of the binary values in the pixel block (hereinafter referred to as the number of dots). ). The encoded data has, for each pixel block, the position of the pixel block and the number of dots in that pixel block. The encoded data is decoded into dot pattern data corresponding to the number of dots in the pixel block using a decode table corresponding to each pixel block. The data of the encoding table is a threshold value table used at the time of encoding.

The processor 7 is an arithmetic processing unit as arithmetic processing means for executing decoding processing of halftone processing and rearrangement processing of binarized data. The CPU 7 a is an arithmetic processing circuit built in the processor 7. The internal RAM 7b is an internal memory built in the processor 7 and connected to the CPU 7a without passing through the bus 9. A high-speed memory such as a static RAM is used as the internal RAM 7b.

Each of the processors 1 to 7 sequentially reads and executes a program stored in advance in a recording medium such as a ROM (not shown) and loaded in the DRAM 8 to perform the above-described processing.

The dynamic RAM (DRAM) 8 is an external memory that is connected to the processors 1 to 7 via the bus 9 and stores various data and programs. The capacity of the DRAM 8 is
It is larger than the capacity of the internal RAMs 6b and 7b. The DRAM 8 includes an RGB data buffer 11,
Storage areas such as an intermediate data buffer 12 and an image buffer 13 are provided. The RGB data buffer 11 is a storage area for temporarily storing RGB data generated by the processing of the processors 3 to 5 and serving as input data for the processor 6. The intermediate data buffer 12 temporarily stores intermediate data that is output data of the processor 6 and is input data of the processor 7 (in the first embodiment, data after the halftone process encoding process, hereinafter referred to as encoded data). This is a storage area to be stored. Image buffer 1
Reference numeral 3 denotes a storage area for temporarily storing binarized data to be output from the processor 7.

The bus 9 includes a data bus and a program bus, and is a signal path that connects each of the processors 1 to 7 and the DRAM 8.

Next, the memory access circuit MA 1-1 operates independently of the processors 1 to 7 and acquires input data from the DRAM 8 via the bus 9 in parallel with the image processing of the processor 6. 6 is a circuit serving as a first memory access means to be supplied to 6. Also,
The memory access circuit MA2 operates independently of the processors 1 to 7 and acquires the data of the first table from the DRAM 8 via the bus 9 in parallel with the image processing of the processor 6. This is a circuit as a second memory access means for supplying to the memory. Also,
The memory access circuit MA 3-1 operates independently of the processors 1 to 7 and acquires the data of the second table from the DRAM 8 via the bus 9 in parallel with the image processing of the processor 6. This is a circuit as second memory access means to be supplied to the processor 6.

In addition, the memory access circuit MA1-2 operates independently of the processors 1 to 7 and acquires input data from the DRAM 8 via the bus 9 in parallel with the image processing of the processor 7. 1 is a circuit as a first memory access means for supplying to the memory. Also,
The memory access circuit MA 3-2 operates independently of the processors 1 to 7 and acquires the data of the third table from the DRAM 8 via the bus 9 in parallel with the image processing of the processor 7. This is a circuit as second memory access means to be supplied to the processor 7.

These memory access circuits MA1-1, MA1-2, like a series of image data,
This is used when a series of input data having a large size is read sequentially. The memory access circuit MA2 is used when the location of the table to be accessed is random.
In the first embodiment, the memory access circuit MA2 includes a lookup table (LUT).
Used for reading data. The memory access circuits MA3-1 and MA3-2 are
This is used when the location of the table to be accessed is continuous and data is read for each predetermined size. In the first embodiment, the memory access circuit MA3-1 is used for reading data of the encode table, and the memory access circuit MA3-2 is used for reading data of the decode table.

FIG. 2 is a block diagram illustrating a configuration related to data processing by the processors 6 and 7 in the image processing apparatus according to the first embodiment. As shown in FIG. 2, the internal RAM of the processor 6
In 6b, a pre-conversion table 21 used when converting the gradation resolution before color conversion is stored, and an encode table buffer 22 is provided. The encoding table buffer 22 is a storage area for temporarily storing encoding table data corresponding to one line of image data. The internal RAM 7b of the processor 7 is provided with a decode table buffer 23 and a work buffer 24. The decode table buffer 23 is a storage area for temporarily storing decode table data corresponding to one line of image data. The work buffer 24 is a storage area used in the rearrangement process.

Here, each memory access circuit MA1-1, MA1-2, MA2, MA3-1, MA3.
Details of -2.

FIG. 3 is a block diagram showing the configuration of the memory access circuits MA1-1 and MA1-2 and their peripherals. As shown in FIG. 3, each of the memory access circuits MA1-1 and 1-2 has a data queue 41 and a control circuit 42. The data queue 41 is the CPU 6a or CPU
7a is a storage circuit that holds data sequentially supplied from the control circuit 42 in order. The CPU 6a or the CPU 7a can access the data queue 41 without going through the bus 9, and reads the head data of the data queue 41. The top data of the data queue 41 is
When it is read by the CPU 6a or CPU 7a, it is erased from the data queue 41.
When the control circuit 42 is supplied with the head address and the number of data from the CPU 6a or the CPU 7a, the control circuit 42 starts the operation, specifies the addresses in order from the head address, and the data of the number of data specified from the DRAM 8 via the bus 9. Are sequentially read out and stored in the data queue 41.

FIG. 4 is a flowchart for explaining the operation of the processors 6 and 7 when the memory access circuits MA1-1 and MA1-2 are used. FIG. 4A shows memory access circuits MA1-1, MA.
It is a figure which shows the flow of a process when not using 1-2. FIG. 4B is a diagram showing a process flow when the memory access circuits MA1-1 and MA1-2 are used.

When the memory access circuits MA1-1 and MA1-2 are not used (FIG. 4A), when the head address of the input buffer is specified (step S1), data is first transferred directly from the address to the processor via the bus. It is read (step S2). And the process with respect to the data is performed (step S3). After the process, it is determined whether or not there is next data (step S4). If there is next data, the address of the next data is calculated,
Data is read directly from the address into the processor via the bus (step S2).
. In this way, processing is performed while a predetermined number of data is being read.

On the other hand, when the memory access circuits MA1-1 and MA1-2 are used (FIG. 4B), when the head address of the input buffer (RGB data buffer 11 or intermediate data buffer 12) is specified, the CPUs 6a and 7a The head address and the number of data for one line, for example, are supplied to the memory access circuits MA1-1 and MA1-2 (step S11). The memory access circuits MA1-1 and MA1-2 sequentially read the number of data from the head address and store the data in the data queue 41. The CPUs 6a and 7a read the head data from the data queue 41 (step S12) and execute processing for the data (step S13). The head data of the data queue 41 is erased when read by the read CPU 6a or CPU 7a. After the process is completed, the CPUs 6a and 7a determine whether or not the process for the predetermined number of data has been completed (step S14), and step S12 to step until the process for the predetermined number of data is completed. The process of S14 is repeatedly executed.

FIG. 5 is a diagram showing an example of a processing schedule of the CPUs 6a and 7a when the memory access circuits MA1-1 and 1-2 are used. As shown in FIG. 5, the memory access circuit MA1
-1, MA1-2 once activated, the data processing of CPU 6a, 7a (step S13
In parallel with this period, data is acquired from the DRAM 8 in parallel. For this reason, it is possible to reduce the frequency of stalling of the CPUs 6a and 7a due to data waiting, that is, latency.
In FIG. 5, the activation times of the memory access circuits MA1-1 and MA1-2 are expressed to be relatively long, but actually, they are very short compared to the data processing time.

FIG. 6 is a block diagram showing the configuration of the memory access circuit MA2 and its periphery. As shown in FIG. 6, the memory access circuit MA2 includes an address queue 51 and a data queue 52.
And a control circuit 53. The address queue 51 is connected to the CPU 6a, and the CPU 6
This is a memory circuit for sequentially holding addresses sequentially supplied from a. The head data of the address queue 51 is deleted from the address queue 51 when read by the control circuit 53. The data queue 52 is a storage circuit that is connected to the CPU 6 a and sequentially holds data sequentially supplied from the control circuit 53. The CPU 6 a can access the data queue 52 without using the bus 9, and reads the head data in the data queue 52. The head data of the data queue 52 is deleted from the data queue 52 when read by the CPU 6a. The control circuit 53 is a circuit that monitors the address queue 51, reads an address that is head data of the address queue 51, specifies the address, reads data from the DRAM 8 via the bus 9, and stores the data in the data queue 52. .

FIG. 7 is a flowchart for explaining the operation of the processor 6 when the memory access circuit MA2 is used. FIG. 7A shows a processing flow when the memory access circuit MA2 is not used. FIG. 7B is a diagram showing a processing flow when the memory access circuit MA2 is used.

Since the entire process can be separated into a pre-stage process and a post-stage process, and when the data read from the DRAM 8 is used in the post-stage process, the use of the memory access circuit MA2 is effective.

When the memory access circuit MA2 is not used (FIG. 7A), after the counter i is reset to 0 (step S21), the i-th pre-stage process is executed (step S22), and then the i-th data is stored. The data is read from the DRAM via the bus into the processor (step S23).
The i-th subsequent process is executed (step S24). Thereafter, the counter i is incremented by 1 (step S25), and it is determined whether or not n times of the pre-stage process and the post-stage process have been executed (step S26). Steps S22 to S26 are executed until n times of the pre-stage process and the post-stage process are completed.

On the other hand, when the memory access circuit MA2 is used (FIG. 7B), first, the CPU 6a executes the 0th pre-stage process (step S31). Next, the CPU 6a issues the address of the 0th data to the address queue 51 (step S32). Then, the counter i is reset to 0 (step S33). Next, the CPU 6a executes the (i + 1) th pre-stage process (step S34). Thereafter, the CPU 6a reads the i-th data from the data queue 52 (step S35), issues the address of the (i + 1) -th data to the address queue 51 (step S36), and executes the i-th subsequent process. (Step S
37). Then, the CPU 6a increments the counter i by 1 (step S38).
), It is determined whether n times of the pre-stage process and the post-stage process have been executed (step S39).
Steps S34 to S39 are executed until n times of the pre-stage process and the post-stage process are completed. When n times of the pre-stage process and the post-stage process are completed, the CPU 6a executes the (n-1
) Is read from the data queue 52 (step S40), and the (n-1) th subsequent process is executed (step S41).

FIG. 8 is a diagram illustrating an example of a processing schedule of the CPU 6a when the memory access circuit MA2 is used. Although FIG. 8 shows a case where data processing (previous processing and subsequent processing) is executed only four times, the number of times of data processing is usually very large. As shown in FIG. 8, the memory access circuit MA2 performs the pre-processing of the CPU 6a (step S34) and / or
Alternatively, data is acquired from the DRAM 8 in parallel with the period of the subsequent process (step S37). For this reason, it is possible to reduce the frequency of stalling of the CPU 6a due to data waiting, that is, latency.

FIG. 9 is a block diagram showing a peripheral configuration of the memory access circuits MA3-1 and MA3-2. As shown in FIG. 9, the memory access circuits MA3-1 and MA3-2 include a processor 6
The internal RAM 6b of the processor 7 or the internal RAM 7b of the processor 7 can be accessed, and when the head address and the data size are supplied, data corresponding to the data size is read from the DRAM 8 via the bus 9 and the bank flag 61 Is written in either the first bank 62 or the second bank 63 according to the value of. The value of the bank flag 61 is a 1-bit value, and is switched to 0 or 1 by the CPUs 6a and 7a every time certain processing is completed. The first bank 62 and the second bank 63 are respectively connected to the CPUs 6a and 7a.
This is a storage area having a capacity larger than the data size required by. The memory access circuits MA3-1 and MA3-2 cannot store the entire table in the internal RAMs 6b and 7b, but can store table data used for processing one line of image data in one bank 62 and 63. Used.

FIG. 10 is a flowchart for explaining the operation of the processors 6 and 7 when the memory access circuits MA3-1 and MA3-2 are used. FIG. 10A shows a memory access circuit MA3-1.
It is a figure which shows the flow of a process when not using MA3-2. FIG. 10B is a diagram showing a processing flow when the memory access circuits MA3-1 and MA3-2 are used.

When the memory access circuits MA3-1 and MA3-2 are not used (FIG. 10A), after the counter i is reset to 0 (step S51), the table data for the i-th line of the image data is processed by the processor. Thus, the data is read from the DRAM via the bus and written to the internal RAM (step S52). Thereafter, the process for the i-th line data is executed (step S53). Thereafter, the counter i is incremented by 1 (step S54).
), It is determined whether data processing for n lines has been executed (step S55). Until the data processing for n lines is completed, the processing from step S52 to step S55 is executed.

On the other hand, when the memory access circuits MA3-1 and MA3-2 are used (FIG. 10B),
First, the CPUs 6a and 7a supply the head addresses of the table data for the 0th line image data and the data length of the data to the memory access circuits MA3-1 and MA3-2 (step S61). The CPUs 6a and 7a reset the counter i to 0 (step S62).
), And waits until the table data for the 0th line is read to the internal RAMs 6b and 7b (step S63). Thereafter, the CPUs 6a and 7a determine the start address and the data length of the table data for the image data of the (i + 1) -th line as the memory access circuits MA3-1 and MA3-.
2 (step S64), the process for the i-th line is executed (step S).
65). Thereafter, the CPUs 6a and 7a increment the counter i by 1 (step S66), and determine whether data processing for n lines has been executed (step S67).
Until the data processing for n lines is completed, the processing from step S64 to step S67 is executed.

FIG. 11 shows the CPU 6a when the memory access circuits MA3-1 and MA3-2 are used.
It is a figure which shows an example of the processing schedule of 7a. Although FIG. 11 shows a case where data processing is executed only four times, the number of data processing is usually very large. In FIG. 11, the activation times of the memory access circuits MA3-1 and MA3-2 are expressed to be relatively long, but actually they are very short compared to the data processing time. As shown in FIG. 11, the memory access circuits MA3-1 and MA3-2 perform data processing (step S65) of the CPUs 6a and 7a.
In parallel with the period), table data is acquired from the DRAM 8 and written to the internal RAMs 6b and 7b. For this reason, it is possible to reduce the frequency of stalling of the CPUs 6a and 7a due to data waiting, that is, latency.

The architecture as described above can be realized by an architecture such as Tensilica's XtensaLX that can easily extend the interface of instructions and processors at the design stage. For example, in XtensaLX, an interface capable of controlling access to a queue connected to a processor can be added as a CPU command. The XtensaLX LX queue function can be used for the address queue and data queue described above.
As a result, the CPU can directly perform data transfer with a circuit outside the processor.

  Next, the operation of the above apparatus will be described.

First, image processing in the processor 6 will be described. The processor 6 processes the image data line by line. FIG. 12 is a flowchart for explaining image processing for image data for one line in the processor 6. FIG. 13 is a diagram for explaining the data flow of the image processing of FIG. First, first RGB data is acquired (step S101), and edge determination (step S102) and color conversion processing (step S10) are performed on the RGB data.
3) Encoding of smoothing (step S104) and halftone processing (
Step S105) is executed. Then, it is determined whether or not all data for one line has been processed (step S106). If there is RGB data that has not been processed for one line, the next RGB data is acquired (step S107), and the same processing is performed. Processing (Step S102 ~
S106) is executed. As shown in FIG. 13, edge information is detected in the edge determination, and the color space of the image data is converted from RGB to CMYK in the color conversion process. In the smoothing, the CMYK data is corrected based on the edge information. In the encoding process, the CMYK color data is encoded separately with reference to the encoding table.

Next, the operation of the processor 6 in the first embodiment will be described. FIG. 14 is a flowchart for explaining the operation of the processor 6 in the first embodiment. 15 is similar to FIG.
It is a figure explaining the data flow at the time of operation | movement of the processor 6 shown in FIG. Three memory access circuits MA1-1, MA2 and MA3-1 are used to supply data to the processor 6.
Therefore, the processor 6 operates according to the processing procedure of FIG. 4B for the memory access circuit MA1-1, and operates according to the processing procedure of FIG. 7B for the memory access circuit MA2.
The memory access circuit MA3-1 operates according to the processing procedure of FIG. In other words,
The process of steps S211 to S225 in FIG. 14 corresponds to the process of step S65 in FIG. Further, the processing in steps S215 to S217 in FIG. 14 is changed to step S in FIG.
The processing in steps S221 to S224 in FIG. 14 corresponds to the processing in step S37 in FIG. 7B. Further, the processing of steps S216 to S224 in FIG.
This corresponds to the process of step S13 in (B).

The CPU 6a of the processor 6 supplies the leading address and data length to the memory access circuit MA3-1 to copy the 0th line encoding table data to the internal RAM 6b (step S201). Then, after resetting the counter i to 0 (step S202), the CPU 6a stores the table data for the 0th line in the internal RAM 6b.
(Step S203). Thereafter, the CPU 6a performs the (i + 1) th
) After supplying the head address and data length of the table data for line image data to the memory access circuit MA3-1 (step S204), the processes of steps S211 to S225 are executed as the process for the i-th line.

On the other hand, independent of the processor 6, the memory access circuit MA3-1 reads the designated data in the encode table 15 from the DRAM 8 and writes it to the first bank 62 or the second bank 63 of the internal RAM 6b. The table data for one line is stored in the first bank 62 and the second bank 63 alternately for each line. This memory access circuit M
The process of A3-1 is the halftone process encoding process for the (i + 1) th line (
Preferably, it is completed before step S223) is started.

After the process of step S204, the CPU 6a identifies the start address of the line to be processed in the RGB data buffer 11, and supplies the start address and the number of data for one line to the memory access circuit MA1-1 (step S211). . The CPU 6a uses the counter j
Is reset to 0 (step S212). Thereafter, the CPU 6a determines that the value of the counter j is n
It is determined whether it is larger (step S213). When the value of the counter j is n or less, the CPU 6a executes the processes of steps S214 to S225.

The processing of steps S214 to S224 is performed until the value of the counter j changes from 0 to n (n +
1) It is executed repeatedly. However, in the first process (j = 0), processes corresponding to steps S31 and S32 in FIG. 7B are executed in steps S215 to S218, and the processes in steps S220 to 224 are skipped (step S219). . In the (n + 1) th process (j = n), processes corresponding to steps S40 and S41 in FIG. 7B are executed in steps S220 to S224, and the processes in steps S215 to S218 are skipped (
Step S214).

First, as shown in FIG. 15, the CPU 6a reads the 0th (ie, the first) RGB data in one line from the data queue 41 of the memory access circuit MA1-1 (step S215). Edge determination is performed on the data (step S21).
6). Thereafter, the CPU 6a calculates the address of the storage location of the LUT data necessary for color conversion of the 0th RGB data (step S217), and uses the address as the memory access circuit MA.
2 is written into the address queue 51 (step S218). Thereafter, the CPU 6a increments the value of the counter j to 1 (j = 1) (step S225).

Next, as shown in FIG. 15, the CPU 6a reads the first (that is, second) RGB data in one line from the data queue 41 (step S215), and performs edge determination on the RGB data (step S215). Step S216). After that, the CPU 6a uses the second RGB
The storage location address of the LUT data necessary for data color conversion is calculated (step S217).
The address is written into the address queue 51 of the memory access circuit MA2 (step S218). Thereafter, as shown in FIG. 15, the CPU 6a reads the 0th (that is, the first in one line) LUT data from the data queue 52 of the memory access circuit MA2, and based on the LUT data, the 0th RGB The data is color-converted into 0th CYMK data (step S221). Note that the CPU 6a performs pre-conversion with reference to the pre-conversion table 21 before performing color conversion processing, and converts the gradation of RGB data from 256 gradations to 32 gradations. Further, the CPU 6a performs smoothing on the CYMK data after color conversion based on the edge information obtained by the edge determination (step S216) (step S22).
2). Further, as shown in FIG. 15, the CPU 6a reads the encoding table data from the internal RAM 6b, encodes the 0th CYMK data based on the encoding table data (step S223), and uses the encoded data as intermediate data. Store in the intermediate data buffer 12 (step S224).

Thereafter, the CPU 6a increments the value of the counter j to 2 (j = 2) (step S225). In the same manner, the processes in steps S215 to S218 and S220 to S224 described above are repeated until the value of the counter j reaches n.

When the value of the counter j reaches n, the CPU 6a reads the (n−1) th (that is, the last in one line) LUT data from the data queue 52 of the memory access circuit MA2, and based on the LUT data. The (n-1) th RGB data is converted into the (n-1) th C data.
Color conversion to YMK data is performed (step S221). In addition, the CPU 6a performs CY after color conversion.
Smoothing is performed on the MK data based on the edge information obtained by the edge determination (step S216) (step S222). Further, the CPU 6a has an internal RAM 6b.
Read the encoding table data from, and based on the encoding table data,
The (n-1) th CYMK data is encoded (step S223), and the encoded data is stored in the intermediate data buffer 12 (step S224).

Thereafter, the CPU 6a increments the value of the counter j to (n + 1) (j = n + 1
) (Step S225). Therefore, the CPU 6a, in step S213,
It is determined that the value of the counter j is larger than n, and processing for one line (steps S204, S21)
1 to S225) is completed.

In this way, the memory access circuits MA1-1, MA2, and MA3-1 store data (RGB data, LUT table data, and encode table data) necessary for processing.
The DRAM 8 via the bus 9 independently of the processor 6 and in parallel with the processing of the processor 6
Is provided to the processor 6 without going through the bus 9.

Next, image processing in the processor 7 will be described. The processor 7 processes the image data line by line. However, the unit of the image data is a block (that is, one encoded data). FIG. 16 is a flowchart for explaining image processing for image data for one line in the processor 7. FIG. 17 is a diagram showing each area of the image buffer 13. FIG. 18 is a diagram for explaining the data flow of the image processing of FIG. As shown in FIG. 17, the image buffer 13 has an effective nozzle area that ejects ink from the nozzles of the print head corresponding to the image. Depending on the position of the print head, a NULL area exists. The NULL region is a region corresponding to a region where there is no printing paper or a blank region, and is a nozzle region which does not eject ink in the ink nozzle array of the print head. The image buffer 13 stores binary data necessary for one scan of the print head. That is, 1
Binarized data of the product of the number of nozzles used for one scanning and the number of dot positions in the scanning direction is stored in the image buffer 13. When ink is ejected by interlace processing, binarized data necessary for one scan is selected and stored in the image buffer 13. As interlace processing, for example, there is processing disclosed in Japanese Patent No. 3371302. Note that the presence / absence and location information of the NULL area is supplied from the processor 1.

As shown in FIG. 16, first, it is determined whether there is an upper end NULL area to be processed (step S301). If there is an upper end NULL area to be processed, NULL data for one line (that is, ink is not ejected). Data) is written into the 8-line buffer (step S302). When writing to the 8-line buffer is completed, it is determined whether or not data for 8 lines is stored in the 8-line buffer (step S303), and data for 8 lines is stored in the 8-line buffer. The data stored in the 8-line buffer is stored in the image buffer 13 after the rows and columns are exchanged and rotated (step S304). FIG. 19 is a diagram illustrating rearrangement of binarized data. The data supplied to the print head needs to be arranged along the scanning direction of the print head. That is, data necessary for the first ink ejection is arranged at the top of the image buffer 13,
Data necessary for the next ink ejection after the print head is moved needs to be arranged next. On the other hand, normal image data is arranged line by line from the left to the right of the image in the image file. For this reason, the image data is rotated.

Then, the processes in steps S302 to S304 are repeatedly executed until there is no upper end NULL area to be processed.

If there is no upper NULL region to be processed, it is next determined whether or not there is an effective nozzle region to be processed (step S305). When there is an effective nozzle area to be processed, intermediate data for one line is decoded to generate binarized data, and binarized data for one line is 8
It is stored in the line buffer (step S306). When writing to the 8-line buffer is completed, it is determined whether 8-line data is stored in the 8-line buffer (
In step S307), when data for 8 lines is stored in the 8-line buffer, the data stored in the 8-line buffer is stored in the image buffer 13 after the rows and columns are exchanged and rotated. (Step S308). Then, the processes in steps S306 to S308 are repeatedly executed until there is no effective nozzle area to be processed.

When there is no more effective nozzle area to be processed, it is next determined whether or not there is a remaining area to be processed (that is, a lower end NULL area) (step S309). Lower end NUL to be processed
When there is an L area, NULL data for one line is written into the 8-line buffer (step S310). When writing to the 8-line buffer is complete, 8
It is determined whether or not data for a line is stored (step S311), and if data for 8 lines is stored in the 8-line buffer, the data stored in the 8-line buffer is After the columns are exchanged and rotated, they are stored in the image buffer 13 (
Step S312). Then, until there is no lower end NULL area to be processed, step S
The processes of 310 to S312 are repeatedly executed.

In this way, binary data corresponding to the height of the image buffer 13 is generated. The data is erased after being used in one scan of the print head, and necessary binary data is generated in the next scan.

FIG. 20 is a flowchart for explaining the operation of the processor 7 in the first embodiment. FIG. 21 is a flowchart illustrating details of the process in step S411 of FIG.
FIG. 22 is a diagram for explaining the data flow when the processor 7 shown in FIGS. 20 and 21 is operating. For supplying data to the processor 7, two memory access circuits MA1-2, MA
3-2 is used. Therefore, the processor 7 operates according to the processing procedure of FIG. 4B for the memory access circuit MA1-2, and for the memory access circuit MA3-2, FIG.
It operates according to the processing procedure (B). That is, the processing of steps S410 and S411 in FIG.
This corresponds to the process of step S65 in FIG. Also, steps S423 to S in FIG.
The process of 425 corresponds to the process of step S13 in FIG.

The processing for the top NULL region (steps S401 to S404)
Since this is the same as the processing for the LL area (steps S301 to S304), the description thereof is omitted. In addition, the processing for the bottom NULL area (steps S414 to S417) is also performed.
Since it is the same as the process (steps S309 to S312) for the lower end NULL area, the description thereof is omitted.

If there is no upper end NULL area to be processed, the CPU 7a first determines whether there is an effective nozzle area to be processed (step S405). If there is an effective nozzle area to be processed,
The CPU 7a performs the memory access circuit M only for the first line (step S406).
A start address and data length of the decode table data for the first line are supplied to A3-2, and the decode table data for the first line is read from the DRAM 8 and the internal RAM 7b.
(Step S407), and waits until the decode table data is written to the internal RAM 7b (step S408).

When the decode table data is written to the internal RAM 7b, the CPU 7a supplies the start address and the data length of the decode table data for the next line to the memory access circuit MA3-2 (step S409). Further, the CPU 7a supplies the head address of the intermediate data buffer 12 and the number of data for one line to the memory access circuit MA1-2 (step S410).

When the address and data length are supplied, the memory access circuit MA3-2 starts its operation, reads the decode table data from the DRAM 8, and writes it into the internal RAM 7b. Also, when the memory access circuit MA1-2 is supplied with the address and the number of data, the memory access circuit MA1-2 starts to operate and reads encoded data (that is, input data) from the DRAM 8 and stores it in the data queue 41.

Thereafter, the CPU 7a sequentially reads the encoded data from the data queue 41 of the memory access circuit MA1-2, performs a decoding process for one line based on the decoding table data stored in the internal RAM 7b, and is generated by the decoding process. The binarized data for one line is stored in the 8-line buffer 17 (step S411).

As shown in FIG. 22, the encoded data is read from the data queue 41 of the memory access circuit MA1-2 to the input register 71 in the CPU 7a (step S421). Next, the CPU 7a obtains one element data (one encoded data) from the input register 71 and decodes it based on the decode table data stored in the decode table buffer 23 of the internal RAM 7b as shown in FIG. Then, the CPU 7a generates binarized data for one block (step S423), and from the binarized data for one block,
Only the binarized data of the processing target line is extracted (step S424) and stored in the output register 72 (step S425). Data in the input register 71 is sequentially selected and processed (step S431), and when the output register 72 is filled with data (step S426).
The CPU 7a stores the binarized data in the 8-line buffer 17 (step S427).
. When all the element data in the input register 71 is processed (step S428), subsequent data is read from the data queue 41 to the input register 71 (step S429).
When the processing is completed for all elements in one line (step S430), step S430
The process of 410 is completed. The input register 71 and the output register 72 are connected to the CPU 7.
It is a 128-bit register provided in a.

When the writing of binary data for one line to the 8-line buffer 17 is completed in this way, the CPU 7a determines whether or not data for 8 lines is stored in the 8-line buffer 17 (step S412). ). When data for 8 lines is stored in the 8-line buffer 17, the CPU 7a exchanges the data stored in the 8-line buffer 17 for rows and columns using the work buffer 24 in the internal RAM 7b. And stored in the image buffer 13 (step S413). FIG. 23 is a diagram for explaining the binarized data rearrangement operation by the processor 7. As shown in FIG. 23, the 8-line buffer 17
The data read from is stored in the work buffer 24 as it is. The data stored in the work buffer 24 is read at regular intervals and stored in the image buffer 13. In order to reduce the number of direct accesses to the DRAM 8, the work buffer 2
Continuous data corresponding to the number of bits of four columns and rows is read from and written to continuous storage areas in the DRAM 8 in one access. For example, when 1-bit binarized data is used and data is supplied to the print head every 8 nozzles, rearrangement is performed in units of 8 bits.
The number of bits in the columns and rows of the work buffer 24 is the same as the unit (for example, 128 bits) at the time of data access to the DRAM 8.

Then, the processes in steps S408 to S412 are repeatedly executed until there is no effective nozzle area to be processed.

In this way, the memory access circuits MA1-2 and MA3-2 send data (encoded data and decode table data) necessary for processing to the bus 9 independently of the processor 7 and in parallel with the processing of the processor 7. And is provided to the processor 7 without going through the bus 9.

Embodiment 2. FIG.
The image processing apparatus according to Embodiment 2 of the present invention uses a dither method as a halftone processing method. In the first embodiment, halftone processing is executed by the two processors 6 and 7. In the second embodiment, one processor 6 executes dither halftone processing. FIG. 24 is a block diagram illustrating a configuration related to data processing by the processors 6 and 7 in the image processing apparatus according to the second embodiment. In the second embodiment, dither matrix data 81 and dither matrix buffer 82 are provided instead of the encode table 15 and the encode table buffer 22. The dither matrix data 81 is stored in the DRAM 8, and the memory access circuit MA3-1 reads the dither matrix data 81 and stores it in the dither matrix buffer 82 in the internal RAM 6b. In the second embodiment, the decode table 16,
Memory access circuit MA3-2 and decode table buffer 23 do not exist. In the second embodiment, the processor 6 executes dither halftone processing, and the processor 7
Does not perform halftone processing. Other configurations in FIG. 24 are the same as those in the first embodiment (FIG. 2), and thus description thereof is omitted.

Next, the operation of the above apparatus will be described. First, the operation of the processor 6 in the second embodiment will be described. FIG. 25 is a flowchart for explaining the operation of the processor 6 in the second embodiment. FIG. 26 is a diagram for explaining the data flow during operation of the processor 6 shown in FIG. As shown in FIG. 25, the CPU 6 of the processor 6 in the second embodiment.
a requests dither matrix data from the memory access circuit MA3-1 instead of the encoding table data for each line (steps S201a and S204a). The memory access circuit MA3-1 reads the designated dither matrix data 81 from the DRAM 8 and stores it in the internal RAM 6b. Then, the CPU 6a, as shown in FIG.
The dither matrix data is read from the M6b dither matrix buffer 82, halftone processing is executed (step S223a), and the binarized data is stored in the intermediate data buffer 12 as intermediate data (step S224).

Since other operations of the processor 6 in the second embodiment are the same as those in the first embodiment, description thereof is omitted.

Next, the operation of the processor 7 in the second embodiment will be described. FIG. 27 is a flowchart for explaining the operation of the processor 7 in the second embodiment. FIG. 28 is similar to FIG.
It is a flowchart explaining the detail of the process of step S502. FIG. 29 is a diagram for explaining the data flow when the processor 7 shown in FIGS. 27 and 28 is operating. As shown in FIG. 27, the processing (steps S401 to S404) regarding the upper end NULL region and the lower end N
Since the process related to the UL area (steps S414 to S417) is the same as that in the first embodiment, the description thereof will be omitted, and the process related to the effective nozzle area will be described here.

In the second embodiment, halftone processing is executed by the processor 6 and the binarized data is stored in the intermediate data buffer 12 as intermediate data. Therefore, the processor 7
Is already binarized. Therefore, the processor 7 performs data extraction and rearrangement to generate binarized data for the image buffer 17.

The CPU 7a of the processor 7 determines whether or not there is an effective nozzle area to be processed (step S501). When there is an effective nozzle area to be processed, the CPU 7a reads the intermediate data from the data buffer 41 of the memory access circuit MA1-2 and stores the binarized data necessary for the one-line binarized data in the 8-line buffer 17. (Step S502). In the dither method, since binarization is performed in units of blocks, intermediate data is arranged in units of blocks. For this reason, the binarized data necessary for one line is extracted from the binarized data of each block.

At that time, as shown in FIG. 29, the intermediate data is loaded into the input register 71 (step S511), and the CPU 7a extracts data necessary for one-line binarized data from the intermediate data loaded into the input register 71. (Step S512) and stored in the output register 72 (step S513). When all the data loaded in the input register 71 is processed, subsequent data is read out to the input register 71. When the output register 72 is filled with data, the data in the output register 72 is stored in the 8-line buffer 17 (step S51).
4) After that, it is erased. The processes in steps S511 to S514 are repeatedly executed until one line of binarized data is generated (step S515).

When the writing to the 8-line buffer 17 is completed, the CPU 7a executes the 8-line buffer 1
7 determines whether data for 8 lines is stored (step S503). If data for 8 lines is stored in the 8-line buffer 17, the 8-line buffer 17
Is stored in the image buffer 13 after exchanging the rows and columns (step S504).

Embodiment 3 FIG.
The image processing apparatus according to Embodiment 3 of the present invention uses an error diffusion method as a halftone processing method. In the first embodiment, halftone processing is executed by two processors, the processor 6 and the processor 7, but in the third embodiment, the processor 6
Thus, error diffusion halftone processing is executed. The error diffusion method for halftone processing in the third embodiment is disclosed in, for example, Japanese Patent Laid-Open No. 2002-199220, and can sequentially read error data and execute halftone processing for one line. Is.

FIG. 30 is a block diagram illustrating a configuration related to data processing by the processors 6 and 7 in the image processing apparatus according to the third embodiment. In the third embodiment, the encoding table 15, the memory access circuit MA3-1, and the encoding table buffer 22 of the first embodiment.
Instead of these, an error buffer 91 and memory access circuits MA1-3 are provided. DR
The AM 8 is provided with an error buffer 91 for storing error data at the time of halftone processing by the CPU 6a. Memory access circuits MA1-3 are memory access circuits MA1-1, MA1-1.
Similar to MA1-2, the error data is sequentially read from the error buffer 91 of the DRAM 8 and stored in the data queue 41.

Other configurations in FIG. 30 are the same as those in the first embodiment or the second embodiment, and thus description thereof is omitted. Since the configuration and operation of the processor 7 and the memory access circuit MA1-2 in the third embodiment are the same as those in the second embodiment, description thereof is omitted.

Next, the operation of the above apparatus will be described. FIG. 31 is a flowchart for explaining the operation of the processor 6 in the third embodiment. In the third embodiment, the memory access circuit MA
1-1 and MA1-3 provide the processor 6 with RGB data and error data. At the beginning of the processing of each line, the CPU 6a designates the start address of the error buffer and the number of data and activates the memory access circuit MA1-3 (step S601), and designates the start address and the number of data of the RGB data buffer 11. Memory access circuit MA1-1
Is activated (step S211). At the time of halftone processing, the CPU 6a performs error diffusion processing while referring to error data stored in the internal RAM 6b, and stores the generated error data in the error buffer 91 (step S223b). And CPU
6a stores the binarized data in the intermediate data buffer 12 as intermediate data (step S224).

Since other operations of the processor 6 in the third embodiment are the same as those in the first or second embodiment, the description thereof is omitted.

Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is. For example, in the halftone process of each of the above embodiments, the binarized data is not 4
You may make it produce | generate value data. The quaternarized data is data representing the presence / absence of dots and the dot size in 2 bits. Accordingly, when data is supplied to the print head every 8 elements, the data is supplied in units of 16 bits. The sizes of the 8-line buffer 17 and the image buffer 13 may also be changed according to the size of the data unit supplied to the print head. The counters in the above embodiments use registers in the CPUs 6a and 7a or storage areas in the internal RAMs 6b and 7b.

  The present invention is applicable to, for example, a printer having a plurality of processors.

1 is a configuration diagram of an image processing apparatus according to Embodiment 1 of the present invention. 2 is a configuration diagram around processors 6 and 7 in Embodiment 1. FIG. 2 is a configuration diagram of a memory access circuit MA1 and its periphery. FIG. It is a figure explaining processor operation at the time of memory access circuit MA1 use. It is a figure which shows the example of a process schedule at the time of memory access circuit MA1 use. 2 is a configuration diagram of a memory access circuit MA2 and its periphery. FIG. It is a figure explaining processor operation at the time of memory access circuit MA2 use. It is a figure which shows the example of a process schedule at the time of memory access circuit MA2 use. 4 is a block diagram showing a configuration around a memory access circuit MA3. FIG. It is a figure explaining processor operation at the time of memory access circuit MA3 use. It is a figure which shows the example of a process schedule at the time of memory access circuit MA3 use. 6 is a flowchart for explaining image processing in a processor 6; It is a figure explaining the data flow of the image processing of FIG. 6 is a diagram for explaining the operation of the processor 6 in Embodiment 1. FIG. It is a figure explaining the data flow at the time of the processor operation | movement shown in FIG. 6 is a flowchart for explaining image processing in a processor 7; It is a figure which shows each area | region of an image buffer. It is a figure explaining the data flow of the image processing of FIG. It is a figure explaining rearrangement of binarized data. 6 is a diagram for explaining the operation of the processor 7 in Embodiment 1. FIG. It is a figure explaining the detail of the process of step S411 of FIG. It is a figure explaining the data flow at the time of processor operation shown in FIG. It is a figure explaining the rearrangement operation | movement of the binarized data by the processor. FIG. 6 is a configuration diagram around processors 6 and 7 in a second embodiment. FIG. 10 is a diagram for explaining the operation of the processor 6 in the second embodiment. It is a figure explaining the data flow at the time of the processor operation | movement shown in FIG. FIG. 10 is a diagram for explaining the operation of the processor 7 in the second embodiment. It is a figure explaining the detail of the process of step S502 of FIG. It is a figure explaining the data flow at the time of the processor operation | movement shown in FIG. FIG. 10 is a configuration diagram around processors 6 and 7 in a third embodiment. FIG. 10 is a diagram for explaining the operation of a processor 6 in the third embodiment.

Explanation of symbols

6, 7 processor (arithmetic processing means), 6b, 7b internal RAM (internal memory), 8
DRAM (memory), 9 buses, 14 LUT (table), 15 encoding table (table), 16 decoding table (table), 41 data queue, 42 control circuit, 51 address queue, 52 data queue, 53 control circuit, MA1- 1, MA
1-2 Memory access circuit (first memory access means), MA2, MA3-1, MA
3-2, MA1-3 Memory access circuit (second memory access means).

Claims (5)

In an image processing apparatus comprising a plurality of arithmetic processing means, a memory, and a bus connecting each of the plurality of arithmetic processing means and the memory,
Any one of the plurality of arithmetic processing means, wherein the arithmetic processing means sequentially performs image processing on a series of image data using a table;
In parallel with the image processing of the arithmetic processing means, the image data is acquired from the memory via the bus and supplied to the arithmetic processing means without going through the bus. 1 memory access means;
A second operation that operates independently of the arithmetic processing means and obtains the table from the memory via the bus and supplies the table to the arithmetic processing means via the bus in parallel with the image processing of the arithmetic processing means. comprising of a memory access means, and
The arithmetic processing means has an internal memory having at least two banks,
When the second memory access means obtains the head address from the arithmetic processing means, the second memory access means obtains data of a predetermined length from the head address from the memory via the bus, and one bank and the other of the internal memory An image processing apparatus characterized by storing alternately in any of the banks . The second memory access means obtains a table used for halftone processing from the memory via the bus, and supplies the table to the arithmetic processing means without going through the bus. The image processing apparatus according to claim 1, wherein halftone processing is performed on the image data using a table. The first memory access means obtains a data queue that can be read by the arithmetic processing means without going through the bus and a head address from the arithmetic processing means, and sequentially transfers image data from the memory from the head address. The image processing apparatus according to claim 1, further comprising a control circuit that acquires the data via the bus and stores the data in the data queue. The second memory access means stores in the address queue that the arithmetic processing means can write without going through the bus, the data queue that the arithmetic processing means can read without going through the bus, and the address queue. 4. A control circuit for acquiring a stored address, acquiring data of the address in the table from the memory via the bus, and storing the data in the data queue. The image processing device according to claim 1. 5. A printing system comprising the image processing apparatus according to claim 1 and performing printing processing based on data obtained by performing image processing by the image processing apparatus. apparatus.

Images