JP4869326B2 - Communications system - Google Patents

Description

  The present invention relates to a communication system in which a plurality of signals are simultaneously transmitted through the same transmission path by a code multiplexing method.

  As a method of multiplexing and transmitting a plurality of signals on the same transmission path, a method by code division multiplexing (CDM) is known. The code division multiplexing method is an application of a spread spectrum (SS) method.

  For example, Japanese Patent Laying-Open No. 2000-183849 (Patent Document 1) discloses a technique for transmitting a large amount of information data without deteriorating the error rate of transmission data using the CDM method. In this technique, information data is distributed to a plurality of channels, and the signals of each channel are spread-modulated with different spreading code sequences, multiplexed and transmitted. In this case, orthogonal codes are used for the spreading code sequence, and the spreading code output of each channel has the same spreading code speed and the code phase is synchronized. As a result, the modulation rate of the data modulation can be reduced, so that it is possible to prevent the error rate of the transmission data from deteriorating. Furthermore, in this technique, the receiving station determines the optimum channel multiplexing number, data modulation and spreading modulation multi-level number used for transmission by the other station based on the signal-to-interference noise power ratio of the received packet. Determination is made, and designation information for designating these is transmitted to the partner station. Then, the partner station sets the number of multiplexed channels used for transmission of the local station, the modulation level of data modulation and spread modulation for each packet based on the transmitted designation information.

  The CDM method can also be applied to an optical communication system. For example, in the technique disclosed in Japanese Patent Application Laid-Open No. 2004-304444 (Patent Document 2), on the transmission side, transmission information of a plurality of channels is individually encoded by an optical encoder and then multiplexed by a multiplexing unit, and then an optical transmission line. Send to. On the receiving side, the optical code division multiplexed transmission signal transmitted on the optical transmission line is separated by the demultiplexing means and then decoded by the optical decoder. Further, in this technique, the transmitting side periodically inserts and transmits a pilot signal having an amplitude larger than the maximum amplitude in the code division multiplex transmission signal, and the receiving side sets the maximum amplitude level in a predetermined period to the pilot signal. Detect as. On the receiving side, synchronization of the transmission signal can be acquired by the pilot signal, and equalization is ensured by correcting the attenuation of the optical code division multiplexing transmission signal by the optical transmission path from the detected amplitude level of the pilot signal. Can do.

  Japanese Patent Laying-Open No. 2005-109580 (Patent Document 3) discloses an optical CDM system using code shift keying (CSK). A transmitter used for the CSK system includes a modulator, a mark optical encoder, a space optical encoder, and a multiplexer. The modulator distributes the optical pulse train generated from the light source at the bit period into a mark corresponding to “1” of the digital data and a space corresponding to “0” of the digital data. The mark optical encoder encodes the mark optical pulse train distributed by the modulator. The space optical encoder encodes the space optical pulse train distributed by the modulator. The multiplexer multiplexes the pulse train encoded by the mark optical encoder and the pulse train encoded by the space optical encoder.

  Therefore, a CSK transmitter requires more optical encoders than a transmitter using conventional OOK (On-Off Keying) modulation, and the apparatus becomes complicated. However, in the CSK system, a “0” signal that has not been encoded in the conventional optical CDM is encoded by the newly added space optical encoder, so that side lobes can be suppressed and data measurement can be performed. The judgment range can be increased.

  In addition to the above OOK and CSK, PPM (Pulse Position Modulation), PAM (Pulse Amplitude Modulation), PWM (Pulse Width Modulation), and the like are known as data modulation methods in optical communication. For example, Inoue et al. Have reported a PPM-PAM multiplex modulation system combining PPM and PAM ("Detection of PPM-PAM multiplex modulation pulse using linear filter", IEICE Transactions A, 1996). March, Vol. J79-A, No. 3, pp. 776-784 (Non-Patent Document 1)). PPM-PAM modulation is a method in which the timing and amplitude of a pulse are changed independently, and has characteristics such that analog and digital information can be mixed and transmitted.

  Further, signal transmission by light is suitably used for signal transmission with a large amount of information such as a Full HD (High Definition) video signal. For example, the technique disclosed in Japanese Patent Application Laid-Open No. 2006-191160 (Patent Document 4) relates to an optical transmission system that performs optical transmission between a source device side block and a monitor device side block. From the source device side block to the monitor device side block, an electrical signal including a digital video signal and a plurality of source device side control signals is multiplexed into one stream with a clock synchronized with the pixel clock of the digital video signal. Optical transmission. In addition, from the monitor device side block to the source device side block, a plurality of monitor device side control signals, which are electric signals supplied from the monitor device side block, are multiplexed into one stream, and an asynchronous serial It is converted into a signal and transmitted optically.

On the other hand, as a method in which a plurality of users share one optical transmission line and perform multiple access, for example, optical CDMA (Code Division Multiple Access) disclosed in JP-A-2002-290375 (Patent Document 5) is known. ing. In the optical CDMA communication system, since the optical signal of the target user is identified from the optical reception signal by the correlator, multiple access interference occurs due to cross-correlation between spreading code sequences assigned to other users. There is a problem. The technique disclosed in Japanese Patent Application Laid-Open No. 2002-290375 (Patent Document 5) relates to a multi-level modulation method capable of transmitting multiple symbols per spreading code sequence time. Furthermore, this technique relates to a new modulation scheme in which an error correction code is embedded in a multi-valued symbol in order to improve resistance against multiple access interference.
JP 2000-183849 A JP 2004-304444 A JP 2005-109580 A JP 2006-191160 A JP 2002-290375 A Tadaaki Inoue and two others, "Detection of PPM-PAM multiplexed modulation pulses using linear filters", IEICE Transactions A, March 1996, Vol. J79-A, No. 3, pp. 776- 784

  Using the technique described in the above-mentioned Japanese Patent Application Laid-Open No. 2000-183849 (Patent Document 1), the same user can efficiently transmit a plurality of signals through a transmission path of the same band by code division multiplexing. It is possible. In particular, if the code phases of the spreading code sequences assigned to each signal are synchronized, in principle, no interference occurs between these signals.

  However, when the number of simultaneously output signals becomes several tens or more, in order to transmit these signals without error, highly accurate signal processing is required for the transmitter and the receiver. In particular, the transmitter needs to synchronize the code phase of the spread code sequence with high accuracy between the signals. In addition, the receiver needs to establish synchronization with high accuracy based on the received signal.

  In addition, when a plurality of users are connected to the same transmission path and perform signal transmission at the same time, it is necessary to suppress multiple access interference. However, even if an error correction code is used as described in Japanese Patent Application Laid-Open No. 2002-290375 (Patent Document 5), a data transmission error occurs if the code error rate increases.

  Therefore, a first object of the present invention is to provide a communication system that can code-multiplex and multiplex a large number of signals without error. A second object of the present invention is to provide a communication system capable of code-division multiplexing and transmitting without error between a plurality of users.

  In summary, the present invention is a communication system including a transmitter and a receiver. Here, the transmitter includes a signal input unit, a comb pulse generation unit, a spread modulation unit, and a multiplexed signal generation unit. The signal input unit receives a plurality of bit signals respectively corresponding to a plurality of spread sequences having the same sequence length and having the same bit period. The comb pulse generator outputs comb pulses having the number of pulses equal to the sequence length for each bit period based on the clock signal. For each of the plurality of bit signals received by the signal input unit, the spread modulation unit outputs a corresponding spread sequence in synchronization with the comb pulse according to the bit data of each bit signal. The multiplexed signal generation unit generates and transmits a multiplexed signal by adding the output of the spread modulation unit and the output of the comb pulse generation unit.

  The receiver includes a multiplexed signal receiving unit, a clock generation unit, a despreading unit, and a first signal determination unit. The multiplexed signal receiving unit receives the multiplexed signal. The clock regeneration unit regenerates the comb pulse by determining whether or not the reception signal output from the multiplexed signal reception unit exceeds a preset first threshold value. The despreading unit calculates and outputs a correlation value between the received signal and each of the plurality of spread sequences in accordance with the timing of the reproduced comb pulse. The first signal determination unit reproduces the plurality of bit signals by determining whether the output of the despreading unit exceeds a preset second threshold value.

  In another aspect, the present invention is a communication system including n (n is an integer of 2 or more) transmitters and receivers. Here, each of the n transmitters is assigned a time slot in a circulating manner. Each of the n transmitters includes a signal input unit, a comb pulse generation unit, a spread modulation unit, and a multiplexed signal generation unit. The signal input unit receives a plurality of bit signals having the same bit period. At this time, each of the plurality of bit signals has the same sequence length and individually corresponds to any one of a plurality of spreading sequences used in common by n transmitters. The comb pulse generator outputs comb pulses having the number of pulses equal to the sequence length for each bit period based on the clock signal. For each of the plurality of bit signals received by the signal input unit, the spread modulation unit outputs a corresponding spread sequence in synchronization with the comb pulse according to the bit data of each bit signal. The multiplexed signal generation unit generates a multiplexed signal for each bit period by adding the output of the spread modulation unit and the output of the comb pulse generation unit, and the generated multiplexed signal is assigned between the assigned time slots. Send.

  The receiver includes a multiplexed signal receiving unit, a clock recovery unit, a despreading unit, and a first signal determination unit. The multiplexed signal receiving unit receives the multiplexed signal transmitted from each of the n transmitters. The clock recovery unit determines whether or not the received signal output from the multiplexed signal receiving unit exceeds a preset first threshold value, thereby generating comb pulses generated by each of the n transmitters. Reproduce. The despreading unit calculates and outputs a correlation value between the received signal and each of the plurality of spreading coefficients in accordance with the timing of the comb pulse reproduced by the clock reproduction unit. The first signal determination unit reproduces a plurality of bit signals for each of the n transmitters by determining whether the output of the despreading unit exceeds a preset second threshold.

  In yet another aspect, the present invention is a communication system including n (n is an integer of 2 or more) transmitters and receivers. Here, each of the n transmitters is assigned a time slot in a circulating manner. Each of the n transmitters includes a signal input unit, a comb pulse generation unit, a spread modulation unit, and a multiplexed signal generation unit. The signal input unit receives a plurality of bit signals having the same bit period. At this time, each of the plurality of bit signals has the same sequence length and individually corresponds to any one of a plurality of spreading sequences used in common by n transmitters. The comb-shaped pulse generation unit outputs a comb-shaped pulse having a number of pulses equal to the sequence length based on the clock signal and corresponding to each assigned time slot, one bit period. For each of the plurality of bit signals received by the signal input unit, the spread modulation unit outputs a corresponding spread sequence in synchronization with the comb pulse according to the bit data of each bit signal. The multiplexed signal generation unit adds the output of the spread modulation unit and the output of the comb pulse generation unit to generate a multiplexed signal for each bit period, and transmits the generated multiplexed signal in a corresponding time slot. .

  The receiver includes a multiplexed signal receiving unit, a clock recovery unit, a despreading unit, and a first signal determination unit. The multiplexed signal receiving unit receives the multiplexed signal transmitted from each of the n transmitters. The clock recovery unit determines whether or not the received signal output from the multiplexed signal receiving unit exceeds a preset first threshold value, whereby comb pulses generated in each of the n transmitters are A combined reproduction clock signal is generated. The despreading unit calculates and outputs a correlation value between the received signal extracted at the timing of every n pulses of the recovered clock signal and each of the plurality of spreading coefficients. The first signal determination unit reproduces the plurality of bit signals of each of the n transmitters by determining whether the output of the despreading unit exceeds a preset second threshold value.

  According to the present invention, the comb pulse is generated based on the clock signal, and the spreading sequence is generated in synchronization with the generated comb pulse, so that the phase of the code of the spreading sequence can be synchronized with high accuracy between a plurality of signals. Can do. Further, the receiver can perform despreading with high accuracy based on the comb pulse signal transmitted after being added to the spread sequence. As a result, the communication system of the present invention can code-multiplex and multiplex a larger number of bit signals without error than conventional ones.

  According to another aspect of the present invention, each of the plurality of transmitters transmits a multiplexed signal by code division multiplexing generated in synchronization with the comb pulse during the assigned time slot. Each transmitter can transmit a transmission signal without interfering with transmission signals from other transmitters.

  According to still another aspect of the present invention, each of the plurality of transmitters transmits a multiplexed signal by code division multiplexing generated in synchronization with a comb pulse between corresponding time slots for each pulse. Since transmission is performed, each transmitter can transmit a transmission signal without causing interference with transmission signals from other transmitters.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing a schematic configuration of a communication system 1 according to Embodiment 1 of the present invention. With reference to FIG. 1, the communication system 1 includes a transmitter 101 and a receiver 102.

  The transmitter 101 receives n data signals Db0 to Dbn-1 (referred to as data signal Dtrns when generically referred to), converts them into a multiplexed signal Lsig0, which is an optical signal that has been code division multiplexed, and receives the signal. 102. Here, each of the data signals Db0 to Dbn-1 is a 1-bit pulse signal.

  In the transmission optical path 20, the signal strength of the transmitted multiplexed signal Lsig0 is attenuated (transmission gain Ag <1), and additive noise Na is superimposed on the multiplexed signal Lsig0. When the multiplexed signal Lsig1 having a reduced SNR (Signal-to-Noise Ratio) reaches the receiver 102, the receiver 102 receives the original n pieces of data from the received multiplexed signal Lsig1. The signals Db0 to Dbn-1 are reproduced. The reproduced data signals Db0 to Dbn-1 are collectively referred to as a reproduced data signal Drecv. Hereinafter, configurations and operations of the transmitter 101 and the receiver 102 will be described in detail.

  FIG. 2 is a block diagram showing a configuration of the transmitter 101 of FIG. Referring to FIG. 2, transmitter 101 includes an input terminal CNCS as a signal input unit that receives data signal Dtrns, comb-shaped pulse generation unit 403, spread modulation unit 41, and multiplexed signal generation unit 37.

  The comb pulse generator 403 repeatedly generates comb pulses, which are n pulse groups having the same height, based on the clock signal CLK input from the outside. The number n of comb pulses is equal to the sequence length n of the spreading sequence described later. The repetition period of the comb pulse is equal to the bit period of the data signal Dtrns (reference symbol Tb in FIG. 5). Comb pulse signal CLKCOM in which the comb pulse is repeated is output to spread modulation section 41 and multiplexed signal generation section 37.

  As an example of a specific configuration, the comb pulse generator 403 includes a timer circuit 4031 and a gate circuit 4032 as shown in FIG. In this case, the clock signal CLK is a continuous pulse train. The timer circuit 4031 outputs an activation signal having a time width corresponding to the number of pulses n to the gate circuit 4032. Gate circuit 4032 passes clock signal CLK while receiving the activation signal from timer circuit 4031. Accordingly, the comb pulse generator 403 generates a comb pulse having the number of pulses n.

The spread modulation unit 41 includes a spread sequence generation unit 411 and an encoding unit 412. Spreading sequence generation section 411 generates a plurality of spreading sequences having a sequence length n and outputs the generated spreading sequences to encoding section 412. These spreading sequences are individually assigned to the data signals Db0 to Dbn-1. Note that the sequence length of the spreading code only needs to be equal to or greater than the number of data of the data signal Dtrns, but here, for the sake of simplicity, it is assumed that the sequence length n is equal to the number of data n of the data signals Db0 to Dbn-1. To do. In the first embodiment, the plurality of spreading sequences are the basic spreading sequence G0: {h (0), h (1), h (2),..., H (n-2), h (n-1)} … (1)
Is generated by cyclic shift.

  FIG. 3 is a diagram illustrating an example of a basic spreading sequence. The spreading code in FIG. 3 is an M-sequence code (Maximum length Code) having a sequence length (period) n of 63 (degree 6). The M series is a kind of signal called a pseudo noise signal (also referred to as a PN (Pseudo Noise) signal).

  FIG. 4 is a diagram for explaining spreading sequences G0 to Gn-1 by cyclic shift. As shown in FIG. 4, spreading sequences G1 to Gn−1 are generated corresponding to the shift amounts τ = 1, 2,..., N−1, respectively. The case where the shift amount τ = 0 is the basic spreading sequence G0. Spreading sequences G0 to Gn-1 are assigned to data signals Db0 to Dbn-1. Here, spreading sequences G0 to Gn-1 indicate the correlation shown in the following equations (2) and (3) when the convolution integral operator is represented by "*". However, in the following formulas (2) and (3), i and j are integers of 0 or more and n or less.

Gi * Gj = 1 (i = j) (2)
Gi * Gj = 0 (i ≠ j) (3)
The merit of generating the n spreading sequences G0 to Gn-1 by cyclically shifting the basic spreading sequence G0 in this way is that n spreading sequences are used by using only one correlator corresponding to the basic spreading sequence G0. It exists in the point which can carry out the back diffusion of G0-Gn-1. In the case of the first embodiment, the code sequences for two periods of the basic spreading sequence G0 shown in FIG. 4 are arranged in reverse order R: {h (n-1), h (n-2), ..., h (1) , H (0), h (n-1), ..., h (0)} (4)
Is used to obtain the correlation value with the received signal. As will be described later with reference to FIG. 9, a time corresponding to twice the sequence length n in the received signal received by the receiver 102 is stored in the shift register. Then, de-spreading is performed by sequentially calculating the correlation value between the received signal stored in the shift register and the code sequence R in accordance with the timing of the internal clock pulse generated based on the comb pulse.

  Referring to FIG. 2 again, for each data signal Db0 to Dbn−1 received via input terminal CNCS, encoding unit 412 synchronizes the corresponding encoded sequence with the comb pulse according to the bit data of each data signal. And output. Specifically, the bit data of the data signal Dbi (in this case, i is an integer from 0 to n−1) among the data signals Db0 to Dbn−1 is the first logic level (hereinafter “1”). ), The corresponding spreading sequence Gi is output. When the bit data of the data signal Dbi is at the second logic level (hereinafter referred to as “0”), a 0 level signal is output. That is, when the bit data of the data signal Dbi is represented by Dbi = 1 or 0, for each of 0 ≦ i ≦ n−1, a pulse train Dcode obtained by multiplying Dbi and Gbi is output in synchronization with the comb pulse. .

  The multiplexed signal generation unit 37 includes an addition unit 372, an amplifier 371, and the electrical / optical converter 15.

  The adder 372 adds the output of the comb pulse generator 403 and the output of the encoder 412 and outputs the result as a multiplexed signal Ssnd. Therefore, multiplexed signal Ssnd is represented by the following equation using comb pulse signal CLKCOM, data signals Db0 to Dbn-1, and spreading sequences G0 to Gn-1.

Ssnd = CLKCOM + Db0 × G0 + Db1 × G1 + ... + Dbn-1 × Gn-1 (5)
The multiplexed signal Ssnd is amplified by the amplifier 371, converted to the multiplexed signal Lsig 0 of the optical signal by the electric / optical converter 15, and transmitted to the receiver 102. As the electrical / optical converter 15, for example, a method of directly modulating a semiconductor laser, a method of modulating output light of a semiconductor laser with an external modulator, or the like can be used.

  FIG. 5 is a timing diagram schematically showing each signal waveform of the transmitter 101. With reference to FIG. 5, the signal waveforms of the clock signal CLK, the data signal Dtrns, and the multiplexed signal Ssnd will be described collectively.

  As shown in the upper part of FIG. 5, the timing of each signal is determined based on a clock signal CLK that is a continuous pulse group. Data signals Db0 to Dbn-1 are each a 1-bit signal repeated at bit period Tb. The multiplexed signal Ssnd is a pulse train that is repeated every bit period Tb. In the bit period Tb, the pulse train of the multiplexed signal Ssnd appears in the first half section Tb1, and the second half section Tb2 is a no-signal section. In order to avoid interference of the multiplexed signal Ssnd between the adjacent bit periods Tb, the first half section Tb1 is set to a time equal to or less than half of the bit period Tb.

  The middle part of FIG. 5 is an enlarged view of the multiplexed signal Ssnd in the section Tb1. As already described, the multiplexed signal Ssnd is generated by synchronously adding n pulse trains Dcode obtained by performing spread modulation on the data signals Db0 to Dbn-1, and further by synchronously adding the comb pulse signal CLKCOM. A signal obtained by synchronously adding n pulse trains Dcode has a signal intensity corresponding to a maximum of n bits. The chip period Tc of the multiplexed signal Ssnd corresponds to the minimum shift amount τ = 1 when the basic spreading sequence G0 is cyclically shifted.

  The reason why the comb-shaped pulse signal CLKCOM is included in the transmission signal is to facilitate acquisition of synchronization during reception. As shown in the lower part of FIG. 5, the receiver 102 can reproduce the comb pulse signal CLKCOM by determining whether or not the received signal Srcv0 has exceeded the first threshold value THRL. The signal intensity of the comb-shaped pulse signal CLKCOM is set to be sufficiently larger than the noise intensity of the transmission optical path 20 so that the comb-shaped pulse signal CLKCOM can be easily separated and detected during reception.

Next, the configuration and operation of the receiver 102 will be described.
FIG. 6 is a block diagram illustrating a configuration of the receiver 102 of FIG. Referring to FIG. 6, receiver 102 includes a multiplexed signal receiving unit 103 that receives multiplexed signal Lsig 1, a clock recovery unit 375, a despreading unit 106, and a first signal determination unit 44. Among these, the multiplexed signal receiving unit 103 includes an optical / electrical converter 12, an AC-coupled amplifier 104 </ b> A, and a baseline recovery circuit (BLR: Base-Line Restorer) 105.

  The optical / electrical converter 12 is a device such as a photodiode that converts the multiplexed signal Lsig1 that is an optical signal into an electrical signal. The output of the optical / electrical converter 12 is amplified by an AC coupled amplifier 104A. As shown in FIG. 6, one end of the capacitor CAC is connected to the output node of the amplifier 104, and the other end of the capacitor CAC is connected to the baseline regeneration circuit 105. When a DC coupled amplifier is used, the influence of baseline drift cannot be ignored. On the other hand, the baseline drift can be avoided by using the AC coupling, but the baseline varies when the pulse time series signal is processed. At this time, if the fluctuation amount exceeds several percent, it becomes difficult to determine the threshold value of the signal. Therefore, a baseline regeneration circuit 105 is provided in order to prevent fluctuations in the baseline.

  FIG. 7 is a circuit diagram showing an example of the baseline reproduction circuit 105. Referring to FIG. 7, the baseline reproduction circuit 105 is a circuit that returns the potential of the connection node 1051 to the capacitor to the reference potential Vstd when the multiplexed signal Lsig1 is not input. Baseline reproduction circuit 105 includes resistance elements R1, R2 and diodes D1, D2. A resistance element R1 and a forward diode D2 are connected in series between a power supply node 1052 for applying a positive bias voltage + VB and a connection node 1051. Resistance element R2 is connected between power supply node 1053 for applying negative bias voltage -VB and connection node 1051. A forward diode D1 is connected between a connection node 1054 for resistance element R1 and diode D2 and ground node 1055 for supplying reference potential Vstd.

  The operation of the baseline reproduction circuit 105 in FIG. 7 is as follows. When there is no signal, ½ times the current VB / R1 flowing through the resistance element R1 becomes equal to the current VB / R2 flowing through the resistance element R2. As a result, the potential VN of the connection node 1051 becomes equal to the reference potential Vstd. On the other hand, when the signal is input, the diode D2 is turned off, so that the output of the AC coupled amplifier 104A is transmitted as the received signal Srcv0 without distortion.

  Referring to FIG. 6 again, received signal Srcv0 output from baseline recovery circuit 105 is input to clock recovery unit 375 and despreading unit 106. As described with reference to FIG. 5, the clock regeneration unit 375 regenerates the comb pulse signal CLKCOM used as a clock signal by determining whether or not the received signal Srcv0 exceeds the first threshold value THRL stored in the memory 376. To do. The reproduced comb pulse signal CLKCOM is supplied to the despreading unit 106 and the signal determination unit 44.

  FIG. 8 is a block diagram illustrating an example of the configuration of the clock recovery unit 375. The clock recovery unit 375 includes a comparator 3751 and a pulse shaping circuit 3752. The comparator 3751 outputs an H level signal when the received signal Srcv0 exceeds the first threshold value THRL. The pulse shaping circuit 3752 shapes the output waveform of the comparator 3751 and adjusts the pulse width. The whisker signal output from the comparator 3751 is ignored by the pulse shaping circuit 3752.

  Referring to FIG. 6 again, despreading section 106 receives received signal Srcv0 output from multiplexed signal receiving section 103 and a plurality of spreading sequences G0 to Gn-1 in accordance with reproduced comb pulse signal CLKCOM. Find the correlation value. The despreading unit 106 includes a multilevel quantization unit 107 and a matched filter 43.

  The multilevel quantization unit 107 quantizes the reception signal Srcv0 in accordance with the timing of the comb pulse signal CLKCOM. As described above, the received signal Srcv0 is originally obtained by synchronously adding n pulse trains Dcode obtained by spreading-modulating n data signals Db0 to Dbn-1 in the transmitter 101, and further adding a comb pulse signal CLKCOM by synchronous addition. It is generated by doing. Therefore, the multi-level quantization unit 107 needs to have quantization accuracy for discriminating at least n-bit signals. Note that the comb-shaped pulse signal CLKCOM and the received signal Srcv0 both have n pulse trains per bit period Tb, so that the received signal Srcv0 can be effectively quantized using the comb-shaped pulse signal CLKCOM. Further, the output of the multilevel quantization unit 107 is 0 at a timing different from that of the comb-shaped pulse having the number of pulses n.

  The reception signal Srcv1 generated by quantizing the reception signal Srcv0 by the multilevel quantization unit 107 is supplied to the matched filter 43. The regenerated comb pulse signal CLKCOM is also supplied to the matched filter 43.

  FIG. 9 is a block diagram showing a configuration of the matched filter 43 of FIG. The matched filter 43 receives a comb-shaped pulse signal CLKCOM used as a synchronization signal. Referring to FIG. 9, matched filter 43 includes internal clock generation unit 434, multi-value shift register 431, spreading sequence generation unit 402 that generates basic spreading sequence G0, correlation value calculation unit 433, And a signal detection unit 433A as a signal determination unit.

  The internal clock generation unit 434 receives the comb-shaped pulse signal CLKCOM and newly generates a comb-shaped pulse having the number of pulses n having the chip period Tc following the comb-shaped pulse having the number of pulses n. As a result, an internal clock pulse Tint having the number of pulses 2n having the chip period Tc is generated. The internal clock generation unit 434 outputs the generated internal clock pulse Tint to the multi-value shift register 431 and the correlation value calculation unit 433.

  Multi-level shift register 431 includes flip-flops 431 (1) to 431 (2n) that are twice as many as sequence length n of basic spreading sequence G0. Each flip-flop temporarily stores multi-bit data. The multilevel shift register 431 stores the reception signal Srcv1 quantized by the multilevel quantization unit 107 in synchronization with the internal clock pulse Tint. The reception signal Srcv1 at the current time is stored in the flip-flop 431 (1), and the previous data by the chip period Tc is sequentially stored in the flip-flops 431 (2) to 431 (2n). Therefore, the reception signal Srcv1 that is Tc × (2n−1) before the current time is stored in the flip-flop 431 (2n).

  Note that the flip-flops 431 (1) to 431 (n) can also be said to be registers that store multi-bit data, and thus the multi-value shift register 431 has 2n registers 431 (1) to 431 (2n). Can be considered as a multiple-type register in which are connected.

  With the above configuration, in accordance with the timing of n pulses in the first half of the internal clock pulse Tint, the part of the pulse train having the number of pulses n in the 1-bit period of the reception signal Srcv1 is flip-flops 431 (1) to 431 (n ) In order. As will be described later, the correlation value calculation unit 433 outputs a correlation value between the received signal Srcv1 and the basic spreading sequence G0 at the timing of the last nth pulse of the first half of the internal clock pulse Tint. Then, in accordance with the timing of n pulses in the latter half of the internal clock pulse Tint, the stored pulse train of the number n of pulses is transferred to the adjacent flip-flop, and the received signal Srcv1 and the remaining spreading sequences G1 to Gn− 1 and the correlation value with the spreading sequence G0 are sequentially output.

  Correlation value calculation section 433 calculates the correlation value between two periods of basic spreading sequence G0, which is despreading sequence R, and received signal Srcv1 stored in shift register 431 in real time in accordance with the timing of internal clock pulse Tint. Calculated and sequentially output as a reproduction signal Srec. Correlation value calculation section 433 includes coefficient calculation section 432 and addition circuits 433B, 433C, and 433F.

  The coefficient calculation unit 432 includes 2n calculation circuits 432 (1) to 432 (2n) provided corresponding to the 2n flip-flops 431 (1) to 431 (2n), respectively. In arithmetic circuits 432 (1) to 432 (2n), two cycles of basic spreading sequence G0 are stored in reverse order. When basic spreading sequence G0 is code 1, reception signal Srcv1 stored in the corresponding flip-flop is multiplied by +1 and output. When basic spreading sequence G0 is code 0, reception signal Srcv1 stored in the corresponding flip-flop is output. Is multiplied by -1 and output.

  The outputs of the coefficient calculation unit 432 are added by the addition circuits 433B and 433C. The adder circuit 433B obtains the sum of the calculation results of the reception signal Srcv1 and the coefficient calculation unit 432 stored in the first half 431 (1) to 431 (n) of the shift register 431. Therefore, the output UADD of the adder circuit 433B is equal to the correlation value between one period of the basic spreading sequence G0 and the reception signal Srcv1 stored in the first half 431 (1) to 431 (n) of the shift register 431. The correlation value in this case is calculated by adding reception signal Srcv1 corresponding to code 1 of basic spreading sequence G0 and subtracting reception signal Srcv1 corresponding to code 0 of basic spreading sequence G0. Of the coefficient calculation section 432, the first half calculation circuits 432 (1) to 432 (n) and the addition circuit 433B constitute a first correlation value calculation section 433U.

  Similarly, the adder circuit 433C obtains the sum of the calculation results of the reception signal Srcv1 and the coefficient calculation unit 432 stored in the latter half 431 (n + 1) to 431 (2n) of the shift register 431. Therefore, the output LADD of the adder circuit 433C is equal to the correlation value between one period of the basic spreading sequence G0 and the received signal Srcv1 stored in the latter half 431 (n + 1) to 431 (2n) of the shift register 431. The first correlation value calculation unit 433L is configured by the calculation circuits 432 (n + 1) to 432 (2n) in the first half of the coefficient calculation unit 432 and the addition circuit 433C.

  The adder circuit 433F adds the output UADD of the adder circuit 433B and the output LADD of the adder circuit 433C, and outputs the result as a reproduction signal Srec. Since a pulse train having a pulse number n for each bit period Tb in the received signal Srcv1 is sequentially transferred through the shift register 431, the adding circuit 433F performs spreading in the order of spreading sequences G0, G1,. The correlation value between the sequence and the received signal Srcv1 is output as the reproduction signal Srec.

  With the above configuration, the matched filter 43 uses the quantized received signal Srcv1 and the despread sequence R in Equation (4) to calculate the correlation value shown in the following Equation (6) in real time, and reproduces it. The signal Srec is output. In the following formula (6), * represents a convolution operator. Tc represents the chip period (corresponding to the cyclic shift amount τ = 1 of the spreading sequences G0 to Gn-1), and t represents time.

  The despreading sequence R (k) in the above equation (6) is obtained by arranging the code sequences for two periods of the basic spreading sequence G0 in the reverse order as described with reference to FIG. 4 and the equation (4). That is, R (0) = h (n−1), R (1) = h (n−2),..., R (n−1) = h (0), R (n) = h (n−1) , ..., R (2n-1) = h (0). As described above, the calculation of the correlation value between the quantized received signal Srcv1 and the despread sequence R is realized by the coefficient calculation unit 432 and the addition circuits 433B, 433C, and 433F.

  In the above equation (6), assuming that the timing of the first pulse of the internal clock pulse Tint is time t = 0, at time t = 0, Tc, 2Tc,..., (2n−1) Tc, the reproduction signal Srec (0 ), Srec (Tc), Srec (2Tc),..., Srec ((2n-1) Tc) are output in time series. The reproduction signal Srec ((n−1) Tc) output at time t = (n−1) Tc corresponds to the correlation value between the reception signal Srcv1 and the basic spreading sequence G0. Similarly, reproduction signals Srec output at times t = nTc to (2n−2) Tc correspond to correlation values with spread sequences G1 to Gn−1, respectively.

  At this time, the output at time t = 0 to (n−2) Tc is a correlation value with a part of the spread sequences G1 to Gn−1, and thus must be excluded from the output of the reproduction signal Srec. In order to perform this processing, signal detection section 433A described later detects the output timing of reproduction signal Srec corresponding to basic spreading sequence G0 at time t = (n−1) Tc. Further, the gate signal generation unit 445 and the reproduction signal discrimination unit 443 select and output n pulses of the reproduction signals Srec ((n−1) Tc) to Srec ((2n−2) Tc).

  As described with reference to FIG. 5, n pulse trains of the multiplexed signal Ssnd appear in the first half section Tb1 of the bit period Tb, and the second half section Tb2 is a no-signal section. Therefore, only the data for n out of 2n data stored in the multi-value shift register is necessary for the calculation of the correlation value with the spreading sequences G1 to Gn. Therefore, in practice, the correlation value can be calculated by n additions as shown in the following equation (7). However, in the following equation (7), time t = 0 is the time when the first pulse is received. Gq (G0 to Gn-1) is a cyclic shift of the basic spreading sequence as described with reference to FIG. 4, and can be replaced with R (n-1-k + t).

  Thus, according to the configuration of the matched filter 43, the data of the n quantized reception signals Srcv1 synchronized with the comb-shaped pulse signal CLKCOM is stored in the shift register 431 that temporarily stores 2n time-series data. Other data is 0. Therefore, there is a feature that unnecessary noise such as baseline noise is not generated by the calculation processing by the correlation value calculation unit 433.

  In addition, since the addition / subtraction calculation process by the correlation value calculation unit 433 is a kind of differential correlation process, the reference level of the reproduction signal Srec can be stabilized near zero level regardless of the intensity of the input signal. As a result, as described later, the second threshold value DSCL used for the threshold value determination of the signal determination unit 44 in the next stage can be set to a constant value that does not depend on the signal intensity, so that stable threshold value determination can be performed. .

  Next, the signal detection unit 433A will be described. The signal detection unit 433A includes comparators 433D and 433E and an AND circuit 433G.

  The comparator 433D sets the output Ucomp to the H level when the output UADD of the adder circuit 433B exceeds the threshold value K1. On the other hand, the comparator 433E sets the output Lcomp to the H level when the output LADD of the adder circuit 433C is less than the threshold value K2. The AND circuit 433G outputs a logical product AND of the output Ucomp of the comparator 433D and the output Lcomp of the comparator 433E as the first bit flag Fclk0. Therefore, in the signal detection unit 433A, one period of the spread sequence is stored in the first half 431 (1) to 431 (n) of the shift register 431, and the second half 431 (n + 1) to 431 (2n) is in the no-signal state. The timing is detected. This timing is equal to the timing at which the first bit corresponding to the basic spreading sequence G0 is output from the reproduction signal Srec output sequentially from the correlation value calculation unit 433. In this sense, the output signal of the signal detection unit 433A is referred to as a head bit flag Fclk0. The first bit flag Fclk0 is used in the signal determination unit 44 described later.

  Since the data signal Db0 corresponding to the basic spreading sequence G0 is used for detecting the first bit of the reproduction signal Srec, the bit data of the data signal Db0 must always be set to “1”. However, since the data signal Db0 is output in synchronization with the other data signals Db1 to Dbn-1, in the communication system 1 according to the first embodiment, the training bits in which “1” continues are used as the data signal for frame detection. There is no need to output before.

  FIG. 10 is a truth table of each signal in the leading bit detection circuit 433A. As shown in FIG. 10, when the output UADD of the adder circuit 433B is larger than the threshold value K1 and the output LADD of the adder circuit 433C is smaller than the threshold value K2, an H level (“1”) signal is output as the first bit flag Fclk0. I understand that

  FIG. 11 is a diagram illustrating an example of a signal waveform of the first bit flag Fclk0 obtained by numerical analysis. In FIG. 11, for the sake of convenience, the position of the head bit flag Fclk0 is arranged at the center of the signal waveform. As shown in FIG. 11, it can be seen that the head bit flag Fclk0 has a pulse waveform with excellent SNR.

  Referring to FIG. 6 again, the signal determination unit 44 determines whether the reproduction signal Srec output from the despreading unit 106 exceeds the second threshold value DSCL, thereby determining the data signals Db0 to Dbn−1. Reproduce. The reproduced data signals Db0 to Dbn-1 are output via the output terminal CNCR.

  FIG. 12 is a block diagram illustrating a configuration of the signal determination unit 44 of FIG. Referring to FIG. 12, signal determination unit 44 includes a gate signal generation unit 445, a reproduction signal discrimination unit 443, and a serial / parallel (S / P: Serial / Parallel) conversion unit 442.

  The gate signal generation unit 445 outputs the gate signal Gate in synchronization with the comb pulse signal CLKCOM. The gate signal Gate is activated to the H level for a time corresponding to the data number Ndat (= n) of the data signals Db0 to Dbn−1 after receiving the head bit flag Fclk0. The number of data Ndat is stored in the memory 441 in advance.

  The reproduction signal discriminating unit 443 receives the reproduction signal Srec while the gate signal Gate is activated. Then, the reproduction signal discriminating unit 443 determines whether or not the received reproduction signal Srec exceeds the second threshold value DSCL. The threshold value DSCL is stored in the memory 441 in advance. The reproduction signal discriminating unit 443 outputs an H level signal when the reproduction signal Srec exceeds the threshold value DSCL, and outputs an L level signal when the reproduction signal Srec is equal to or less than the threshold value DSCL.

  The serial / parallel converter 442 receives the serial output of the reproduction signal discriminating unit 443, converts it into a reproduction data signal Drecv that is a parallel signal, and outputs it. Thus, the reproduction of the data signals Db0 to Dbn-1 is completed.

  13 and 14 are diagrams showing numerical analysis examples of signal transmission by the communication system 1 of FIG. 13 and 14 are numerical analysis examples in the case where there is no signal attenuation by the transmission optical path 20. FIG. 13A is a diagram illustrating an example of bit data of the data signal Dtrns. In FIG. 13A, the horizontal axis indicates the numbers 1 to 63 of the input terminals CNCS, and the vertical axis indicates an example of bit data of the data signals Db0 to Db62 input to the input terminals CNCS. FIG. 13B shows an example of a basic spreading sequence G0 having a sequence length of 63. FIG. 13C shows the waveform of the multiplexed signal Ssnd output from the adder 372. The multiplexed signal Ssnd is obtained by synchronously adding spread sequences corresponding to the data signals having the bit data “1” in the data signals Db0 to Db62 of FIG. 13A and further synchronously adding comb pulses. It is. FIG. 14A shows a signal waveform of the reproduction signal Srec output from the despreading unit 106. The reproduction signal Srec is obtained by sequentially arranging the correlation values between the reception signal Srcv0 and each of the spreading sequences G0 to G62 in time series. In FIG. 14A, when the reproduction signal Srec exceeds the threshold value DSCL, it is determined as bit data “1”. FIG. 14B is a diagram showing a frequency distribution of the intensity of the reproduction signal Srec in FIG. As shown in FIG. 14B, the intensity of the reproduction signal Srec has two peaks corresponding to the bit data “0” and “1” of the data signal Dtrns. The threshold DSCL is set between these two peaks. FIG. 14C shows bit data of the reproduction data signal Drecv that is finally output to the reproduction signal Srec of FIG. 14A based on the determination result. It can be seen that the data signal Dtrns input to the transmitter 101 shown in FIG.

  As described above, according to the communication system 1 of the first embodiment, the comb pulse signal CLKCOM is generated based on the clock signal CLK. The spread modulation unit 41 outputs spread sequences G0 to Gn−1 corresponding to the data signal of the bit data “1” among the data signals Db0 to Dbn−1 in synchronization with the generated comb pulse signal CLKCOM. Therefore, the phase of the code | symbol of spreading | diffusion series G0-Gn-1 can be synchronized with a high precision between several data signals. Further, since comb pulse signal CLKCOM and spreading sequences G0 to Gn-1 are added and transmitted, receiver 102 performs despreading with high accuracy based on comb pulse signal CLKCOM reproduced from reception signal Srcv0. Can do. As a result, the communication system 1 according to the first embodiment can code-division multiplex a large number of data signals Db0 to Dbn-1 and transmit them without error as compared with the prior art.

  In addition, since both the transmitter 101 and the receiver 102 perform signal processing in real time in synchronization with the comb pulse signal CLKCOM, the signal processing circuit can be reduced in size and the apparatus can be downsized. As a result, the communication system of the first embodiment can be suitably used for a real-time control device that requires an immediate response.

  In the communication system 1 described above, the multiplexed signal Ssnd is converted to the optical signal Lsig0 and then transmitted to the receiver 102. However, it is not always necessary to convert the multiplexed signal Ssnd to the optical signal Lsig0. The baseband transmission can be performed with the electrical signal as it is, or a carrier wave of an appropriate frequency can be modulated and transmitted.

  In the communication system 1 described above, the transmitter 101 receives a plurality of data signals Db0 to Dbn-1 from the outside, converts the plurality of data signals Db0 to Dbn-1 into a multiplexed signal Ssnd, and transmits the signal. explained. On the other hand, the transmitter 101 receives a multi-bit data signal from the outside, divides the multi-bit data signal into a plurality of data signals Db0 to Dbn-1 for each bit, and thereafter, the multiplexed signal Ssnd. You may make it convert.

[Modification of Embodiment 1]
FIG. 15 is a block diagram showing a configuration of a matched filter 43A according to a modification of the first embodiment. The matched filter 43A in FIG. 15 differs from the matched filter 43 in FIG. 9 in that it further includes a delay circuit 433H. Further, the multi-value shift register 431 in FIG. 15 further includes a reset terminal RST for erasing bit information stored in the n registers 431 (n + 1) to 431 (2n) in the latter half. Different from the multi-value shift register 431. Since the matched filter 43A in FIG. 15 is common to the matched filter 43 in FIG. 9 in other points, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  The delay circuit 433H of FIG. 15 outputs the flag Fclk1 to the reset terminal RST of the multi-value shift register 431 based on the leading bit flag Fclk0 from the AND circuit 433G of the signal detection unit 433A. The flag Fclk1 is a pulse signal delayed from the head bit flag Fclk0 by n × Tc for one cycle of the spreading sequence. When the multi-value shift register 431 receives the flag Fclk1, the multi-value shift register 431 erases the bit information stored in the n registers 431 (n + 1) to 431 (2n) in the latter half.

  Thereby, when the despreading of the reception signal Srcv1 of the current bit period Tb is completed, the reception signal Srcv1 related to the current bit period Tb can be erased, so that the reception signal Srcv1 in the next bit period Tb can be promptly accepted. it can. As a result, the no-signal section Tb2 of FIG. 5 becomes unnecessary, and there is an advantage that transmission efficiency is improved.

[Embodiment 2]
In the second embodiment, the attenuation of the transmission optical path 20 is corrected from the amplitude level of the received monitor signal Mtrns by transmitting the monitor signal Mtrns and the data signal Dtrns together. In particular, when spatial transmission is performed without using an optical fiber in the transmission optical path 20, correction is necessary in consideration of fluctuations in the transmission gain Ag.

  FIG. 16 is a diagram illustrating a numerical analysis example of signal transmission by the communication system 1 in consideration of attenuation of the transmission optical path 20. FIG. 16A is a diagram showing a frequency distribution of the intensity of the reproduction signal Srec corresponding to FIG. In FIG. 14B, the transmission gain Ag of the transmission optical path 20 is 1, whereas FIG. 16A shows the case where the transmission gain Ag is 0.8. FIG. 16B shows bit data of the reproduction data signal Drecv that is finally output based on the reproduction signal Srec in FIG. Although the transmission optical path 20 is attenuated, the same threshold value DSCL as in FIG. 14B is used, and data is missing compared to FIG. 14C.

  As described above, when the transmission gain Ag of the transmission optical path 20 varies because the length of the transmission optical path 20 varies, the optical characteristics of the transmission optical path 20 vary, or noise due to external light increases. Cannot perform stable threshold determination. Therefore, in the second embodiment, the fluctuation of the transmission gain Ag is corrected using the monitor signal Mtrns as described below.

  FIG. 17 is a block diagram showing a schematic configuration of the communication system 2 according to the second embodiment of the present invention. In the transmitter 101A of FIG. 17, the spread modulation unit 41A further receives k monitor signals Mon1 to Monk (generally referred to as monitor signal Mtrns) in addition to the m data signals Db0 to Dbm-1. Thus, it differs from the transmitter 101 of FIG. 17 is different from the receiver 102 of FIG. 1 in that the receiver 102A of FIG. Hereinafter, differences from the first embodiment will be mainly described, and the same or corresponding points will be denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 18 is a block diagram showing a configuration of the transmitter 101A of FIG. 18 receives m data signals Db0 to Dbm-1 via an input terminal CNCS1, and receives k monitor signals Mon1 to Monk via an input terminal CNCS2. Usually, the bit data of the monitor signals Mon1 to Monk is always 1. In this specification, the data signal Dtrns and the monitor signal Mtrns are also collectively referred to as a bit signal.

  Spreading sequences G0 to Gn-1 are individually assigned to the monitor signal Mtrns and the data signal Dtrns. As in the case of the first embodiment, spreading sequences G0 to Gn-1 are obtained by cyclically shifting basic spreading sequence G0. The sequence length n of each spreading sequence needs to be m + k or more. In the second embodiment, the sequence length n is set equal to m + k for simplicity. Specifically, G0 to Gk-1 are assigned to the monitor signals Mon1 to Monk, respectively, and the remaining Gk to Gn-1 are assigned to the data signals Db0 to Dbm-1.

  The encoding unit 412A outputs spreading sequences G0 to Gk-1 corresponding to the monitor signals Mon1 to Monk in synchronization with the comb pulse signal CLKCOM. Also, the encoding unit 412 outputs the corresponding spreading code for the data signal whose bit data is “1” among the data signals Db0 to Dbm−1 in synchronization with the comb pulse signal CLKCOM. The pulse train Mcode corresponding to the monitor signal Mtrns output from the encoding unit 412A and the pulse train Dcode corresponding to the data signal Dtrns are synchronously added by the adder 372. Further, the adder 372 synchronously adds the comb pulse signal CLKCOM.

  FIG. 19 is a table showing an example of assignment of spreading sequences G0 to G62 to the data signal Dtrns and the monitor signal Mtrns. Cyclic shift amounts 0 to 31 are assigned to 32 monitor signals Mon1 to Mon32, and cyclic shift amounts 32 to 62 are assigned to 31 data signals Db0 to Db30, respectively.

  FIG. 20 is a block diagram illustrating a configuration of the receiver 102A in FIG. As shown in FIG. 20, the transmission line monitor 446 receives the comb pulse signal CLKCOM regenerated by the clock regenerating unit 375, the regenerated signal Srec output from the matched filter 43, and the head bit flag Fclk0, and outputs a threshold value DSCL. To do. The transmission line monitor 446 detects the monitor signals Mon1 to Monk included in the reproduction signal Srec based on the comb pulse signal CLKCOM and the head bit flag Fclk0, and obtains an average value <Mon> thereof.

<Mon> = (Mon1 + Mon2 + ... + Monk) / k (8)
The transmission path monitor 446 determines the threshold value DSCL of the reproduction signal Srec according to the following equation (9) using the average value <Mon>. In the following equation, ξ is a preset constant.

DSCL = ξ × <Mon> (9)
Thus, if the threshold value DSCL of the reproduction signal Srec is determined according to the equation (9), the threshold value determination of the reproduction signal Srec can be performed with an appropriate threshold value DSCL corresponding to the transmission gain of the transmission optical path 20.

  FIG. 21 is a block diagram illustrating a configuration of the signal determination unit 44A of FIG. Referring to FIG. 21, signal determination unit 44A includes a gate signal generation unit 445A, a reproduction signal discrimination unit 443, and a serial / parallel conversion unit 442.

  The gate signal generation unit 445A in FIG. 21 outputs the gate signal Gate based on the comb pulse signal CLKCOM. The gate signal Gate is activated to H level when a time corresponding to the number of data Kclk (= k) of the monitor signals Mon1 to Monk elapses after receiving the head bit flag Fclk0. Thereafter, the gate signal Gate returns to the L level when a time corresponding to the number of data Ndat (= m) of the data signals Db0 to Dbm−1 has elapsed. The data numbers Ndat and Kclk are stored in advance in the memory 441A.

  The reproduction signal discriminating unit 443 determines whether or not the reproduction signal Srec exceeds the threshold value DSCL while the gate signal is activated. The threshold value DSCL is supplied in advance from the transmission line monitor 446. The reproduction signal discriminating unit 443 outputs an H level signal when the reproduction signal Srec exceeds the threshold value DSCL, and outputs an L level signal when the reproduction signal Srec is equal to or less than the threshold value DSCL.

  FIG. 22 is a timing chart schematically showing waveforms of respective parts of the signal determination unit 44A of FIG. The head bit flag Fclk0, the comb pulse signal CLKCOM, the reproduction signal Srec, the threshold value DSCL, the gate signal Gate, and the serial reproduction data signal Drecv0 are shown in order from the top of FIG.

  Referring to FIG. 22, when matched filter 43 in FIG. 20 outputs first bit flag Fclk0, transmission path monitor 446 in FIG. 20 is based on reproduction signal Srec for the number of data Kclk including the timing of first bit flag Fclk0. The threshold value DSCL is output in accordance with the above-described equation (9). Further, the gate signal generation unit 445A of FIG. 21 outputs the gate signal Gate activated to the H level for a time corresponding to the data number Ndat excluding the reproduction signal Srec for the data number Kclk. While the gate signal Gate is activated, the reproduction signal discriminating unit 443 determines whether or not the reproduction signal Srec exceeds the threshold value DSCL and outputs a serial reproduction data signal Drecv0.

[Modification of Embodiment 2]
FIG. 23 is a block diagram showing a configuration of a receiver 102B according to a modification of the second embodiment of the present invention. The transmission line monitor 446B in FIG. 23 differs from the transmission line monitor 446 in FIG. 20 in that it has an alarm output ALARM. Since the other points are the same as those in FIG. 20, the same or corresponding parts are denoted by the same reference numerals as in FIG. 20, and description thereof will not be repeated.

  The transmission path monitor 446B of FIG. 23 obtains the value of the standard deviation σmon in addition to the average value <Mon> of the monitor signals Mon1 to Monk. When the standard deviation σmon is less than or equal to the allowable value, the transmission line monitor 446B is determined to be normal because it is within the range of statistical variation. If the standard deviation σmon exceeds the allowable value, the transmission line monitor 446B determines that an abnormality has occurred and issues an alarm. Further, even when the average value <Mon> changes suddenly, an alarm can be issued even if it is determined to be abnormal.

  FIG. 24 is a diagram showing a frequency distribution of the monitor signal Mtrns in the reproduction signal Srec. As already described, the threshold value DSCL is determined according to the equation (9) based on the average value <Mon> of the monitor signals Mon1 to Monk. Further, the abnormality of the transmission optical path 20 is determined based on the standard deviation σmon of the monitor signals Mon1 to Monk.

As described above, according to the receiver 102B of the modification of the second embodiment, the state of the transmission optical path 20 is constantly monitored, so that even if there is a sudden increase in noise or a decrease in transmission gain, it can be promptly performed. By detecting an abnormality in the transmission optical path 20, it is possible to prevent erroneous signal detection.
[Embodiment 3]
Embodiment 3 is an example of a case where a plurality of communication devices are connected to the same transmission path and communicate with each other.

  FIG. 25 is a block diagram showing a schematic configuration of the communication system 3 according to the third embodiment of the present invention. Referring to FIG. 25, communication system 3 includes five communication devices Adev to Edev connected to transmission optical path 20. Each communication device includes a transmitter 501 and a receiver 502. Each transmitter 501 of the communication devices Adev to Edev transmits optical signals Lsig0_A to Lsig0_E to 20 on a common transmission optical path, respectively. Each receiver 502 of the communication devices Adev to Edev receives from the transmission optical path 20 a received signal Lsig1 generated by combining the optical signals Lsig0_A to Lsig0_E.

  In Embodiment 3, each bit period Tb is divided into five time slots equal to the number of transmitters 501. Communication devices Adev to Edev are assigned to each time slot in this order. Each transmitter 501 of the communication devices Adev to Edev transmits the optical signals Lsig0_A to Lsig0_E to the transmission optical path 20 during the assigned time slot, respectively. As a result, interference between optical signals between transmitters can be avoided.

  FIG. 26 is a block diagram showing a configuration of the communication device Adev of FIG. Since all of the five communication devices Adev to Edev in FIG. 25 have the same configuration including the transmitter 501 and the receiver 502, FIG. 26 shows the configuration of the communication device Adev as a representative of these.

  Referring to FIG. 26, transmitter 501 includes m data signals DT0 to DTm-1 (referred to collectively as data signal Dtrns_A) and k monitor signals Mon1 to Monk (referred to collectively as monitor signal Mtrns). ) And p device attribute signals Code1 to Codep (generally referred to as device attribute signal Dev) are received from the input terminal CNCS and converted into a multiplexed signal Lsig0_A which is an optical signal that has been code division multiplexed. The converted multiplexed signal Lsig0_A is transmitted toward the transmission optical path 20. The transmitter Adev includes an input terminal CNCS as a signal input unit, a comb pulse generation unit 403A, a spread modulation unit 41B, and a multiplexed signal generation unit 37.

  Comb pulse generation unit 403A repeats comb pulses, which are n pulse groups having the same height, based on clock signal CLK input from the outside, similarly to comb pulse generation unit 403 of the first and second embodiments. Generate. The number n of comb pulses is equal to the sequence length n of the spreading sequence. The repetition period of the comb pulse is equal to the bit period of the data signal Dtrns_A.

  However, unlike Embodiments 1 and 2, in Embodiment 3, the timing is adjusted so that a comb-shaped pulse is output during each time slot assigned to itself. For this reason, the comb-shaped pulse generation unit 403A generates a comb-shaped pulse with reference to the timing of the first bit flag Fclk0 detected at 502 by the receiver. Comb pulse signal CLKCOM in which the comb pulse is repeated is output to spread modulation section 41 </ b> B and multiplexed signal generation section 37.

  The spread modulation unit 41B receives m data signals DT0 to DTm-1, k monitor signals Mon1 to Monk, and p device attribute signals Code1 to Codep. These signals are all 1-bit pulse signals, and different spreading sequences are assigned to them. Specifically, spreading sequences G0 to Gn-1 due to cyclic shift of basic spreading sequence G0 are assigned to input terminals CNCS (in the case of Embodiment 3, input terminals 0 to 62), respectively. Since the details of the spreading sequence are as described in FIG. 4 of the first embodiment, description thereof will not be repeated. Note that n needs to be m + k + p or more. In the case of Embodiment 3, n = 63, m = 22, k = 38, and p = 3.

  The monitor signal Mtrns is a signal used to correct the fluctuation of the transmission gain of the transmission optical path 20. Details of monitor signal Mtrns are as described in the second embodiment, and therefore description thereof will not be repeated.

  FIG. 27 is a table showing an example of the device attribute signal Dev. The device attribute signal Dev is a p-bit (p = 3) signal for indicating the transmission source of the optical signal. As shown in FIG. 27, a unique signal is assigned to each of the communication devices Adev to Edev. For example, Code 1 = 0, Code 2 = 0, and Code 3 = 1 are assigned to the communication device Adev.

FIG. 28 is a table showing an example of signal allocation to the input terminal CNCS of the transmitter 501.
Referring to FIG. 28, each transmitter 501 of communication apparatuses Adev to Edev has input terminals CNCS (input terminals 0 to 62), and data signals DT0 to DT21 and monitor signals Mon1 to Mon38 are input terminals 0 to 62, respectively. , And device attribute signals Code1 to Code3, respectively.

  The data signal Dtrns includes a frame signal fclk0 indicating the beginning of data and a data signal destined for each communication device. In any of the communication devices Adev to Edev, the data signal Dtrns starts with the frame signal fclk0 and is input to the input terminal 0. The frame signal fclk0 is always fixed to “1” and the basic spreading sequence G0 is assigned.

  As shown in FIG. 28, for example, the data signal Dtrns_A transmitted from the communication device Adev includes data signals Db0 to Db6 destined for the communication device Bdev and data destined for the communication device Cdev in addition to the frame signal fclk0. Signals Dc0 to Dc3, data signals Dd0 to Dd3 destined for communication device Ddev, and data signals De0 to De5 destined for communication device Edev are included. As described above, each communication device has a different destination, and the number of bit signals transmitted to each communication device is also different. As will be described later with reference to FIGS. 29 and 30, destination information for each of the communication devices Adev to Edev is stored in the memory 441B of each receiver 502 of the communication devices Adev to Edev.

  The 3-bit device attribute signal Dev is input to the input terminals 60-62. A characteristic point of the communication system 3 according to the third embodiment is that a device attribute signal Dev to be the next transmission source is input to the input terminals 60 to 62. For example, device attribute signals (Code1 = 0, Code2 = 1, Code3 = 0) of the communication device Bdev are input to the input terminals 60 to 62 of the communication device Adev. As a result, each receiver 502 of the communication devices Adev to Edev can read out destination information and the like from the memory 441B in advance in preparation for receiving an optical signal from the communication device in the next transmission order. Switching can be performed smoothly.

  Referring to FIG. 26 again, as in the case of the first and second embodiments, the spread modulation unit 41B performs the data signal DT0 to DTm-1, the monitor signals Mon1 to Monk, and the device attribute signals Code1 to Codek. The spreading sequence corresponding to the bit data “1” is output in synchronization with the comb pulse. Details are the same as those in the first and second embodiments, and thus description thereof will not be repeated.

  Since the configuration and operation of multiplexed signal generation unit 37 are similar to those of the first and second embodiments, description thereof will not be repeated. The multiplexed signal Lsig0 generated by the multiplexed signal generation unit 37 is output to the optical transmission line 20.

  Next, the configuration of the receiver 502 will be described. The receiver 502 includes a multiplexed signal receiving unit 103 that receives the multiplexed signal Lsig1, a clock recovery unit 375, a despreading unit 106A, a transmission path monitor 446, and a first signal determination unit 44B. Of these components, multiplexed signal receiving section 103 and clock recovery section 375 are the same as in the first embodiment, and transmission path monitor 446 is the same as in the second embodiment, so the description will be repeated. Absent.

  The despreading unit 106A determines the correlation value between the received signal Srcv0 output from the multiplexed signal receiving unit 103 and the plurality of spread sequences G0 to Gn-1 in accordance with the comb pulse signal CLKCOM regenerated by the clock regenerating unit 375. Ask. The despreading unit 106A includes a multi-level quantization unit 107 that quantizes the reception signal Srcv0 in accordance with the timing of the comb pulse signal CLKCOM and a matched filter 43A.

  Here, the matched filter 43A has the same configuration as that of the modification of the first embodiment. According to the matched filter 43A in FIG. 15, when the despreading of the signal transmitted from a certain communication device is completed, the bit information stored in the n registers 431 (n + 1) to 431 (2n) in the latter half is deleted. To do. Thereby, the despreading of the signal transmitted from the next communication apparatus can be started promptly.

  The signal determination unit 44B reproduces the data signals DT0 to DTm-1 and the monitor signals Mon1 to Monk by determining whether or not the reproduction signal Srec output from the despreading unit 106A exceeds the second threshold value DSCL. . Further, the signal determination unit 44B discriminates a signal destined for itself from the reproduction signal Srec.

  FIG. 29 is a block diagram showing a configuration of the signal determination unit 44B of FIG. Referring to FIG. 29, signal determination unit 44A includes a gate signal generation unit 445B, a reproduction signal discrimination unit 443, and a serial / parallel conversion unit 442A.

  29 outputs the gate signal Gate based on the comb pulse signal CLKCOM. The gate signal Gate is activated only for a predetermined period after receiving the head bit flag Fclk0. More specifically, the gate signal Gate is activated only for the time corresponding to the number of cut data Ndat after the time corresponding to the cut start number Adr has elapsed after receiving the first bit flag Fclk0. . The reproduction signal discriminating unit 443 can discriminate only the signal addressed to itself based on the gate signal Gate. The gate signal Gate is activated only during a period corresponding to the device attribute signal Dev. The cut-out start number Adr and the cut-out data number Ndat are different values for the communication devices Adev to Edev that are optical signal transmission sources, and are stored in the memory 441B in advance.

  FIG. 30 is a diagram illustrating an example of a data table stored in the memory 441B. Referring to FIG. 30, in memory 441B, cut start number Adr and cut data number Ndat are stored for each of communication devices Adev to Edev, together with device attribute signal Dev described above.

  For example, when the transmission destination device is the communication device Adev, the data signal DT0 to DT21 transmitted from the communication device Bdev as the transmission source starts from the Adr (= 1) th data next to the frame signal fclk0, and Ndat (= 2) pieces of data are data destined for the communication device Adev. These data correspond to Da0 and Da1 input to the input terminals 1 and 2 in FIG. Similarly, Ndat (= 19) pieces of data signals DT0 to DT21 transmitted from the communication measure Cdev, which is the transmission source, starting from the Adr (= 1) th data next to the frame signal fclk0. Is the data destined for the communication device Adev. These data correspond to Da0 to Da18 input to the input terminals 1 to 19 in FIG. In addition, since there is no data signal transmitted from the communication measure Ddev as the transmission source to the communication device Adev, both the extraction start number Adr and the number of extracted data Ndat are set to 0.

  In general, when multiple communication devices are connected to a common transmission line, the signal connection is changed when the data destination is changed, such as by removing or adding some of these communication devices. There is a need to. In the case of cable wiring, a great deal of work is required to change the connection. According to the communication system 3 of the third embodiment, information on the mutual destinations between the communication devices Adev to Edev connected to the common transmission optical path 20 is stored in the memory 441B. Therefore, it is possible to cope with the change of the destination by only rewriting the information stored in the memory 441B without significantly changing the hardware. In particular, if the destination information can be rewritten by remote operation, it is possible to cope with the change of the destination even during the service period of the communication system.

  Referring to FIG. 29 again, reproduction signal discriminating unit 443 determines whether reproduction signal Srec exceeds threshold value DSCL while the gate signal is activated. As described in the second embodiment, the threshold value DSCL is supplied in advance from the transmission line monitor 446. The reproduction signal discriminating unit 443 outputs an H level signal when the reproduction signal Srec exceeds the threshold value DSCL, and outputs an L level signal when the reproduction signal Srec is equal to or less than the threshold value DSCL.

  The serial / parallel conversion unit 442A converts the serial output of the reproduction signal discriminating unit 443 into reproduction data signals Drecv_A to Drecv_E which are parallel signals, and outputs them. Further, the serial / parallel converter 442A outputs the device attribute signal Dev to the gate signal generator 445B. Based on the device attribute signal Dev received from the serial / parallel conversion unit 442A, the gate signal generation unit 445B reads the extraction start number Adr and the number of extraction data Ndat corresponding to the next transmission source from the memory 441B. In this way, the reproduction of the data signals DT0 to DTm-1 output from the transmitters 501 of the respective communication devices Adev to Edev as transmission sources is completed.

  FIG. 31 is a timing chart schematically showing waveforms of optical signals Lsig0_A to Lsig0_E transmitted from the communication devices Adev to Edev in FIG. FIG. 31 shows, in order from the top, the waveform of the clock signal CLK, the waveform of the data signal Dtrns_A input to the communication device A, and the waveforms of the optical signals Lsig0_A to Lsig0_E.

  Referring to FIG. 31, each bit period Tb includes time slot TSL1 at time t1 to t2, time slot TSL2 at time t2 to t3, time slot TSL3 at time t3 to t4, and time slot at time t4 to t5. The time slot is divided into five time slots consisting of TSL4 and time slot TSL5 at times t5 to t6. Optical signals Lsig0_A to Lsig0_E are transmitted to the time slots TSL1 to TSL5, respectively. These optical signals Lsig0_A to Lsig0_E are combined in the transmission optical path 20 of FIG. 25 and received as the optical signal Lsig1 by the receiver 502 of the communication devices Adev to Edev.

  FIG. 32 is a timing chart schematically showing the output waveform of the signal determination unit 44B. FIG. 32 shows, in order from the top, the waveform of the reproduction signal Srec generated by despreading by each receiver 502 of the communication devices Bdev to Edev, and the reproduction signal Srec by each signal determination unit 44B of the communication devices Bdev to Edev as transmission destinations. Shows a waveform of a data signal obtained by discriminating.

  Referring to FIG. 32, a reproduction signal Srec obtained by despreading the optical signal Lsig0_A transmitted from the communication device Adev includes a data signal (A / B, A in FIG. 32) addressed to each of the communication devices Bdev to Edev. / C, A / D, and A / E) are arranged in time series. The signal determination unit 44B of each receiver 502 of the communication devices Bdev to Edev discriminates and outputs data destined for itself from the reproduction signal Srec.

  As described above, according to the communication system 3 of the third embodiment, the transmitters 501 of the communication devices Adev to Edev use the optical signals Lsig0_A to Lsig0_E generated for each bit period Tb in the time slots assigned to themselves. Send each in between. Therefore, the optical signal transmitted from each transmitter 501 does not interfere with the optical signal transmitted from the other transmitter 501.

[Embodiment 4]
In the third embodiment, one time slot is assigned to the entire optical signal output from each transmitter 501 for each bit period Tb. In contrast, in the fourth embodiment, one time slot is assigned to each pulse of the optical signal transmitted from each transmitter 501. For this reason, in the case of Embodiment 4, it is necessary that the clocks are accurately synchronized between the transmitters 501.

  FIG. 33 is a block diagram showing a schematic configuration of the communication system 4 according to the fourth embodiment of the present invention. Referring to FIG. 33, the communication system 4 includes five communication devices Adev to Edev connected to the transmission optical path 20. Each communication device includes a transmitter 503, a receiver 504, and a clock generation circuit 510. Each transmitter 503 of the communication devices Adev to Edev transmits optical signals Lsig0_A to Lsig0_E to 20 on a common transmission optical path, respectively. Each receiver 504 of the communication devices Adev to Edev receives from the transmission optical path 20 a received signal Lsig1 generated by combining the optical signals Lsig0_A to Lsig0_E. Each clock generation circuit 510 of the communication devices Adev to Edev generates a clock signal based on the signal received by the receiver 504.

  In order to synchronize the clock, the frame signal fclk0 described in the third embodiment is used. In the fourth embodiment, only the frame signal fclk0 of the communication device Adev is set to “1”, and the frame signals fclk0 of the other communication devices Bdev to Edev are set to “0”. The other communication devices Bdev to Edev generate a clock signal based on the leading bit flag Fclk0 when the frame signal fclk0 transmitted from the communication device Adev is detected. As a result, the clocks of the other communication apparatuses Bdev to Edev are synchronized with the clock of the communication apparatus Adev.

  FIG. 34 is a block diagram illustrating a configuration of the communication device Adev. Since all of the five communication devices Adev to Edev in FIG. 33 have the same configuration including the transmitter 503, the receiver 504, and the clock generation circuit 510, FIG. 34 shows the configuration of the communication device Adev as a representative of these. ing.

  Referring to FIG. 34, transmitter 503 includes m data signals DT0 to DTm-1 (referred to collectively as data signal Dtrns_A) and k monitor signals Mon1 to Monk (referred to collectively as monitor signal Mtrns). ) From the input terminal CNCS is converted into a multiplexed signal Lsig0_A, which is an optical signal that has been code division multiplexed. The converted multiplexed signal Lsig0_A is transmitted toward the transmission optical path 20. The transmitter Adev includes an input terminal CNCS as a signal input unit, a comb pulse generation unit 403B, a spread modulation unit 41A, a delay circuit 511, and a multiplexed signal generation unit 37.

  Comb pulse generation unit 403B is a comb shape that is a group of n pulses having the same height based on clock signal CLK input from clock generation circuit 510, similarly to comb pulse generation unit 403 of the first and second embodiments. Generate pulses repeatedly. The number n of comb pulses is equal to the sequence length n of the spreading sequence. The repetition period of the comb pulse is equal to the bit period of the data signal Dtrns_A.

  However, unlike the first to third embodiments, in the fourth embodiment, the timing is adjusted so that each comb-shaped pulse is output one by one during each time slot assigned to itself. For this reason, the comb-shaped pulse generation unit 403B generates a comb-shaped pulse based on the timing delayed by a predetermined time by the delay circuit 511 from the first bit flag Fclk0 detected at 504 by the receiver. Specifically, the delay time in the communication device Adev is 0, and the delay times in the communication devices Bdev to Edev are TCLK, 2 × TCLK, 3 × TCLK, and 4 × TCLK, respectively (where TCLK is This is the cycle of the clock signal CLK output from the clock generation circuit 510). Comb pulse signal CLKCOM in which the comb pulse is repeated is output to spread modulation section 41A and multiplexed signal generation section 37.

  The spread modulation unit 41A receives m data signals DT0 to DTm-1 and k monitor signals Mon1 to Monk. These signals are all 1-bit pulse signals, and different spreading sequences are assigned to them. Specifically, spreading sequences G0 to Gn-1 obtained by cyclically shifting basic spreading sequence G0 are assigned to input terminals CNCS (in the case of the fourth embodiment, input terminals 0 to 62). Since the details of the spreading sequence are as described in FIG. 4 of the first embodiment, description thereof will not be repeated. In addition, n needs to be m + k or more. In the case of the fourth embodiment, n = 63, m = 22, and k = 41.

  The monitor signal Mtrns is a signal used to correct the fluctuation of the transmission gain of the transmission optical path 20. Details of monitor signal Mtrns are as described in the second embodiment, and therefore description thereof will not be repeated.

  As in the case of the second embodiment, the spread modulation unit 41A synchronizes the spread series corresponding to the case where the bit data is “1” with the comb pulse for each of the data signals DT0 to DTm−1 and the monitor signals Mon1 to Monk. And output. Details are the same as those in the second embodiment, and thus description thereof will not be repeated.

  Since the configuration and operation of multiplexed signal generation unit 37 are similar to those of the first and second embodiments, description thereof will not be repeated. The multiplexed signal Lsig0 generated by the multiplexed signal generation unit 37 is output to the optical transmission line 20.

  FIG. 35 is a table showing an example of signal assignment of the input terminal CNCS of the transmitter 503. The table of FIG. 35 corresponds to a table obtained by deleting the device attribute signals Code1 to Code3 from the table of FIG. However, in the case of FIG. 28, each of the frame signals fclk0 transmitted from the communication devices Adev to Edev is “1”, whereas in the case of FIG. 35, the frame signal transmitted from the communication device Adev. Only fclk0 becomes “1”.

  FIG. 36 is a timing chart schematically showing waveforms of optical signals Lsig0_A to Lsig0_E transmitted from the communication devices Adev to Edev in FIG. FIG. 36 shows, sequentially from the top, the waveform of the clock signal CLK, the waveform of the first bit flag Fclk0 detected by the receiver 504, and the waveforms of the optical signals Lsig0_A to Lsig0_E.

  FIG. 37 is an enlarged timing diagram of FIG. FIG. 36 shows the waveform of the head bit flag Fclk0 detected by the receiver 504 and the waveforms of the optical signals Lsig0_A to Lsig0_E in order from the top.

  Referring to FIGS. 36 and 37, in the case of the communication system of the fourth embodiment, the time width of time slot TSL is equal to clock cycle TCLK. Times t1 to t2, times t2 to t3, times t3 to t4, times t4 to t5, and times t5 to t6 in FIG. 37 correspond to the time slots TSL assigned to the communication devices Adev to Edev, respectively. The next time t6 to t7 becomes the time slot assigned to the communication device Adev again. Accordingly, the chip period Tc of each of the transmission signals Lsig0_A to Lsig0_E is equal to a value obtained by multiplying the clock period TCLK by the number of the transmitters 503 (5 times in the case of the fourth embodiment).

  One frame (bit period Tb) corresponds to a period from time t1 when the receiver 504 detects the first bit flag Fclk0 to time t8 when the receiver 504 detects the first bit flag Fclk0.

  Next, the configuration of the receiver 504 will be described with reference to FIG. 34 again. The receiver 504 includes a multiplexed signal receiving unit 103 that receives the multiplexed signal Lsig1, a clock recovery unit 375, a despreading unit 106B, a transmission path monitor 446, and a first signal determination unit 44C. Of these components, multiplexed signal receiving section 103 and clock recovery section 375 are the same as in the first embodiment, and transmission path monitor 446 is the same as in the second embodiment, so the description will be repeated. Absent.

  However, in the case of the fourth embodiment, the optical signals Lsig0_A to Lsig0_E output from the transmitters 503 of the communication devices Adev to Edev are multiplexed on the transmission optical path 20. Since each receiver 504 receives the multiplexed optical signal Lsig1, the signal output from the clock recovery unit 375 becomes a recovered clock signal RCLK whose period is equal to the period TCLK of the clock signal CLK.

  Based on the recovered clock signal RCLK recovered by the clock recovery unit 375A, the despreading unit 106B calculates the correlation value between the received signal Srcv0 output from the multiplexed signal receiving unit 103 and the plurality of spread sequences G0 to Gn-1. Ask. The despreading unit 106B includes a multi-level quantization unit 107 that quantizes the reception signal Srcv0 in accordance with the timing of the reproduction clock signal RCLK and a matched filter 43B. Multi-level quantization section 107 is as described in Embodiment 1, and therefore description thereof will not be repeated.

  FIG. 38 is a block diagram showing a configuration of the matched filter 43B constituting the despreading unit 106B. The matched filter 43B of FIG. 38 is different from the matched filter 43 of FIG. 9 in that it operates based on the regenerated clock signal RCLK without including the internal clock generation unit 434 and includes a moving addition circuit 436 instead of the addition circuit 433F. Different. Further, the matched filter 43B in FIG. 38 is different in the configuration of the multi-value shift register 435 from the configuration of the multi-value shift register 431 in FIG. In other respects, the configuration of the matched filter 43B in FIG. 38 is the same as the configuration of the matched filter in FIG. 9, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  Referring to FIG. 38, multi-value shift register 435 is a multiple-type register in which 10n-5 registers 435 (0) to 435 (10n-5) are connected, and is synchronized with reproduction clock signal RCLK. Works. Each register 435 (0) to 435 (10n-5) temporarily stores multi-bit data. The reception signal Srcv1 at the current time is stored in the register 435 (0), and the previous data is stored in the registers 435 (1) to 435 (10n-5) in order by the clock period TCLK of the reproduction clock signal RCLK. Since the chip cycle Tc is equal to five times the clock cycle TCLK, the register 435 (10n-5) stores the received signal Srcv1 that is Tc × (2n−1) before the current time. .

  The 2n arithmetic circuits 432 (1) to 432 (2n) constituting the coefficient arithmetic unit 432 correspond to each of the five registers among the registers 435 (0) to 435 (10n-5). That is, the register 435 ((i−1) × 5) corresponds to the arithmetic circuit 432 (i) (where i is an integer of 1 to 2n). In arithmetic circuits 432 (1) to 432 (2n), two cycles of basic spreading sequence G0 are stored in reverse order. When the basic spreading sequence G0 is code 1, the reception signal Srcv1 stored in the corresponding register is multiplied by +1 and output. When the basic spreading sequence G0 is code 0, the reception signal Srcv1 stored in the corresponding register is − Output by multiplying by 1.

  The movement adder circuit 436 adds the outputs of the arithmetic circuits 432 (1) to 432 (n) during the first five cycles of the recovered clock signal RCLK with reference to the head bit flag Fclk0, and during the next five cycles. Adds the outputs of the arithmetic circuits 432 (2) to 432 (n + 1). As described above, the moving addition circuit 436 performs addition while shifting the arithmetic circuit 432 to be added one by one every five cycles. As a result, the mobile adder circuit 436 outputs the operation result of the optical signals Lsig0_A to Lsig0_E and the spread sequences G0 to Gn-1 output from the transmitters 503 of the communication devices Adev to Edev as the reproduction signal Srec. .

  Referring to FIG. 34 again, the signal determination unit 44C determines whether or not the reproduction signal Srec output from the despreading unit 106B exceeds the second threshold value DSCL, thereby obtaining the data signals DT0 to DTm−1. Reproduce. Further, the signal determination unit 44C discriminates a signal destined for itself from the reproduction signal Srec.

  FIG. 39 is a block diagram showing a configuration of the signal determination unit 44C of FIG. Referring to FIG. 39, signal determination unit 44C includes a gate signal generation unit 445C, a reproduction signal discrimination unit 443A, and serial / parallel conversion units 442B (1) to 442B (5).

  The gate signal generation unit 445C in FIG. 39 outputs the gate signal Gate based on the reproduction clock signal RCLK. The gate signal Gate is activated only for a predetermined period with reference to the head bit flag Fclk0. More specifically, the gate signal Gate starts from a time slot corresponding to the extraction start number Adr determined for each of the transmission source communication devices Adev to Edev, and has a time corresponding to the number of extraction data Ndat. Only activated during the slot. The reproduction signal discriminating unit 443A can discriminate only the signal addressed to itself based on the gate signal Gate. The cut-out start number Adr and the cut-out data number Ndat are different values for the communication devices Adev to Edev that are optical signal transmission sources, and are stored in the memory 441B in advance. The stored contents of the memory 441B are the same as the part excluding the device attribute signal Dev in the table of FIG. 30, and therefore the description will not be repeated.

  In general, when multiple communication devices are connected to a common transmission line, the signal connection is changed when the data destination is changed, such as by removing or adding some of these communication devices. There is a need to. According to the communication system 4 of the fourth embodiment, information on the mutual destinations between the communication devices Adev to Edev connected to the common transmission optical path 20 is stored in the memory 441B. Therefore, it is possible to cope with the change of the destination by only rewriting the information stored in the memory 441B without significantly changing the hardware.

  The reproduction signal discriminating unit 443A determines whether or not the reproduction signal Srec exceeds the threshold value DSCL while the gate signal is activated. As described in the second embodiment, the threshold value DSCL is supplied in advance from the transmission line monitor 446. The reproduction signal discriminating unit 443A outputs an H level signal when the reproduction signal Srec exceeds the threshold DSCL, and outputs an L level signal when the reproduction signal Srec is less than the threshold DSCL. At this time, the reproduction signal discriminating unit 443A distributes and outputs the level determination results to the serial / parallel conversion units 442B (1) to 442B (5) for each of the transmission source communication devices Adev to Edev.

  The serial / parallel conversion units 442B (1) to 442B (5) convert the serial output of the reproduction signal discriminating unit 443A into reproduction data signals Drecv_A to Drecv_E which are parallel signals, and output them. In this way, the reproduction of the data signals DT0 to DTm-1 output from the transmitters 503 of the respective communication devices Adev to Edev as transmission sources is completed.

  FIG. 40 is a timing chart schematically showing the output waveform of the signal determination unit 44C. FIG. 40 is obtained by discriminating the reproduction signal Srec by the waveform of the head bit flag Fclk0, the waveform of the reproduction signal Srec input to the signal determination unit 44C, and the signal determination unit 44B of the transmission destination communication device Adev in order from the top. The waveforms of the received data signals Drecv (0) to Drecv (5) are shown.

  As already described, the reproduction signal discriminating unit 443A reproduces the data signals DT0 to DTm-1 from the reproduction signal Srec based on the head bit flag Fclk0. At this time, the output is distributed to each of the transmission source communication devices Adev to Edev. FIG. 40 shows such a situation.

  As described above, according to the communication system 4 of the fourth embodiment, the transmitters 503 of the communication devices Adev to Edev allocate the optical signals Lsig0_A to Lsig0_E generated for each bit period Tb for each pulse of the optical signal. Each time slot is transmitted one by one. Therefore, the optical signal transmitted from each transmitter 503 does not interfere with the optical signal transmitted from the other transmitter 503, and data transmission almost in real time can be realized.

The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows the schematic structure of the communication system 1 of Embodiment 1 of this invention. It is a block diagram which shows the structure of the transmitter 101 of FIG. It is a figure which shows an example of a basic spreading sequence. It is a figure for demonstrating the spreading | diffusion series G0-Gn-1 by cyclic shift. FIG. 4 is a timing diagram schematically showing signal waveforms of a transmitter 101. It is a block diagram which shows the structure of the receiver 102 of FIG. 3 is a circuit diagram showing an example of a baseline reproduction circuit 105. FIG. FIG. 38 is a block diagram illustrating an exemplary configuration of a clock recovery unit 375. It is a block diagram which shows the structure of the matched filter 43 of FIG. It is a truth table of each signal in the head bit detection circuit 433A. It is a figure which shows the example of the signal waveform of the head bit flag Fclk0 calculated | required by the numerical analysis. It is a block diagram which shows the structure of the signal determination part 44 of FIG. It is a figure which shows the numerical analysis example of the signal transmission by the communication system 1 of FIG. It is a figure which shows the numerical analysis example of the signal transmission by the communication system 1 of FIG. It is a block diagram which shows the structure of matched filter 43A by the modification of Embodiment 1. FIG. It is a figure which shows the numerical analysis example of the signal transmission by the communication system 1 when the attenuation | damping of the transmission optical path 20 is considered. It is a block diagram which shows schematic structure of the communication system 2 of Embodiment 2 of this invention. It is a block diagram which shows the structure of the transmitter 101A of FIG. It is a table | surface which shows an example of allocation of the spreading | diffusion series G0-G62 to the data signal Dtrns and the monitor signal Mtrns. It is a block diagram which shows the structure of the receiver 102A of FIG. It is a block diagram which shows the structure of 44 A of signal determination parts of FIG. FIG. 22 is a timing diagram schematically illustrating waveforms of respective units of the signal determination unit 44A in FIG. 21. It is a block diagram which shows the structure of the receiver 102B by the modification of Embodiment 2 of this invention. It is a figure which shows the frequency distribution of the monitor signal Mtrns among the reproduction signals Srec. It is a block diagram which shows schematic structure of the communication system 3 by Embodiment 3 of this invention. It is a block diagram which shows the structure of the communication apparatus Adev of FIG. It is a table | surface which shows an example of the apparatus attribute signal Dev. 10 is a table showing an example of signal assignment to an input terminal CNCS of a transmitter 501. It is a block diagram which shows the structure of the signal determination part 44B of FIG. It is a figure which shows an example of the data table memorize | stored in the memory 441B. FIG. 26 is a timing chart schematically showing waveforms of optical signals Lsig0_A to Lsig0_E transmitted from the communication devices Adev to Edev in FIG. 25, respectively. It is a timing chart showing typically the output waveform of signal judgment part 44B. It is a block diagram which shows schematic structure of the communication system 4 by Embodiment 4 of this invention. It is a block diagram which shows the structure of the communication apparatus Adev of FIG. 10 is a table showing an example of signal assignment of an input terminal CNCS of a transmitter 503. FIG. 34 is a timing chart schematically showing waveforms of optical signals Lsig0_A to Lsig0_E transmitted from the communication devices Adev to Edev in FIG. 33, respectively. FIG. 37 is an enlarged timing diagram of FIG. 36. It is a block diagram which shows the structure of the matched filter 43B which comprises the de-spreading part 106B. It is a block diagram which shows the structure of the signal determination part 44C of FIG. It is a timing chart showing the output waveform of signal judgment part 44C typically.

Explanation of symbols

  1, 2, 3, 4 communication system, 12 optical / electrical converter, 15 electrical / optical converter, 20 transmission optical path, 37 multiplexed signal generation unit, 41, 41A, 41B spread modulation unit, 43 matched filter, 44, 44A, 44B, 44C Signal determination unit, 101, 101A transmitter, 102, 102A, 102B receiver, 103 multiplexed signal reception unit, 104A AC coupled amplifier, 104 amplifier, 105 baseline regeneration circuit, 106, 106A, 106B Despreading unit 107 Multilevel quantization unit 371 Amplifier 372 Adder unit 375 Clock recovery unit 376 Memory 402 Spread sequence generation unit 403 Comb pulse generation unit 411 Spread sequence generation unit 412 412A Encoding unit 431, 435 Multi-value shift register, 431 (1) to (2n) flip-flop 435 (0) to (10n-5) registers, 432 coefficient unit, 432 (1) to (2n) arithmetic circuit, 433 correlation value arithmetic unit, 433A leading bit detection circuit, 433D, 433E comparator, 433B, 433C, 433F addition circuit, 433G AND circuit, 433H delay circuit, 434 internal clock generation unit, 436 moving addition circuit, 441, 441A memory, 442 serial / parallel conversion unit, 443 reproduction signal discrimination unit, 445, 445A gate signal generation unit, 446, 446B Transmission line monitor, 501, 503 Transmitter, 502, 504 Receiver, 511 Delay circuit, 1051, 1054 Connection node, 1052, 1053 Power supply node, 1055 Ground node, 3751 Comparator, 3752 Pulse shaping circuit, 4031 Timer Path, 4032 gate circuit, Adev to Edev communication device, Ag transmission gain, ALARM alarm output, AND logical product, CAC capacitor, CLK clock signal, CLKCOM comb pulse signal, CNCS, CNCS1, CNCS2 input terminal, CNCR output terminal, D1, D2 diode, Db0 to Dbn-1 data signal, Dtrns data signal, Dcode pulse train (spread modulated data signal), Drecv reproduction data signal (parallel), Drecv0 reproduction data signal (serial), DSCL second threshold (data signal) Fclk0 first bit flag, G0 basic spreading sequence, G0 to Gn-1 spreading sequence, Gate gate signal, K1, K2 threshold, number of Kclk monitor signal data, output of LADD adder circuit 433C , Output of Lcomp comparator 433E, Lsig0, Lsig1 multiplexed (optical) signal, Mcode pulse train (spread modulated monitor signal), Mon1 to Monk monitor signal, Mtrns monitor signal, n sequence length, Na additive noise, Ndat data signal Data number, R despread sequence, R1, R2 resistance element, Srcv0 reception signal (analog), Srcv1 reception signal (quantization), Srec reproduction signal, Ssnd multiplexed signal, Tb bit period, Tb1, Tb2 interval, Tc chip Period, THRL first threshold (for comb pulse regeneration), Tint internal clock pulse, output of UADD adder circuit 433B, output of Ucomp comparator 433D, + VB, -VB bias voltage, potential of VN connection node 1051, Vstd reference voltage , Σmon standard deviation, τ shift amount.

Claims (14)

Comprising a transmitter, said transmitter comprising:
A signal input unit for receiving a plurality of bit signals each corresponding to a plurality of spreading sequences having the same sequence length and having the same bit period;
A comb-shaped pulse generator for outputting a comb-shaped pulse having a number of pulses equal to the sequence length based on a clock signal for each bit period;
For each of the plurality of bit signals received by the signal input unit, according to the bit data of each bit signal, a spreading modulation unit that outputs a corresponding spreading sequence in synchronization with the comb pulse,
A multiplexed signal generation unit that generates and transmits a multiplexed signal by adding the output of the spread modulation unit and the output of the comb pulse generation unit;
A receiver further comprising:
A multiplexed signal receiver for receiving the multiplexed signal;
A clock recovery unit for recovering the comb pulse by determining whether or not a reception signal output from the multiplexed signal reception unit exceeds a preset first threshold;
A despreading unit that calculates and outputs a correlation value between the received signal and each of the plurality of spread sequences in accordance with the timing of the reproduced comb-shaped pulse;
And a first signal determination unit that reproduces the plurality of bit signals by determining whether or not an output of the despreading unit exceeds a preset second threshold value.   The communication system according to claim 1, wherein the plurality of spreading sequences are obtained by cyclically shifting one basic spreading sequence. The interval in which the comb pulse is generated in the bit period is not more than half of the bit period,
The despreading part is
A shift register for storing the received signal by a number twice the sequence length;
The received signal and the plurality of spreading sequences are calculated by calculating a correlation value between two periods of the basic spreading sequence and the received signal stored in the shift register in accordance with the timing of the reproduced comb pulse. The communication system according to claim 2, further comprising: a calculation unit that sequentially obtains a correlation value with each of the two. The computing unit is
A first arithmetic unit that calculates a correlation value between one period of the basic spreading sequence and the received signal stored in the first half of the shift register;
A second arithmetic unit that calculates a correlation value between one period of the basic spreading sequence and the received signal stored in the second half of the shift register;
A correlation value between two periods of the basic spreading sequence and the received signal stored in the shift register is calculated by adding the output of the first arithmetic unit and the output of the second arithmetic unit. And a first adder that outputs
In the despreading unit, the output of the first calculation unit exceeds a preset third threshold value, and the output of the second calculation unit is less than a preset fourth threshold value. A second signal determination unit for determining
The first signal determination unit receives the output of the second signal determination unit, and determines the timing for determining whether the output of the first addition unit exceeds the second threshold value. Item 4. The communication system according to Item 3. The plurality of bit signals include a plurality of monitor signals,
The receiver according to claim 1, further comprising: a transmission path monitoring unit that sets the second threshold according to a correlation value between the received signal and a spread sequence corresponding to each of the plurality of monitor signals. The communication system according to any one of the above.   6. The transmission line monitoring unit according to claim 5, wherein the transmission path monitoring unit reports an abnormality when at least one of an average value and a standard deviation of a plurality of correlation values respectively obtained for the plurality of monitor signals exceeds an allowable range. Communications system. The multiplexed signal generator is
A second addition unit for adding the output of the spread modulation unit and the output of the comb pulse generation unit;
An electrical / optical converter that converts the output of the second addition unit into an optical signal and outputs the optical signal as the multiplexed signal;
The communication system according to claim 1, wherein the multiplexed signal receiving unit includes an optical / electrical converter that converts the received multiplexed signal into an electric signal. The multiplexed signal receiver is
An AC coupled amplifier for amplifying the received multiplexed signal;
A baseline regeneration circuit connected to the output side of the AC-coupled amplifier and returning the potential on the output side of the AC-coupled amplifier to zero potential when there is no input of the multiplexed signal. The communication system according to any one of the above. A communication system including n (n is an integer of 2 or more) transmitters,
Each of the n transmitters is assigned a time slot in a cycle,
Each of the n transmitters includes a signal input unit that receives a plurality of bit signals having the same bit period.
Each of the plurality of bit signals has a sequence length equal to each other and individually corresponds to any one of a plurality of spreading sequences commonly used in the n transmitters,
Each of the n transmitters further includes:
A comb-shaped pulse generator for outputting a comb-shaped pulse having a number of pulses equal to the sequence length based on a clock signal for each bit period;
For each of the plurality of bit signals received by the signal input unit, according to the bit data of each bit signal, a spreading modulation unit that outputs a corresponding spreading sequence in synchronization with the comb pulse,
By adding the output of the spread modulation unit and the output of the comb pulse generation unit, a multiplexed signal is generated for each bit period, and the generated multiplexed signal is transmitted between the assigned time slots. A multiplexed signal generator,
The communication system further comprises a receiver, the receiver comprising:
A multiplexed signal receiver for receiving the multiplexed signal transmitted from each of the n transmitters;
The comb-shaped pulse generated in each of the n transmitters is regenerated by determining whether the received signal output from the multiplexed signal receiving unit exceeds a preset first threshold value. A clock recovery unit;
A despreading unit that calculates and outputs a correlation value between the received signal and each of the plurality of spreading coefficients in accordance with the timing of the comb pulse regenerated by the clock regenerating unit,
A first signal determination unit that reproduces the plurality of bit signals for each of the n transmitters by determining whether an output of the despreading unit exceeds a preset second threshold value. Including a communication system. In each of the n transmitters, the plurality of bit signals are:
One or more first bit signals destined for the receiver;
Including one or more second bit signals destined for other than the receiver,
The receiver further includes a storage unit that stores, for each of the n transmitters, information for identifying a bit signal destined for itself among the plurality of bit signals,
The first signal determination unit further includes, based on the identification information stored in the storage unit, for each of the n transmitters, from the reproduced bit signals, the one or more of the plurality of bit signals. The communication system according to claim 9, wherein the first bit signal is discriminated. In each of the n transmitters, the plurality of bit signals further includes one or more third bit signals that are information indicating a transmitter assigned to a time slot next to its own time slot,
The first signal determination unit determines a next time based on the one or more third bit signals obtained when reproducing the plurality of bit signals for the transmitter assigned to the current time slot. The communication system according to claim 10, wherein the identifying information for the transmitter assigned to the slot is read from the storage unit.   The communication system according to claim 10 or 11, wherein the identification information stored in the storage unit is rewritable in accordance with a change in destination of each of the n transmitters. A communication system including n (n is an integer of 2 or more) transmitters,
Each of the n transmitters is assigned a time slot in a cycle,
Each of the n transmitters includes a signal input unit that receives a plurality of bit signals having the same bit period.
Each of the plurality of bit signals has a sequence length equal to each other, and individually corresponds to any one of a plurality of spreading sequences commonly used in the n transmitters,
Each of the n transmitters further includes:
A comb-shaped pulse generator that outputs, based on a clock signal, a comb-shaped pulse having a number of pulses equal to the sequence length and corresponding to each of the assigned time slots, one for each bit period;
For each of the plurality of bit signals received by the signal input unit, according to the bit data of each bit signal, a spreading modulation unit that outputs a corresponding spreading sequence in synchronization with the comb pulse,
Multiplex signal generation for generating a multiplexed signal for each bit period and transmitting the generated multiplexed signal in a corresponding time slot by adding the output of the spread modulation unit and the output of the comb pulse generation unit Including
The communication system further comprises a receiver, the receiver comprising:
A multiplexed signal receiver for receiving the multiplexed signal transmitted from each of the n transmitters;
By determining whether or not the received signal output from the multiplexed signal receiving unit exceeds a preset first threshold, the comb pulses generated by each of the n transmitters are combined. A clock recovery unit for generating the recovered clock signal,
A despreading unit that calculates and outputs a correlation value between the received signal extracted at the timing of every n pulses of the recovered clock signal and each of the plurality of spreading coefficients;
A first signal determination unit that reproduces the plurality of bit signals of each of the n transmitters by determining whether an output of the despreading unit exceeds a preset second threshold; Including a communication system. In each of the n transmitters, the plurality of bit signals are:
One or more first bit signals destined for the receiver;
Including one or more second bit signals destined for other than the receiver,
The receiver further includes a storage unit that stores, for each of the n transmitters, information for identifying a bit signal destined for itself among the plurality of bit signals,
The first signal determination unit further includes, based on the identification information stored in the storage unit, for each of the n transmitters, from the reproduced bit signals, the one or more of the plurality of bit signals. The communication system according to claim 13, wherein the first bit signal is discriminated.

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