JP4871280B2 - 半導体装置およびその製造方法 - Google Patents
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Description
Claims (13)
- 互いに相対する第1の面と第2の面とを有する基板と、
前記基板の前記第1の面上に配置された第1の半導体チップと、
該第1の半導体チップを封止する第1の封止樹脂部と、
該第1の封止樹脂上に配置された内蔵半導体装置と、
前記基板の前記第1の面と前記第1の半導体チップとを接続する第1のワイヤと、
前記第1のワイヤが接続された前記基板の前記第1の面と前記内蔵半導体装置とを接続する第2のワイヤと、
前記第1の封止樹脂部と前記内蔵半導体装置とを封止し、前記基板の側面を覆う第2の封止樹脂部と、を具備する半導体装置。 - 前記基板の前記第1の半導体チップが配置された前記第1の面と相対する前記第2の面にバンプを有する請求項1記載の半導体装置。
- 前記第1の半導体チップは前記基板と前記第1のワイヤで電気的に接続された請求項1または2記載の半導体装置。
- 前記内蔵半導体装置は、第2の半導体チップを含む請求項1から3のいずれか一項記載の半導体装置。
- 前記内蔵半導体装置は、前記第2の半導体チップを封止する第3の封止樹脂部を有する請求項4に記載の半導体装置。
- 前記内蔵半導体装置上に配置された第3の半導体チップを具備し、
前記第2の封止樹脂部は、前記第1の封止樹脂部、前記内蔵半導体装置および第3の半導体チップを封止し、前記基板の側面を覆う請求項1から5のいずれか一項記載の半導体装置。 - 基板上に、第1の半導体チップを配置する工程と、
該第1の半導体チップを第1の封止樹脂部で封止する工程と、
前記第1の封止樹脂部の間の前記基板を切断する工程と、
前記切断された基板をダミーシート上に配置する工程と、
該第1の封止樹脂部上に配置された内蔵半導体装置を封止し、前記第1の封止樹脂部間のダミーシートを覆う第2の封止樹脂部を形成する工程と、
前記第1の封止樹脂部の間の前記第2の封止樹脂部を切断する工程と、を具備する半導体装置の製造方法。 - 前記第2の封止樹脂部を切断する工程は、前記第2の封止樹脂部が前記切断された基板の側面に残存するように第2の封止樹脂部を切断する工程を含む請求項7記載の半導体装置の製造方法。
- 前記基板の前記第1の半導体チップが配置された面と相対する面にバンプを形成する工程を有する請求項7または8記載の半導体装置の製造方法。
- 前記切断された基板を前記ダミーシート上に配置する工程は、前記バンプが前記ダミーシートに埋没するように、前記切断された基板を配置する工程を含む請求項8記載の半導体装置の製造方法。
- 前記ダミーシートは、前記切断された基板が配置された領域に孔部を有する請求項7から10のいずれか一項記載の半導体装置の製造方法。
- 前記ダミーシートは、前記切断された基板が配置される領域に凹部を有する請求項7から11のいずれか一項記載の半導体装置の製造方法。
- 前記切断された基板を前記ダミーシート上に配置する工程の前に、前記切断された基板に配置された前記第1の半導体チップを電気的に試験する工程を具備する請求項7から12のいずれか一項記載の半導体装置の製造方法。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2005/015694 WO2007026392A1 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2007026392A1 JPWO2007026392A1 (ja) | 2009-03-05 |
| JP4871280B2 true JP4871280B2 (ja) | 2012-02-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007533065A Expired - Lifetime JP4871280B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置およびその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (8) | US7626253B2 (ja) |
| JP (1) | JP4871280B2 (ja) |
| WO (1) | WO2007026392A1 (ja) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4871280B2 (ja) | 2005-08-30 | 2012-02-08 | スパンション エルエルシー | 半導体装置およびその製造方法 |
| JP5301126B2 (ja) * | 2007-08-21 | 2013-09-25 | スパンション エルエルシー | 半導体装置及びその製造方法 |
| US8008787B2 (en) * | 2007-09-18 | 2011-08-30 | Stats Chippac Ltd. | Integrated circuit package system with delamination prevention structure |
| US7956449B2 (en) * | 2008-06-25 | 2011-06-07 | Stats Chippac Ltd. | Stacked integrated circuit package system |
| US8531022B2 (en) * | 2009-03-06 | 2013-09-10 | Atmel Corporation | Routable array metal integrated circuit package |
| US8148813B2 (en) * | 2009-07-31 | 2012-04-03 | Altera Corporation | Integrated circuit package architecture |
| US8455304B2 (en) | 2010-07-30 | 2013-06-04 | Atmel Corporation | Routable array metal integrated circuit package fabricated using partial etching process |
| KR101719636B1 (ko) * | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| KR101800440B1 (ko) | 2011-08-31 | 2017-11-23 | 삼성전자주식회사 | 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법 |
| US8791007B2 (en) | 2011-11-29 | 2014-07-29 | Spansion Llc | Device having multiple wire bonds for a bond area and methods thereof |
| KR20130105175A (ko) * | 2012-03-16 | 2013-09-25 | 삼성전자주식회사 | 보호 층을 갖는 반도체 패키지 및 그 형성 방법 |
| JP2013214611A (ja) * | 2012-04-02 | 2013-10-17 | Elpida Memory Inc | 半導体装置 |
| US9385006B2 (en) * | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
| KR20150056555A (ko) | 2013-01-09 | 2015-05-26 | 샌디스크 세미컨덕터 (상하이) 컴퍼니, 리미티드 | 반도체 다이를 매립 및/또는 이격시키기 위한 독립적인 필름을 포함하는 반도체 디바이스 |
| JP6280014B2 (ja) * | 2014-09-30 | 2018-02-14 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| JP6353763B2 (ja) * | 2014-09-30 | 2018-07-04 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| WO2016159937A1 (en) * | 2015-03-27 | 2016-10-06 | Hewlett-Packard Development Company, L.P. | Circuit package |
| JP2016192447A (ja) * | 2015-03-30 | 2016-11-10 | 株式会社東芝 | 半導体装置 |
| US10001963B2 (en) | 2015-12-01 | 2018-06-19 | Alson Technology Limited | Dynamic random access memory |
| KR20180002939A (ko) | 2016-06-29 | 2018-01-09 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 패키지, 및 그것을 포함하는 메모리 모듈 |
| US10522512B2 (en) * | 2018-05-02 | 2019-12-31 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
| JP2022034947A (ja) * | 2020-08-19 | 2022-03-04 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| JP7640250B2 (ja) * | 2020-11-20 | 2025-03-05 | 日東電工株式会社 | スペーサ付ダイシング接着フィルム |
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| US20110312108A1 (en) | 2011-12-22 |
| US20150255446A1 (en) | 2015-09-10 |
| US9472540B2 (en) | 2016-10-18 |
| US7626253B2 (en) | 2009-12-01 |
| US20180076188A1 (en) | 2018-03-15 |
| US7859096B2 (en) | 2010-12-28 |
| US9837397B2 (en) | 2017-12-05 |
| US20130100318A1 (en) | 2013-04-25 |
| US10347618B2 (en) | 2019-07-09 |
| US20170069614A1 (en) | 2017-03-09 |
| JPWO2007026392A1 (ja) | 2009-03-05 |
| US8330263B2 (en) | 2012-12-11 |
| US9041177B2 (en) | 2015-05-26 |
| US20100102424A1 (en) | 2010-04-29 |
| WO2007026392A1 (ja) | 2007-03-08 |
| US20110309494A1 (en) | 2011-12-22 |
| US8329562B2 (en) | 2012-12-11 |
| US20070045876A1 (en) | 2007-03-01 |
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