JP4872883B2 - Computer, failure reproduction method and program - Google Patents

Description

  The present invention relates to a failure reproduction technique for reproducing a failure in a computer such as a server or a personal computer (PC), and in particular, a failure capable of reproducing a failure even when an operating system (OS) cannot be started due to the failure. Reproduction technology.

  In a computer such as a server or a PC, it has been conventionally performed to reproduce a failure in order to investigate the cause of the failure (see, for example, Patent Document 1). In this Patent Document 1, each time an instruction is executed, the value of the register updated by the instruction is stored in the storage unit. When reproducing an unexpected event (failure or the like), the storage unit The registers (including the program counter) are returned to the state before the occurrence of the failure based on the value of the register stored in the memory, and then the program execution is resumed from the instruction indicated by the program counter.

JP-A-3-158937

  According to the technique described in Patent Document 1, since the execution of the program is resumed after returning the state of the register to the state before the occurrence of the failure, the failure can be reproduced with a high probability. . However, the technique described in Patent Document 1 has a problem that the failure cannot be reproduced when the OS cannot be started due to the failure.

(Object of invention)
Therefore, an object of the present invention is to make it possible to reproduce a failure even when the OS cannot be started due to the failure.

The first computer according to the present invention is:
Each time an instruction is executed in the own computer, the executed instruction is written, and when a failure occurs in the own computer, an instruction string storage unit that prohibits writing of the instruction;
A program generation unit that generates a failure reproduction program including a failure reproduction unit for reproducing the failure based on an instruction stored in the instruction sequence storage unit;
And a boot loader that activates the failure reproduction program generated by the program generation unit.

The first failure reproduction method according to the present invention is:
A first step of writing the executed instruction to the instruction sequence storage unit each time an instruction is executed in the own computer;
A second step of prohibiting writing of instructions to the instruction sequence storage unit when a failure occurs in the own computer;
A third step of generating a failure reproduction program including a failure reproduction unit for reproducing the failure based on an instruction stored in the instruction sequence storage unit;
And a fourth step of starting the failure reproduction program generated in the third step by a boot loader.

The first program according to the present invention is:
A first step of writing the executed instruction to the instruction sequence storage unit in the computer each time the instruction is executed in the computer;
A second step of prohibiting writing of an instruction to the instruction sequence storage unit when a failure occurs in the computer;
A third step of generating, on the computer, a failure reproduction program including a failure reproduction unit for reproducing the failure based on an instruction stored in the instruction sequence storage unit;
Causing the computer to execute a fourth step of starting the fault reproduction program generated in the third step by a boot loader.

  According to the present invention, it is possible to obtain an effect that the failure can be reproduced even when the OS cannot be started due to the failure.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

Examples of the present invention
Referring to FIG. 1, a computer 1 according to an embodiment of the present invention includes a processor 2, a main storage device 3, and a nonvolatile memory 4.

  The processor 2 includes an instruction sequence storage unit 25 in addition to an instruction register 21, a decoder 22, general-purpose registers (also simply referred to as registers) R 1 to RN, an arithmetic circuit 23, and a failure detection circuit 24 provided in a general processor. A data string storage unit 26 and a program generation unit 27 are provided.

  The instruction sequence storage unit 25 includes a writing unit 251 and a storage unit 252 as shown in FIG. The storage unit 252 is realized by an SRAM (static RAM) or the like, and includes N areas # 1 to #N. Each time an instruction is sent from the instruction register 21 to the decoder 22 (each time the instruction is executed), the writing unit 251 writes the instructions in order from the area # 1 of the storage unit 252. When the command is written to the area #N, the writing unit 251 writes the command from the area # 1 again. Accordingly, N latest instructions are stored in the storage unit 252. In addition, when the failure detection circuit 24 detects a failure in the computer 1, the writing unit 251 stops writing the instruction. In FIG. 2, instruction # 3 represents the instruction with the oldest storage order, and instruction # (N + 2) represents the instruction with the newest storage order.

  Similar to the instruction sequence storage unit 25, the data sequence storage unit 26 includes a writing unit and a storage unit including N areas. Each time the instruction is executed, the writing means sequentially stores the related data related to the instruction from the area # 1 of the storage unit according to the decoding result of the decoder 22. Therefore, the area #J (1 ≦ J ≦ N) of the data string storage unit 26 stores related data related to the instructions stored in the area #J of the instruction string storage unit 25. In addition, when the failure detection circuit 24 detects a failure of the computer 1, the writing unit stops writing related data. Here, data (values and update and reference positions) related to all registers and main storage devices to be updated and referred to by the instruction may be written in the data string storage unit 26 as related data. In order to reduce the capacity of the data string storage unit 26, only a part of the data string is written in the data string storage unit 26 as related data. In the present embodiment, in the case of a memory store instruction, the value of the referenced register and the register number are used as related data. In the case of a memory load instruction, the value and address of the referenced main storage device are used. In the case of other instructions, the value of the register to be updated and the register number are used as related data.

  When the failure detection circuit 24 detects a failure of the computer 1, the program generation unit 27 is based on the instruction stored in the instruction sequence storage unit 25 and the related data stored in the data sequence storage unit 26. A failure reproduction program 5 as shown in FIG. 3 is generated and stored in the nonvolatile memory 4. The failure reproduction program 5 reproduces the failure with the state restoration unit 51 that returns the states of the registers R1 to RN and the main storage device 3 to the state at the time of execution of the oldest instruction stored in the instruction sequence storage unit 25. And a failure reproduction unit 52 for the purpose.

  FIG. 4 is a block diagram illustrating a configuration example of the program generation unit 27, which includes a decoder 271, a selector 272, a unique flag storage unit 273, an estimation unit 274, and a selector 275.

  The decoder 271 decodes the instructions stored in the instruction sequence storage unit 25 in order from the oldest storage order, and outputs the decoding result.

  The unique flag storage unit 273 stores unique flags F1 to FN for the registers R1 to RN, respectively. The unique flags F1 to FN indicate whether or not the values of the corresponding registers R1 to RN are uniquely determined at the present time, and “1” is determined when the values are uniquely determined. If not, “0” is set.

  The contents of the unique flag storage unit 273 are rewritten by the selector 272 controlled by the decoding result of the decoder 271. The selector 272 is configured to perform the following operation in accordance with the decoding result of the decoder 271. When the decoding result of the decoder 271 indicates that the value of the related data corresponding to the decoded instruction is the value of the register and the value is uniquely determined before the execution of the instruction, the register The unique flag corresponding to is set to “1”. Further, when the decoding result of the decoder 271 indicates that the value of the related data corresponding to the decoded instruction is the value of the register and the value is uniquely determined by the instruction, it corresponds to the register. The unique flag is set to “0”.

  For example, when the instruction decoded by the decoder 271 is a memory store instruction, the value of the related data corresponding to the memory store instruction is the value of the store source register, and the value of the store source register is the memory store instruction. Since it is uniquely determined before the instruction is executed, the unique flag corresponding to the register at the store source is set to “1”. Also, for example, when the decoded instruction is an addition instruction, the value of the related data corresponding to the addition instruction is the value of the register to be updated by the addition instruction, and the value of this register is the addition instruction. Therefore, the unique flag corresponding to the register to be updated is set to “0”.

  The estimation unit 274 has the following functions.

Among the values of the registers or main memory that are updated or referred to by the instruction decoded by the decoder 271, those values stored as related data in the data string storage unit 26 are stored in the register or main memory. An instruction to be written back to the storage device is generated, and the generated instruction is stored in the nonvolatile memory 4.
-For values of registers or main memory that are updated or referred to by instructions decoded by the decoder 271, those values that are not stored as related data in the data string storage unit are estimated and estimated. A command for writing the value back to the register or the main memory is generated and stored in the nonvolatile memory 4. When the unique flag of the register that is updated or referred to by the decoded instruction is “1”, the value has already been determined, so that an instruction to write back the estimated value is not generated. If the value of another register that is updated or referred to is uniquely determined by reading the value of the register having the unique flag “1” from the nonvolatile memory 4, the unique flag of the corresponding register is set to “ As 1 ″, an instruction for writing back a uniquely determined value is generated.

  More specifically, the estimation unit 274 is provided with an estimation circuit (not shown) corresponding to the instruction type, and an estimation circuit corresponding to the instruction type decoded by the decoder 271 is used as the instruction type. Perform appropriate processing. For example, a configuration for generating an instruction to write a value back to a register to be updated based on related data read from the data string storage unit 26 and storing the instruction in the non-volatile memory 4 in the estimation circuit for the addition instruction; A configuration in which an instruction to write 0 to one register referred to by an addition instruction is generated and stored in the nonvolatile memory 4, and the other register being referred to is indicated by related data read from the data string storage unit 26. What is necessary is just to have the structure which produces | generates the command which writes a value and stores it in the non-volatile memory 4. FIG. Note that the configuration of the addition circuit is not limited to this, and may be configured using a random number generator. That is, the value of one register referred to by the addition instruction is determined using a random number generator, and the value of the other register is determined from the value determined using the random number generator and the value indicated by the related data. Anyway.

  In the present embodiment, the program generation unit 27 is realized by hardware (wiring logic), but can also be realized by a computer. In this case, a disk, a semiconductor memory, or other recording medium on which a program for causing the computer to function as the program generation unit 27 is prepared is prepared, and the computer reads the program. The computer implements the program generation unit 27 on its own computer by controlling its own operation according to the read program.

[Description of Operation of Example]
Next, the operation of this embodiment will be described in detail.

  When the computer 1 is operating normally, each time an instruction is executed in the computer 1, the executed instruction is written into the storage unit 252 of the instruction sequence storage unit 25, and related data related to the instruction is stored. The data is stored in the storage unit of the data string storage unit 26. When the failure detection circuit 24 detects a failure in the computer 1, the instruction sequence storage unit 25 stops writing instructions. The data string storage unit 26 writes the related data corresponding to the last written instruction in the instruction string storage unit 25 and then stops writing.

  When a failure occurs in the computer 1 and the instruction sequence storage unit 25 and the data sequence storage unit 26 stop writing instructions and related data, the program generation unit 27 starts the processing shown in the flowchart of FIG.

  First, the program generation unit 27 initializes all the unique flags F1 to FN stored in the unique flag storage unit 273 to “0” (S501 in FIG. 5). After that, the instruction and storage data with the last storage order (execution order) and related data are read from the instruction string storage unit 25 and the data string storage unit 26, respectively (S502), and the value indicated by the related data is a register or memory address indicated by the related data A command to be written to the (main storage device 3) is generated and stored in the nonvolatile memory 4 (S503).

  Thereafter, it is checked whether or not the related data read this time from the data string storage unit 26 indicates the value of the register, and whether the value is uniquely determined before the execution of the instruction read this time from the instruction string storage unit 25. (S504). If the instruction read this time is an instruction uniquely determined as a memory store instruction, the unique flag of the corresponding register is set to “1” (S505). On the other hand, if it is not uniquely determined as in the addition instruction, the unique flag of the corresponding register is set to “0” (S506).

  After that, among the values of the registers or main memory 3 that are updated or referred to by the instruction read this time from the instruction sequence storage unit 25 and whose values are not indicated by the related data read this time, the value is estimated. (S507).

  Then, when the estimation target is the main storage device 3 (No in S508), an instruction to write the estimated value to the corresponding memory address (which can be understood from the instruction) is generated, and the generated instruction is stored in the nonvolatile memory 4. (S509). After that, the previous instruction and related data are read from the instruction sequence storage unit 25 and the data sequence storage unit 26, respectively (S514).

  On the other hand, when the estimation target is a register (S508 is Yes), the unique flags of all the registers that are the estimation target are checked (S510). If all the unique flags are “1” (Yes in S510), all the register values to be estimated are determined at the present time. Therefore, an instruction to write the estimated value is not generated. The previous instruction and related data are read from the instruction sequence storage unit 25 and the data sequence storage unit 26, respectively (S514).

  On the other hand, the unique flag is “0” when one of the unique flags of the register to be estimated includes a value of “0” (No in S510). It is determined whether or not the value of the register can be uniquely determined by the value of the register whose unique flag is “1” and the value of the register or main memory indicated by the related data read this time (S511). ).

  If it is determined that the value can be uniquely determined (Yes in S511), the unique flag of the register whose value is determined to be uniquely determined is rewritten to “1”, and the uniquely determined value is written to the register. And the generated instruction is stored in the nonvolatile memory 4 (S512).

  On the other hand, when it is determined that it cannot be uniquely determined (No in S511), an instruction to write the value estimated in Step S507 to the corresponding register is generated and stored in the nonvolatile memory 4 (Step S513).

  When the process of step S512 or step S513 is completed, the previous instruction and related data are read out from the instruction string storage unit 25 and the data string storage unit 26, respectively (S514). Thereafter, the processing of steps S503 to S514 is repeated to generate the state restoration unit 51 of the failure reproduction program 5. Then, the processes in steps S503 to S514 are performed on all the instructions and related data stored in the instruction sequence storage unit 25 and the data sequence storage unit 26, and when there is no previous instruction in the storage order (Yes in step S515). ) Since the state restoration unit 51 of the failure reproduction program 5 is completed, the process of the flowchart of FIG. 6 is performed in order to generate the failure reproduction unit 52 this time.

  Referring to FIG. 6, the program generation unit 27 first reads the instruction with the earliest execution order from the instructions stored in the instruction sequence storage unit 25 (S601) and stores it in the nonvolatile memory 4 (S602). ). Thereafter, the program generation unit 27 repeatedly performs processing (S603, S602) of fetching the next instruction in the execution order from the instruction sequence storage unit 25 and writing the instruction to the nonvolatile memory 4, and stores the instruction in the instruction sequence storage unit 25. When the last instruction in the executed execution order is taken out and there is no next instruction (Yes in S604), the failure reproduction unit 52 of the failure reproduction program 5 is completed, and thus the process is terminated.

  Next, with reference to FIG. 7 and FIG. 8, the operation in the case of reproducing a fault using the fault reproduction program 5 stored in the nonvolatile memory 4 will be described.

  First, the failure reproduction program 5 stored in the nonvolatile memory 4 is written in the external storage device 6 such as a flexible disk as a boot image (S701 in FIG. 7 and S801 in FIG. 8). In FIG. 8, the failure reproduction program written in the boot image is represented as the failure reproduction program 5a. Then, the boot loader 7 for reading the failure reproduction program 5a is created on the external storage device 6 (S702 in FIG. 7 and S802 in FIG. 8). Alternatively, the boot loader 7 may be created on the external storage device 6 in advance, and the failure reproduction program 5 may be written as a boot image in the external storage device 6 that has been created by the boot loader 7.

  Thereafter, the external storage device 6 is connected to the computer 1 (S703 in FIG. 7, 803 in FIG. 8), and the computer 1 is restarted (704 in FIG. 7, 804 in FIG. 8). It is assumed that the external storage device 6 is the highest priority device among the devices that can be used for booting.

  Thereby, the computer 1 reads and executes the boot loader 7 from the external storage device 6 having the highest priority, and further reads and executes the failure reproduction program 5a by this boot loader 7 (S705 in FIG. 7 and S805 in FIG. 8). , S806).

  When the fault reproduction program 5a is executed, first, the state restoration unit 51 causes the registers R1 to RN of the computer 1 and the state of the main storage device 3 to be executed when the oldest instruction stored in the instruction sequence storage unit 25 is executed. After that, the failure reproduction unit 52 reproduces the failure.

  In the above description, the failure reproduction program 5 stored in the nonvolatile memory 4 is once written as a boot image in the external storage device 6 and the boot loader 7 is created on the external storage device 6. A boot loader 7 is created on the non-volatile memory 4 in which the program 5 is stored, and when the computer 1 is restarted, the boot loader 7 stored in the non-volatile memory 4 is read. The reproduction program 5 may be read and executed.

[Specific Examples]
Next, the operation of the program generation unit 27 will be described with a specific example. For example, assume that the contents of the instruction string storage unit 25 and the data string storage unit 26 are as shown in FIG. In FIG. 9, R * represents a register, and Mem [x] represents the address x of the main storage device 3. Orders 1 to 6 indicate the execution order of instructions, and instructions having a smaller number indicating the execution order are instructions having the previous execution order.

  In order to generate the state restoration unit 51 of the failure reproduction program 5, the program generation unit 27 executes the instructions stored in the instruction sequence storage unit 25 and the data sequence storage unit 26 and the related data with the instructions in the later execution order (execution) Instructions with the highest order number) are read in order, and the following processing is performed.

Operation when order 6 instruction (branch instruction) and related data are read In step S503, based on the related data “R1 = 0”, an instruction to write 0 to the register R1 is generated, and the generated instruction is nonvolatile. Store in memory 4. In step S507, it is estimated that R5 = 101 from the branch condition. In step S513, an instruction to write the estimated value “101” in the register R5 is generated and stored in the nonvolatile memory 4.

Operation when order 5 instruction (OR instruction) and related data are read In step S503, an instruction to write 4 to the register R3 is generated based on the related data “R3 = 4”, and the generated instruction is nonvolatile. Store in memory 4. In step S507, it is estimated that R4 = 4 and R6 = 0 based on the right side of the OR instruction. In step S513, an instruction to write 4 to the register R4 and an instruction to write 0 to the register R6 are generated, and these are nonvolatile. Stored in the memory 4.

Operation when order 4 instruction (left 2 shift instruction) and related data are read In step S503, an instruction to write 4 to the register R4 is generated based on the related data “R4 = 4”. Store in the nonvolatile memory 4. In step S507, it is estimated that R3 = 1 from the right side of the shift instruction, and in step S513, an instruction to write 1 to the register R3 is generated and stored in the nonvolatile memory 4.

Operation in the case of reading an instruction of order 3 (memory load instruction) and related data In step S503, an instruction to write 1 to address 2000 of the main storage device 3 based on the related data “Mem [2000] = 1”. It is generated and stored in the nonvolatile memory 4. In step S507, the value to be written to the load destination register R3 is estimated to be 1, and an instruction to write 1 to the register R3 is generated and stored in the nonvolatile memory 4 in step S513.

Operation when reading order 2 instruction (memory store instruction) and related data In step S503, based on related data “R2 = 20”, an instruction to write 20 to register R2 is generated, and the generated instruction is nonvolatile. Stored in the memory 4. In step S504, the related data corresponding to the memory store instruction indicates the value of the register R2, and it is determined that the value is uniquely determined before the execution of the memory store instruction. Therefore, in step S505, The unique flag F2 corresponding to the register R2 is set to “1”. In step S507, the value of Mem [1000] is estimated to be 20. In step S513, an instruction to write 20 to Mem [1000] is generated and stored in the nonvolatile memory 4.

-Operation when reading an instruction of order 1 (addition instruction) and related data In step S503, an instruction to write 100 to the register R1 is generated based on the related data “R1 = 100”, and the generated instruction is nonvolatile. Store in memory 4. In step S507, the values of the registers R2 and R3 are estimated to be 0 and 100, for example (this estimated value is not used as will be described later). In step S511, since it is determined that the value of the register R3 to be estimated can be uniquely determined by the value of the register R2 whose unique flag is “1”, the value is indicated by the related data “R1 = 100” in step S512. The register R1 value 100 and the register R2 value “20” with the unique flag “1” are determined to uniquely determine the value of the register R3 as “80”, and an instruction to write 80 to the register R3 is generated. And stored in the nonvolatile memory 4. In step S512, the unique flag F3 corresponding to the register R3 is also set to “1”. Note that the value “20” of the register R2 can be obtained from an instruction stored in the nonvolatile memory 4 and having the newest writing order among the writing instructions to the register R2.

  With the above processing, the state restoration unit 51 of the failure reproduction program 5 is generated.

  Thereafter, the program generation unit 27 generates the failure reproduction unit 52 of the failure reproduction program 5, and therefore the instructions (instructions 1 to 6) stored in the instruction sequence storage unit 25 have a small number indicating the execution order. The data are stored in the non-volatile memory 4 in order from the one (see FIG. 6). As a result, the failure reproduction unit 52 that executes sequentially from the instruction having the oldest execution order is completed.

[Effects of Examples]
According to the present embodiment, it is possible to obtain an effect that the failure can be reproduced even when the OS cannot be started due to the failure. This is because the boot loader 7 for starting the failure reproduction program 5 generated by the program generation unit 27 is provided.

  In the present embodiment, the program generation unit 27 includes the failure reproduction program 5 including the registers R1 to RN of the own computer 1 and the state restoration unit 51 for returning the state of the main storage device 3 to the state before the failure occurred. Therefore, by executing the failure reproduction program 5, the states of the registers R1 to RN and the main storage device 3 can be returned to the state before the failure occurred. As a result, it is possible to reproduce a failure depending on a pattern change such as a crosstalk error between signal lines with a high probability.

  Further, in this embodiment, in order to return the state of the register of the computer 1 that performs irreversible operation and the state of the main memory to the state before the occurrence of the failure, the register and the main that are updated and referred to by the instruction executed in the own computer 1 A part of the data related to the storage device is written in the data string storage unit 26 as related data, and the remaining data is estimated from the related data and the corresponding instruction. Can be reduced.

  Further, in the present embodiment, when the write destination of the instruction to write the estimated data is a register indicating that the value is uniquely determined by the unique flag, the instruction is stored in the nonvolatile memory 4. Since they are not stored, the states of the registers R1 to RN and the main storage device 3 can be accurately restored.

  The present invention can be used to investigate the cause of failures in various computers such as servers and PCs.

It is a block diagram of the Example of the computer 1 concerning this invention. 4 is a diagram for explaining an instruction sequence storage unit 25. FIG. It is a figure which shows the structural example of the failure reproduction program 5. FIG. 3 is a block diagram illustrating a configuration example of a program generation unit 27. FIG. 10 is a flowchart illustrating a processing example when the program generation unit 27 generates a state restoration unit 51 of the failure reproduction program 5. 7 is a flowchart illustrating a processing example when the program generation unit 27 generates a failure reproduction unit 52 of the failure reproduction program 5. 7 is a flowchart showing an operation when a failure is reproduced using the failure reproduction program 5. It is a figure for demonstrating the operation | movement in the case of reproducing a failure using the failure reproduction program 5. It is a figure which shows the example of the content of the instruction sequence memory | storage part 25 and the data sequence memory | storage part 26. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Computer 2 ... Processor 21 ... Instruction register 22 ... Decoder 23 ... Operation circuit 24 ... Fault detection circuit 25 ... Instruction sequence memory | storage part 251 ... Writing means 252 ... Memory | storage part 26 ... Data sequence memory | storage part 27 ... Program generation part R1-RN ... Register 271 ... Decoder 272 ... Selector 273 ... Unique flag storage unit 274 ... Inference unit 275 ... Selector 3 ... Main storage device 4 ... Non-volatile memory 5, 5a ... Failure reproduction program 51 ... State restoration unit 52 ... Failure reproduction unit 6 ... External storage device 7 ... boot loader

Claims (12)

Each time an instruction is executed in the own computer, the executed instruction is written, and when a failure occurs in the own computer, an instruction string storage unit that prohibits writing of the instruction;
A program generation unit that generates a failure reproduction program including a failure reproduction unit for reproducing the failure based on an instruction stored in the instruction sequence storage unit;
A computer comprising: a boot loader that activates the fault reproduction program generated by the program generation unit. The computer according to claim 1, wherein
Each time an instruction is executed in the own computer, related data related to the executed instruction is written, and when a failure occurs in the own computer, a data string storage unit is provided to prohibit writing of the related data, and
The failure reproduction program includes, in addition to the failure reproduction unit, a state restoration unit for returning the state of the register of the own computer and the main storage device to the state before the occurrence of the failure,
The computer, wherein the program generation unit generates the state restoration unit based on related data stored in the data string storage unit. The computer according to claim 1 or 2,
The computer according to claim 1, wherein the fault reproduction unit is configured by arranging instructions stored in the instruction sequence storage unit in order from the oldest execution order. The computer according to claim 2 or 3,
The data string storage unit is data related to a register and a main storage device that are updated and referred to by an instruction executed by the own computer, and includes data that is updated and referred to, and an update and reference position. Part of the data is stored as related data,
The program generation unit is updated by an instruction stored in the instruction sequence storage unit based on an instruction stored in the instruction sequence storage unit and related data stored in the data sequence storage unit. Of the registers and main storage devices to be referred to, those for which the value can be specified by the related data stored in the data string storage unit generate a write-back instruction to write back the value and cannot be specified For the above, a write-back instruction for estimating the value and writing back the estimated data is generated, and the generated write-back instruction is arranged in the state restoration unit in order from the instruction corresponding to the instruction having the oldest execution order. A computer characterized by The computer according to claim 4, wherein
It has a unique flag for each register that displays whether the value of the register is uniquely determined,
When the program generation unit is a register in which the write-back destination of the write-back instruction to write back the estimated value is a register that indicates that the value is uniquely determined by a unique flag, the write-back instruction is A computer that is not arranged in the state restoration unit. A first step of writing the executed instruction to the instruction sequence storage unit each time an instruction is executed in the own computer;
A second step of prohibiting writing of instructions to the instruction sequence storage unit when a failure occurs in the own computer;
A third step of generating a failure reproduction program including a failure reproduction unit for reproducing the failure based on an instruction stored in the instruction sequence storage unit;
And a fourth step of starting the fault reproduction program generated in the third step by a boot loader. The failure reproduction method according to claim 6,
A fifth step of writing related data relating to the executed instruction to the data string storage unit each time the instruction is executed in the own computer;
And a sixth step for prohibiting writing of related data to the data string storage unit when a failure occurs in the own computer, and
The failure reproduction program includes, in addition to the failure reproduction unit, a state restoration unit for returning the state of the register of the own computer and the main storage device to the state before the occurrence of the failure,
The failure reproduction method, wherein the third step generates the state restoration unit based on related data stored in the data string storage unit. The failure reproduction method according to claim 6 or 7,
The failure reproduction method is configured by arranging the instructions stored in the instruction string storage unit in order from the oldest execution order. The failure reproduction method according to claim 7 or 8,
In the fifth step, data relating to a register and a main storage device that are updated and referred to by an instruction executed by the own computer, including data that is updated and referred to, and an update and reference position Part of the data is stored as related data,
In the third step, updating is performed by an instruction stored in the instruction sequence storage unit based on an instruction stored in the instruction sequence storage unit and related data stored in the data sequence storage unit Among the registers and main storage devices to be referred to, those for which the value can be specified by the related data stored in the data string storage unit generate a write-back instruction to write back the value, and cannot be specified For a thing, a write-back instruction for writing back the estimated data by guessing its value is generated, and the generated write-back instruction is arranged in the state restoration unit in order from the instruction corresponding to the instruction whose execution order is old. The failure reproduction method characterized by this. The failure reproduction method according to claim 9,
The calculator includes a unique flag for each register that displays whether the value of the register is uniquely determined,
In the third step, when the write back destination of the write back instruction to write back the estimated value is a register indicating that the value is uniquely determined by the unique flag, the write back instruction is A failure reproduction method characterized by not being arranged in the state restoration unit. A first step of writing the executed instruction to the instruction sequence storage unit in the computer each time the instruction is executed in the computer;
A second step of prohibiting writing of an instruction to the instruction sequence storage unit when a failure occurs in the computer;
A third step of generating, on the computer, a failure reproduction program including a failure reproduction unit for reproducing the failure based on an instruction stored in the instruction sequence storage unit;
A program for causing the computer to execute a fourth step of starting the fault reproduction program generated in the third step by a boot loader. The program according to claim 11, wherein
A fifth step of writing relevant data relating to the executed instruction to the data string storage unit each time an instruction is executed in the computer;
Causing the computer to execute a sixth step of prohibiting writing of related data to the data string storage unit when a failure occurs in the computer; and
The failure reproduction program includes, in addition to the failure reproduction unit, a state restoration unit for returning the state of the register of the own computer and the main storage device to the state before the occurrence of the failure,
The program in which the third step generates the state restoration unit based on related data stored in the data string storage unit.

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