JP4873387B2 - Gain control method - Google Patents

Description

The present invention relates to a gain control method for keeping the output of an AGC (Auto Gain Control) amplifier used in a receiving circuit such as a radio timepiece constant.

  Conventionally, a time signal used for a radio timepiece or the like is formed by amplifying a standard radio signal received by an antenna, detecting it, and binarizing it with a predetermined reference voltage. For this reason, in the radio clock receiver circuit, an AGC amplifier composed of an amplifier circuit and a Post amplifier composed of an amplifier circuit are arranged before the detection circuit. Furthermore, in order to accurately extract a signal having a frequency tuned to a radio wave signal (for example, a frequency of 40 kHz transmitted from the Fukushima transmitting station and a frequency of 60 kHz transmitted from the Saga transmitting station in Japan), an AGC amplifier and Post In general, a crystal filter is inserted between the amplifier.

The AGC amplifier used in such a receiving circuit or the like is activated by an activation circuit constituted by the gain control circuits 101 to 108 and 114 shown in FIG.
Time until the voltage at the gain setting terminal (hereinafter referred to as AGC terminal) converges to a constant value when power is turned on or when standby is resumed (when the PON (chip enable) terminal changes from high (H) to low (L)). Is time a + time b shown in FIG. Time a is the time until the circuit 2 that discharges from the capacitor 113 of the AGC terminal 112 biased to the power source 109 until the comparator 2 is inverted is cut off. Time b is a time for discharging the capacitance of the AGC terminal in the circuit 1 until the comparator 1 is inverted. The circuit 2 performs only one operation after the PON terminal changes from high to low, and does not perform more than twice.
The circuit 1 includes an n-type MOSFET 111 and a comparator 110 whose output terminal is connected to the gate of the n-type MOSFET 111. The peak detection voltage of the output of the AGC amplifier is input to the non-inverting input terminal of the comparator 110 and is inverted. A target output voltage is input to the input terminal.

  The circuit 2 includes logic circuits 101 to 106, a comparator 107, and an n-type MOSFET 108. The logic circuits 101-103 are NOT circuits, and the logic circuits 104-106 are NAND circuits. The drain of the n-type MOSFET 108 is connected to the AGC terminal, the source is grounded, and the gate is connected to the output terminal of the NAND circuit 106. The first input terminal of the NAND circuit 106 is connected to the output terminal of the NAND circuit 104, and the second input terminal is connected to the output terminal of the comparator 107. The first input terminal of the NAND circuit 104 is connected to the output terminal of the NOT circuit 103, and the second input terminal is connected to the output terminal of the NAND circuit 105. The first input terminal of the NAND circuit 105 is connected to the output terminal of the NAND circuit 104, and the second input terminal is connected to the output terminal of the comparator 107. The input terminal of the NOT circuit 103 is connected to the output terminal of the NOT circuit 102, and the input terminal of the NOT circuit 102 is connected to the output terminal of the NOT circuit 101. The input terminal of the NOT circuit 101 is connected to a PON terminal to which a voltage for starting the starting circuit is applied. The comparator 107 has an output terminal connected to the second input terminal of the NAND circuit 105, a voltage of the AGC terminal is input to the non-inverting input terminal, and an AGC amplifier gain maximum setting voltage is input to the inverting input terminal. Yes.

  A p-type MOSFET 114 is connected between the power supply and the AGC terminal, and the gate is connected to the output terminal of the NOT circuit 101. Before the power is turned on and during standby, the control signal input to the PON terminal is high, the p-type MOSFET 114 is turned on, and the capacitor 113 of the AGC terminal 112 is charged. At the time of power-on and return from standby, the control signal input to the PON terminal becomes low, the p-type MOSFET 114 is turned off, and the AGC terminal voltage input to the comparator 107 from the capacitor 113 of the AGC terminal is the maximum AGC amplifier gain. The battery is discharged until the voltage falls below the set voltage and the comparator 107 is inverted. After the comparator 107 is inverted, the circuit 2 is cut off. The circuit 2 performs only one operation and does not perform it more than once. The circuit 1 is discharged until the peak detection voltage of the AGC amplifier output input to the comparator 110 becomes the same potential as the target output voltage and the comparator 110 is inverted. After the comparator 110 is inverted, the circuit 1 is cut off.

Patent Document 1 discloses an automatic gain control circuit that can achieve both AGC tracking speed and waveform distortion of an output signal. The present invention can be applied to signals that have been subjected to AM modulation, such as a television luminance signal and a radio clock broadcast signal, and can perform automatic gain control with small distortion of the output signal even when the input signal changes greatly. A gain control circuit that changes the magnitude of the input signal according to the gain control signal, a first comparator that performs level comparison between the first reference voltage and the output signal of the gain control circuit, and the output of the gain control circuit A level detection circuit for detecting the level of the signal, a second comparator for comparing the level of the second reference voltage and the output signal of the level detection circuit, and integrating the output signals of the first and second comparators And an integrating circuit.
JP 2004-274330 A

  According to the prior art shown in FIGS. 4 and 5, in a receiving circuit having an AGC amplifier, when returning from standby or when turning on the power, the AGC amplifier output is the optimum voltage for an input signal having a certain amplitude. It takes time to converge. In particular, when the time constant increases due to process variations, temperature, and power supply voltage fluctuations, there is a problem in that the startup time becomes longer and the receiving circuit is operating during that time, so that power is consumed. For example, when the receiving circuit is in a low temperature state, the power supply voltage (VDD) is low, or when the current varies toward a smaller one, the discharge time becomes longer (time b). On the other hand, when the current is increased, the operation of the AGC amplifier becomes unstable.

The present invention has been made to solve such problems, and even when there is a process variation, temperature, or power supply voltage fluctuation when returning from standby or turning on the power, an input signal having a certain amplitude is provided. On the other hand, the present invention provides a gain control method for an AGC amplifier so that the output of the AGC amplifier converges to an optimum voltage in a short time.

The gain control method of the present invention is a gain control method for converging a voltage of a gain setting terminal of a gain adjustable AGC amplifier that amplifies a radio wave reception signal incorporated in a receiving circuit to a constant value. A first step of setting a target gain setting voltage lower than a given gain maximum setting voltage, and starting with application of a start signal, the voltage of the gain setting terminal matches the first setting voltage lower than the target gain setting voltage Until the second step of charging the gain setting terminal with a first current, and after the first step, the peak detection voltage of the output of the AGC amplifier is set to a second setting voltage exceeding the target gain setting voltage. A third step of charging the gain setting terminal with a second current that is smaller than the first current until they match, and after the second step, the peak detection voltage is It is characterized by comprising a fourth step of discharging the voltage of the gain setting terminal to match the target gain setting voltage.
The gain control circuit used in the gain control method of the present invention is a gain control circuit that adjusts the gain in order to keep the detection output of the received signal constant. The gain control circuit has a first comparator and is biased to the ground potential. A first circuit for charging the terminal capacitance until the first comparator is inverted; and a second comparator; until the second comparator is inverted after the first comparator is inverted. A start circuit having a second circuit for charging the capacitance of the gain setting terminal; and a third comparator, and the gain setting until the third comparator is inverted after the second comparator is inverted. And a third circuit for discharging the terminal capacitance.

  The first circuit has a gate connected to the output terminal of the first comparator, a source connected to a first current source connected to a power supply, and a drain connected to the gain setting terminal. The output of the first comparator controls the first p-type MOSFET, the gate of the second circuit is connected to the output terminal of the second comparator, A second p-type MOSFET having a source connected to a second current source connected to the power source for supplying a smaller current than the first current source and a drain connected to the gain setting terminal; The output of the second comparator controls the second p-type MOSFET, and the third circuit is connected to the power source and charges a capacitance of the gain setting terminal; Connected to a third current source to discharge the capacitance of the gain setting terminal A fourth current source; an n-type MOSFET having a gate connected to the output terminal of the third comparator, a drain connected to the fourth current source, and a source grounded; The output of the comparator may control the n-type MOSFET.

  In the first circuit, the voltage of the gain setting terminal is input to the non-inverting input terminal of the first comparator, the first setting voltage is input to the inverting input terminal, and the voltage of the gain setting terminal is the first voltage. The gain setting terminal continues to be charged until the first comparator inverts in accordance with one set voltage, and the second circuit outputs the detection output to the non-inverting input terminal of the second comparator. A voltage is input, a second setting voltage is input to the inverting input terminal, and the capacitance of the gain setting terminal is charged until the detection output voltage matches the second setting voltage and the second comparator is inverted. Subsequently, in the third circuit, the detection output voltage is input to the non-inverting input terminal of the third comparator, the target output voltage is input to the inverting input terminal, and the detection output voltage is set to the target output voltage. Until the third comparator inverts in agreement. It may be continue the discharge of the capacity of setting pin.

  In the present invention, the output circuit of the AGC amplifier can be converged in a short time in a sufficiently short time by operating the starting circuit even when there are variations in process, temperature, and power supply voltage. Less power is consumed.

  Hereinafter, embodiments of the invention will be described with reference to examples.

First, an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a circuit diagram showing a gain control circuit of the AGC amplifier of this embodiment, FIG. 2 is a characteristic diagram for explaining temporal changes in the AGC amplifier gain setting voltage and the peak detection voltage of the AGC amplifier output, and FIG. FIG. 3 is a circuit diagram of a receiving circuit in which this AGC amplifier is used.
As shown in FIG. 3, a time signal used for a radio timepiece or the like is formed by amplifying a signal received by an antenna 22, detecting it, and binarizing it with a predetermined reference voltage. For this reason, the radio-controlled timepiece receiving circuit 21 is provided with an AGC amplifier 23 including an amplifier circuit and a Post amplifier 24 including an amplifier circuit before the detection circuit. In the receiving circuit 21, the radio wave having a frequency of 40 kHz or 60 kHz received by the antenna 22 is converted into a voltage signal at the antenna end and amplified by the AGC amplifier 23. The amplified signal is filtered to remove noise. An external crystal filter 26 is used for filtering.

  The crystal filter 26 used in this embodiment is composed of three crystal filters connected in parallel, and filters signals having frequencies of 40 kHz, 60 kHz, and 77.5 kHz, respectively. Each crystal filter is provided with a switch 28, and is configured to select a desired signal frequency by switching the switch 28. The crystal filter 26 is connected between the positive phase output terminal of the AGC amplifier 23 and the input terminal of the Post amplifier 24. The signal filtered by the crystal filter 26 is amplified by the Post amplifier 24. The amplified signal is rectified by the rectifier 27, and then the frequency component (40 to 77.5 kHz) of the carrier wave is cut by the low-pass filter (LPF) 29 and smoothed. The rectified and smoothed signal is compared with a predetermined reference voltage in the comparator 20, binarized, and output. A time signal is formed from the binarized signal.

The gain control circuit shown in FIG. 1 is a circuit that quickly converges an input voltage whose magnitude changes to a constant output voltage when an AGC amplifier incorporated in a receiving circuit is started.
The gain control circuit has a first circuit having a first comparator 7 until the first comparator 7 inverts the capacitor 13 of the AGC terminal 12 biased to the ground potential. Charge. After the inversion of the first comparator 7, the first circuit is cut off. As a result, the voltage at the AGC terminal rises from 0 V to voltage V1 (see FIG. 2). The first circuit has a first p-type MOSFET 8. The first p-type MOSFET 8 has a gate connected to the output terminal of the first comparator 7, a source connected to the first current source connected to the power supply, and a drain connected to the AGC terminal. The output of the first comparator 7 controls on / off of the first p-type MOSFET 8. In the first comparator 7, the voltage of the AGC terminal is input to the non-inverting input terminal, the voltage not exceeding the maximum gain setting voltage of the AGC amplifier (hereinafter referred to as the first setting voltage) is input to the inverting input terminal, and the AGC terminal Charging of the capacitor connected to the AGC terminal is continued until the first comparator 7 inverts when the first voltage coincides with the first set voltage.

  The first p-type MOSFET 8 is controlled by the logic circuit 1-6 and the first comparator 7 included in the first circuit. That is, the first circuit includes a first p-type MOSFET 8, a logic circuit 1-6 that controls the first p-type MOSFET 8, and a first comparator 7. The logic circuit 1-3 is a NOT circuit, and the logic circuit 4-6 is a NAND circuit. The gate of the p-type MOSFET 8 is connected to the output terminal of the NAND circuit 6. The first input terminal of the NAND circuit 6 is connected to the output terminal of the NAND circuit 4, and the second input terminal is connected to the output terminal of the first comparator 7. The first input terminal of the NAND circuit 4 is connected to the output terminal of the NOT circuit 3, and the second input terminal is connected to the output terminal of the NAND circuit 5. The first input terminal of the NAND circuit 5 is connected to the output terminal of the NAND circuit 4, and the second input terminal of the NAND circuit 5 is connected to the output terminal of the first comparator 7. The input terminal of the NOT circuit 3 is connected to the output terminal of the NOT circuit 2, and the input terminal of the NOT circuit 2 is connected to the output terminal of the NOT circuit 1. The input terminal of the NOT circuit 1 is connected to a PON terminal to which a voltage for starting the gain control circuit is applied.

  After the first circuit increases the AGC terminal voltage, that is, after the capacitor 13 of the AGC terminal 12 biased to the ground potential (VSS) is charged until the first comparator 7 is inverted, the first circuit The time until it expires is time c (see FIG. 2). After the inversion of the first comparator 7, the first circuit is cut off.

  The gain control circuit has a second circuit including a second comparator 16. The second circuit charges the capacitor connected to the AGC terminal until the second comparator 16 is inverted after the first comparator 7 is inverted. The second circuit includes a second p-type MOSFET 15. The second p-type MOSFET 15 has a gate connected to the output terminal of the second comparator 16, a source connected to a second current source that supplies a smaller current than the first current source, and a drain connected to the AGC terminal. It is connected. The output of the second comparator 16 controls on / off of the second p-type MOSFET 15. A peak detection voltage of the AGC amplifier output is input to the non-inverting input terminal of the second comparator 16, and a voltage equal to or higher than the target output voltage (hereinafter, a second set voltage) is input to the inverting input terminal. When a voltage exceeding the target output voltage is input to the inverting input terminal, the voltage is connected to the AGC terminal until the peak detection voltage of the AGC amplifier output matches the second set voltage and the second comparator 16 is inverted. Continue charging the remaining capacity. Further, when the voltage equal to the target output voltage is input to the inverting input terminal, the second comparator 16 can be omitted. After the inversion of the second comparator 16, the second circuit is cut off.

  When a voltage exceeding the target output voltage is input to the inverting input terminal of the second comparator 16, the AGC terminal voltage supplied to the AGC amplifier is temporarily charged higher than the target gain setting voltage of the AGC amplifier. By charging to a voltage slightly higher than the target gain setting voltage in this way, even if the input voltage changes when the AGC amplifier is activated, the target gain setting voltage value can be reliably determined. As a result, a stable output voltage can be obtained in a short time. The time for charging the capacitor connected to the AGC terminal by the second circuit is time d (see FIG. 2).

  The third circuit includes the third comparator 10, and discharges the capacitor connected to the AGC terminal until the third comparator 10 is inverted after the inversion of the second comparator 16, and the AGC terminal The voltage is converged to the target gain setting voltage. The third circuit is an n-type having a gate connected to the output terminal of the third comparator 10, a drain connected to a power source via a fourth current source and a third current source, and a source grounded An output of the third comparator 10 controls the n-type MOSFET 11. In the third comparator 10, the peak detection voltage of the AGC amplifier output is input to the non-inverting input terminal, the reference voltage serving as the target output voltage is input to the inverting input terminal, and the peak detection voltage of the AGC amplifier output is used as the reference voltage. The discharge of the capacitor connected to the AGC terminal is continued until the third comparator 10 is inverted in accordance with the coincidence. The time discharged by the third circuit is time e (see FIG. 2).

  As described above, in this embodiment, the startup time of the AGC amplifier until the converged stable output is obtained is the time c + time d + time e shown in FIG. 2, and the startup time of the conventional AGC amplifier (shown in FIG. 5). Therefore, the power consumption of the receiving circuit can be reduced.

The circuit diagram which shows the gain control circuit of the AGC amplifier of the Example of this invention. The characteristic view explaining the time change of the AGC amplifier gain setting voltage and the peak detection voltage of the AGC amplifier output in the gain control circuit of the present invention. A circuit diagram of a receiving circuit in which an AGC amplifier is used. The circuit diagram which shows the gain control circuit of the conventional AGC amplifier. The characteristic view explaining the time change of the AGC amplifier gain setting voltage and the peak detection voltage of the AGC amplifier output in the conventional gain control circuit.

Explanation of symbols

1, 2, 3, 17 ... NOT circuit 4, 5, 6 ... NAND circuit 7, 10, 16 ... comparator 8, 15 ... p-type MOSFET
9 ... Power supply 11, 14, 18 ... n-type MOSFET
DESCRIPTION OF SYMBOLS 12 ... AGC terminal 13 ... Capacitance 20 ... Comparator 21 ... Reception circuit 22 ... Antenna 23 ... AGC amplifier 24 ... Post amplifier 26 ... Crystal filter 27 ... Rectifier 28 ... Switch 29 ... Low-pass filter

Claims (1)

A gain control method for converging a voltage of a gain setting terminal of an AGC amplifier capable of gain adjustment, which amplifies a radio wave reception signal incorporated in a receiving circuit, to a constant value, which is higher than a maximum gain setting voltage applied to the gain setting terminal. A first step of setting a low target gain setting voltage and starting with application of a start signal, until the voltage at the gain setting terminal matches a first setting voltage lower than the target gain setting voltage, by a first current After the second step of charging the gain setting terminal and the first step, the first current is applied until the peak detection voltage of the AGC amplifier output matches the second setting voltage exceeding the target gain setting voltage. A third step of charging the gain setting terminal with a smaller second current, and after the second step, the peak detection voltage matches the target gain setting voltage. Gain control method characterized by comprising a fourth step of discharging the voltage of the gain setting terminal to.

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