JP4877133B2 - Precoder device and transmitter - Google Patents

Description

  The present invention performs a predetermined process on input information including a predetermined number of symbols to generate output information including a predetermined number of symbols, and uses the output information output from the precoder apparatus to perform phase deviation. The present invention relates to a transmission device that performs transmission modulation to generate transmission data.

  In recent years, the penetration rate of optical fibers has increased, and it is expected that optical fibers will be laid in most ordinary homes in the near future. Under such circumstances, there is a demand for higher capacity than ever, and long-distance transmission is being studied with the maximum transmission speed increased from 10 Gbps (bit per second) to 40 Gbps. Here, as one of the techniques for realizing the above-described long-distance transmission, a differential binary phase shift keying (DBPSK) system or a differential quadrature phase shift modulation (DQPSK) is provided. A phase shift keying method such as a shift keying method has attracted attention.

  FIG. 9 is a block diagram showing a main configuration of a conventional transmitter using differential quadrature phase shift keying. As shown in FIG. 9, the transmitter 100 includes a framer function unit 101, a parallel precoder 102, and a transponder 103. The framer function unit 101 multiplexes data to be transmitted into multiple frames such as SONET (Synchronous Optical NETwork: Synchronous Optical Hierarchy), SDH (Synchronous Digital Hierarchy), OTN (Optical Transport Network). The data D101 for 8 channels (8 symbols) with 2 bits as 1 channel is output in synchronization with the transfer clock. In the case of OTN, the data D101 is output in synchronization with a 2.7 GHz transfer clock.

  The parallel precoder 102 performs a predetermined operation on the data D101 as input information output from the framer function unit 101, and outputs data D102 as output information. The transponder 103 generates transmission data D103 by performing phase shift keying (for example, DQPSK) using the data D102 output from the parallel precoder 102, and transmits the transmission data D103 to the outside. Further, the transponder 103 receives and demodulates transmission data D104 transmitted from the outside, and outputs the reception data D105 obtained thereby to the framer function unit 101. The received data D105 is data for eight channels synchronized with a 2.7 GHz transfer clock, similarly to the data D101 output from the framer function unit 101.

  FIG. 10 is a block diagram showing the internal configuration of the parallel precoder 102. As shown in FIG. 10, the parallel precoder 102 is provided with eight precoders 110 having the same number as the number of channels (symbols) of the data D101 in parallel, and holds the output end of the precoder 110 in the eighth stage (final stage). In this configuration, the first stage precoder 110 is connected to the input terminal via the circuits 111a and 111b. The parallel precoder 102 performs logical operations simultaneously in parallel on the eight symbols (data D101) taken out in order, and again in the next cycle, the eight symbols (data D101) in the next order. On the other hand, logical operations are simultaneously performed in parallel, and thereafter the same calculation processing is repeated.

FIG. 11 is a circuit diagram showing an internal configuration of the precoder 110 provided in the parallel precoder 102. As shown in FIG. 11, the precoder 110 includes a plurality of AND (logical product) circuits, an OR (logical sum) circuit, a NAND (negative logical product) circuit, and the like. Each of the precoders 110 transmits data (I _j , Q _j ) for one channel (2 bits) to be transmitted and data (ρ _k−1 , η _k− ) for one channel (2 bits) one symbol before. ₁ ) and the following equation (1) is performed to generate data (ρ _k , η _k ) for one channel (2 bits).

For details of the transmitter and parallel precoder described above, refer to Patent Document 1 below.
JP 2006-245647 A

  By the way, in the parallel precoder 102 provided in the conventional transmitter 100, as described above, each of the precoders 110 provided in parallel simultaneously performs the calculation expressed by the above equation (1). However, referring to FIG. 10, since the precoder 110 receives the output of another precoder 110 provided adjacent thereto, the delay time generated in one precoder 110 affects the other precoder 110. Therefore, for example, when the number of channels (symbols) of the data D101 increases and the number of precoders 110 increases, the accumulation of delay time in each precoder 110 increases, and until all the precoders 110 have finished their computations. There is a possibility that a malfunction will occur when the time required for the above becomes more than one cycle of the transfer clock.

  In recent years, various circuits have been realized using inexpensive field programmable gate arrays (FPGAs), but FPGAs have a lower operating frequency range than gate arrays and the like. For this reason, in order to suppress the time required for the completion of the calculation of all the precoders 110 within one cycle of the transfer clock, the parallel precoder 110 must be realized with an expensive high-speed element, which causes an increase in cost. There is a possibility.

  The present invention has been made in view of the above circumstances, and even when the number of symbols constituting input information is increased, output information similar to the conventional one can be obtained without causing a significant cost increase. It is an object of the present invention to provide a precoder device and a transmission device including the precoder device.

In order to solve the above-described problem, the precoder apparatus according to the present invention performs predetermined processing on input information including a predetermined number of symbols (S1 to S8) represented by a Gray code, and performs a predetermined process represented by a Gray code. In a precoder (1) that generates output information composed of a number of symbols (S11 to S18), a first conversion unit (12) that converts the input information represented by a Gray code into input information represented by a binary code ) And an integration unit (13) for accumulating and accumulating values from the last last symbol to the symbol for each of the symbols constituting the input information converted by the first conversion unit, and for each symbol by the integration unit And a second conversion unit (14) for converting the value accumulated and accumulated into output information represented by a Gray code.
According to the present invention, when input information composed of a predetermined number of symbols represented by a gray code is input, the first conversion unit converts the input information into input information represented by a binary code, and the symbols constituting the converted input information For each of the above, values from the previous last symbol to the symbol are cumulatively accumulated in the accumulating unit, and a value accumulated and accumulated for each symbol is converted into output information represented by a Gray code in the second converting unit.
In the precoder device according to the present invention, the integrating unit includes an integrating circuit (13a, 13b) having a plurality of stages, and cumulatively integrates the value of the symbol with the number of clocks corresponding to the number of stages of the integrating circuit. It is characterized by that.
Further, the precoder device of the present invention is characterized in that the integration circuit includes the same number of integration blocks (21a to 21h, 22a to 22h) as the number of symbols constituting the input information.
Further, the precoder device of the present invention is characterized in that the integration block partially integrates the value of a symbol from the previous last symbol to the current final symbol.
In the precoder of the present invention, if the number of symbols constituting the input information is X, the number of input terminals of the integration block is Y, and the number of stages of the integration circuit is T, (Y-1) · Y ^{(T -1) The} relationship of ≧ X is satisfied.
Furthermore, the precoder device of the present invention includes an inverting unit (11) provided in a preceding stage of the first conversion unit and inverting the value of each symbol constituting the input information represented by a Gray code. Yes.
The transmission apparatus according to the present invention includes a precoder apparatus that generates predetermined output information, and a transponder (103) that performs phase shift modulation using the output information from the precoder apparatus and generates transmission data. The precoder device includes any one of the precoder devices described above.

  According to the present invention, input information composed of a predetermined number of symbols represented by a Gray code is converted into input information represented by a binary code, and each symbol constituting the converted input information is converted from the previous last symbol. Since the value up to the symbol is accumulated and converted, and the accumulated value for each symbol is converted into output information expressed in gray code, even if the number of symbols constituting the input information increases, Output information similar to the conventional one can be obtained without causing a significant increase in cost.

  Hereinafter, a precoder and a transmitter according to an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a precoder apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the precoder device 1 of this embodiment includes an inverting unit 11, a converting unit 12 (first converting unit), an integrating unit 13, and a converting unit 14 (second integrating unit). A predetermined process is performed on the input information composed of the eight symbols S1 to S8 represented by the above, and output information composed of the eight symbols S11 to S18 represented by the Gray code is generated. Symbols S1 to S8 and S11 to 18 are each composed of 2-bit data, and are input / output to / from precoder device 1 in synchronization with a transfer clock (not shown). Further, it is assumed that the precoder apparatus 1 according to the present embodiment operates in synchronization with the above-described transfer clock and generates output information suitable for the differential quadrature phase shift keying (DQPSK) system.

  First, an outline of the precoder device 1 will be described before the details of each block included in the precoder device 1 are described. The precoder device 1 according to the present embodiment converts input information represented by a gray code into a binary code by a conversion unit 12, and accumulates and accumulates each symbol constituting the input information converted into a binary code by an accumulation unit 13. Output information is generated by converting the cumulatively accumulated value into a gray code again by the conversion unit 14. Here, the differential phase modulation method such as DQPSK is a modulation method that modulates by taking a relative phase difference with respect to the phase of the preceding signal, so the phase of the signal at the present time is the phase difference of all the preceding signals. It can be obtained by accumulating cumulatively. Based on this concept, the precoder device 1 of the present embodiment obtains a value indicating the current signal phase by accumulating in the accumulating unit 13 for each symbol constituting the input information.

  Here, the accumulating unit 13 does not accumulatively accumulate the phase difference itself, but accumulatively accumulates symbols associated with the phases. For this reason, in order to facilitate the calculation of the value indicating the current phase, it is desirable that the phase magnitude relationship and the symbol magnitude relationship match. In the present embodiment, the gray code is converted into a binary code by the conversion unit 12 in order to facilitate the calculation of the value indicating the current phase. In addition, since the information used when performing DQPSK needs to be expressed by the Gray code, the conversion part 14 which converts the value expressed by the binary code integrated by the integration part 13 into the Gray code is also provided. .

  This will be specifically described below. FIG. 2 is a diagram showing a relationship between a phase and a symbol in DQPSK, (a) is a diagram showing a relationship when the symbol is represented by a Gray code, and (b) is a symbol representing a binary code. It is a figure which shows the relationship in case represented by. Referring to FIG. 2A, when the symbol is represented by a Gray code, the phase π / 4, 3π / 4, with respect to the symbols (00), (01), (11), and (10). 5π / 4 and 7π / 4 are associated with each other. On the other hand, referring to FIG. 2B, when the symbol is represented by a binary code, the phase π / 4, with respect to the symbols (00), (01), (10), and (11). 3π / 4, 5π / 4, and 7π / 4 are associated with each other.

  Now, the symbols (00), (01), (10), and (11) can be expressed as decimal numbers “0”, “1”, “2”, and “3”. Referring to FIG. 2A, in the case of the Gray code, values “0”, “1”, “3”, “2” with respect to the phases π / 4, 3π / 4, 5π / 4, and 7π / 4. "Is associated with each other, and the magnitude relation of the phase does not match the magnitude relation of the symbols. On the other hand, referring to FIG. 2B, in the case of binary code, values “0”, “1”, “2” with respect to phases π / 4, 3π / 4, 5π / 4, and 7π / 4. , “3” are associated with each other, and the magnitude relation of the phase and the magnitude relation of the symbols coincide with each other. Therefore, the conversion unit 12 converts the gray code into a binary code.

  Next, each block provided in the precoder device 1 will be described in detail. The inverting unit 11 includes eight inverter circuits 11a to 11h corresponding to the symbols S1 to S8 constituting input information. The inverter circuits 11a to 11h are provided in order to obtain an input / output relationship similar to that of the conventional precoder 110 shown in FIG. FIG. 3 is a diagram for explaining the reason why the inverting unit 11 is provided. FIG. 3A is a truth table showing the input / output relationship of the conventional precoder 110 shown in FIG. 11, and FIG. ) Is a truth table in which the truth table is rewritten into binary code.

In FIG. 3A, the “previous symbol” is a symbol one symbol before ((ρ _k−1 , η _k−1 ) shown in FIG. 11), and the “input symbol” is a newly input symbol (FIG. 11 (I _j , Q _j )). The 16 symbols specified by the “previous symbol” and the “input symbol” are newly generated symbols ((ρ _k , η _k ) shown in FIG. 11). Referring to the truth table of FIG. 3A, it can be seen that the new symbol is obtained by adding the phase shift amount indicated by the input symbol to the previous symbol.

  For example, when the input symbol is “00”, when the previous symbol is “00”, a new symbol “11” is generated, and when the previous symbol is “01”, a new symbol “10” is generated. . Similarly, when the previous symbols are “11” and “10”, new symbols “00” and “01” are generated, respectively. Here, referring to FIG. 2A, the phase of the new symbol “11” is shifted by π from the previous symbol “00”. Similarly, the new symbols “10”, “00”, and “01” are shifted in phase by π from the previous symbols “01”, “11”, and “00”, respectively. Therefore, it can be seen that the phase shift amount indicated by the input symbol “00” is π. In the same manner, the phase deviation amount indicated by the input symbol “01” is 3π / 2, the phase deviation amount indicated by the input symbol “11” is 0, and the phase deviation amount indicated by the input symbol “10”. It can be seen that the transfer amount is π / 2.

  Next, referring to FIG. 2, gray code symbols (00), (01), (11), and (10) and binary code symbols (00), (01), (10), and (11), respectively. It corresponds. If the truth table shown in FIG. 3A is rewritten for the binary code based on the correspondence, the truth table shown in FIG. 3B is obtained. Here, as described with reference to the truth table shown in FIG. 3A, the new symbol has a relationship obtained by adding the phase shift amount indicated by the input symbol to the previous symbol. The values of A, B, C, and D in () are (10), (11), (00), and (01), respectively. As a result, when the cumulative amount of phase difference is expressed in binary code, the input symbols (00), (01), (11), (01) are replaced with the input symbols (10), (11), (00). , (01) need to be converted. Such a conversion can be realized by a first conversion that inverts each of the input symbols and a second conversion that is converted using a conversion rule from gray code to binary code. In the present embodiment, the conversion unit 11 is provided to perform the first conversion. The second conversion is realized by the conversion unit 12. By performing such conversion, an input / output relationship similar to the input / output relationship of the conventional precoder 110 shown in FIG. 11 is obtained in this embodiment.

  The conversion unit 12 includes eight conversion circuits 12a to 12h corresponding to the symbols S1 to S8 constituting input information. FIG. 4 is a circuit diagram showing an internal configuration of the conversion circuits 12a to 12h. As shown in FIG. 4, each of the conversion circuits 12a to 12h includes an EXOR (exclusive OR) circuit 31, and outputs the upper bit b1 of the input symbol as the upper bit b3 as it is, The exclusive OR of the lower bit b2 and the upper bit b1 is calculated by the EXOR circuit 31, and the calculation result is output as the lower bit b4. As a result, the gray code symbols (00), (01), (11), and (10) are converted into binary code symbols (00), (01), (10), and (11), respectively.

  The accumulating unit 13 includes two-stage accumulating circuits 13a and 13b, and for each of the symbols converted by the converting circuits 12a to 12h, the last final symbol (the last of the symbols input at the previous clock). Symbols) to the respective symbols are cumulatively accumulated. Here, the accumulating unit 13 accumulates and accumulates the symbols converted into the binary code with the number of transfer clocks (2 clocks) corresponding to the number of stages of the integrating circuits 13a and 13b. The integration circuit 13a includes the same number of integration blocks 21a to 21h as the symbols S1 to S8 constituting input information. Similarly, the integration circuit 13b includes the same number of integration blocks 22a to 22h as the symbols S1 to S8 constituting the input information.

  FIG. 5 is a diagram illustrating an internal configuration of the integration blocks 21a to 21h and 22a to 22h. As shown in FIG. 5, the integration blocks 21 a to 21 h and 22 a to 22 h include an adder 41 that adds 4-bit symbols and a D flip-flop 42 whose input terminal is connected to the output terminal of the adder 41. . The integration blocks 21a to 21h and 22a to 22h operate in synchronization with a transfer clock (not shown). When four symbols of 2 bits are input to the integration blocks 21a to 21h and 22a to 22h, they are added by an adder 41, and the addition result is externally synchronized with a transfer clock (not shown) via a D flip-flop 42. Is output. In other words, each of the integration blocks 21a to 21h and 22a to 22h partially determines a symbol value between the previous last symbol and the current final symbol (the final symbol of the symbols input at the current clock). Accumulate.

  Here, the accumulation processing performed by the integration unit 13 will be described more specifically. FIG. 6 is a diagram for explaining the cumulative integration process performed by the integration unit 13. Now, as shown in FIG. 6, the symbols output from the conversion circuits 12a to 12h are V1 to V8, respectively. In FIG. 6, symbol V0 represents the last symbol of the previous time. Referring to FIG. 1, a conversion circuit 12a is connected to the input terminal of the integration block 21a, conversion circuits 12a and 12b are connected to the input terminal of the integration block 21b, and conversion circuits 12a to 12c are connected to the input terminal of the integration block 21c. 12c is connected, and conversion circuits 12a to 12d are connected to the input terminal of the integrating block 21d. Further, conversion circuits 12b to 12e are connected to the input terminal of the integration block 21e, conversion circuits 12c to 12f are connected to the input terminal of the integration block 21f, and conversion circuits 12d to 12g are connected to the input terminal of the integration block 21g. The conversion circuits 12e to 12h are connected to the input terminal of the integration block 21h.

  With the above connection relationship, the integration blocks 21a to 21h output values obtained by integrating the symbols in the range indicated by the solid arrows denoted by reference signs A1 to A8 in FIG. Specifically, the symbol V1 is output as the partial integration value V11 from the integration block 21a, the value obtained by integrating the symbols V1 and V2 is output as the partial integration value V12 from the integration block 21b, and the symbol V1 is output from the integration block 21c. A value obtained by integrating ~ V3 is output as a partial integrated value V13, and a value obtained by integrating symbols V1 through V4 is output as a partial integrated value V14 from the integration block 21d. A value obtained by integrating the symbols V2 to V5 is output as a partial integrated value V15 from the integration block 21d, and a value obtained by integrating the symbols V3 to V6 is output as a partial integration value V16 from the integration block 21f. A value obtained by integrating the symbols V4 to V7 is output as a partial integrated value V17, and a value obtained by integrating the symbols V5 to V8 is output as a partial integrated value V18 from the integration block 21g.

  Next, output terminals of the integration blocks 21a to 21d are connected to input terminals of the integration blocks 22a to 22d, respectively. Further, the output terminals of the integration blocks 21a and 21e are connected to the input terminal of the integration block 22e, and the output terminals of the integration blocks 21b and 21f are connected to the input terminal of the integration block 22f. Similarly, the output terminals of the integration blocks 21c and 21g are connected to the input terminal of the integration block 22g, and the output terminals of the integration blocks 21d and 21h are connected to the input terminal of the integration block 22h. Furthermore, the output terminal of the integration block 22h is commonly connected to the integration blocks 22a to 22h. The previous final symbol is output from the output terminal of the integration block 22h.

From the above relationship, the cumulative integration values V21 to V28 output from the integration blocks 22a to 22d can be expressed by the following equations.
V21 = V0 + V11
V22 = V0 + V12
V23 = V0 + V13
V24 = V0 + V14
V25 = V0 + V11 + V15
V26 = V0 + V11 + V16
V27 = V0 + V11 + V17
V28 = V0 + V11 + V18

  That is, referring to the above formula and FIG. 6, the cumulative integration values V21 to V28 output from the integration blocks 22a to 22h are values obtained by cumulatively integrating values from the last symbol to the respective symbols. For example, the cumulative integration value V21 output from the integration block 22a is a value obtained by adding the previous last symbol V0 and the symbol V11, and the cumulative integration value V24 output from the integration block 22d is the previous final symbol V0 to the symbol V4. It is a value obtained by integrating up to. Similarly, the cumulative integration value V28 output from the integration block 22h is a value obtained by integrating the previous last symbol V0 to symbol V8.

  The conversion unit 14 includes conversion circuits 14a to 14h, and converts each of the cumulative integration values V21 to V28 output from the integration unit 13 into a Gray code. The internal configuration of the conversion circuits 14a to 14h provided in the conversion unit 14 is the same as the internal configuration of the conversion circuits 12a to 12h illustrated in FIG. As a result, the binary code symbols (00), (01), (10), and (11) are converted to gray code symbols (00), (01), (11), and (10), respectively.

  In the above configuration, when input information composed of eight symbols S1 to S8 expressed in gray code is input to the precoder device 1 in synchronization with the transfer clock, each of the symbols S1 to S8 forming the input information 11 is respectively input to the inverter circuits 11a to 11h included in the circuit 11 and the logic is inverted. Each symbol whose logic is inverted is input to conversion circuits 12a to 12h included in the conversion unit 12 and converted into a symbol represented by a binary code. Each symbol converted by the conversion circuits 12a to 12h is input to integration blocks 21a to 21h included in the integration circuit 13a of the integration unit 13 in accordance with the connection relationship shown in FIG. 1, whereby partial integration values V11 to V18 (FIG. 6). Reference) is required. Here, since the integration circuit 13a operates in synchronization with a transfer clock (not shown), the partial integration values V11 to V18 are obtained during one period of the synchronization clock.

  Partial integration values V11 to V18 obtained in each of the integration blocks 21a to 21h are output from the integration blocks 21a to 21h in synchronization with a transfer clock (not shown), and are integrated by the integration unit 13 in accordance with the connection relationship shown in FIG. Accumulated integrated values V21 to V28 obtained by accumulating the values from the last symbol to the respective symbols are input to the integrating blocks 22a to 22h included in the circuit 13b. Here, since the integrating circuit 13b also operates in synchronization with a transfer clock (not shown), the accumulated integrated values V21 to V28 are obtained during one period of the synchronous clock. Accumulated integrated values V21 to V28 obtained in each of the integrating blocks 22a to 22h are output from the integrating blocks 22a to 22h in synchronization with a transfer clock (not shown) and input to the converting circuits 14a to 14h included in the converting unit 14, respectively. Then, it is converted into a symbol represented by a Gray code and outputted from the precoder device 1 as symbols S11 to S18.

  As described above, in the precoder device 1 of the present embodiment, the symbols S1 to S8 represented by the gray code are converted into the symbols represented by the binary code, and the values from the last symbol of the previous time to each of the current symbols are converted. Cumulative integration values V21 to V28 are respectively obtained by accumulating, and the accumulated integration values V21 to V28 are converted into symbols represented by gray codes and output. Here, when performing the above-mentioned cumulative integration, the integration circuit 13a obtains the partial integration values V11 to V18 by one transfer clock, and the integration circuit 13b obtains the cumulative integration values V21 to V28 by the next one clock of the transfer clock. Seeking. From the above, the precoder apparatus 1 of the present embodiment can be realized at low cost using an FPGA or the like, and can obtain output information similar to the conventional one without causing an increase in cost.

[Second Embodiment]
FIG. 7 is a block diagram showing the configuration of the precoder apparatus according to the second embodiment of the present invention. As shown in FIG. 7, the precoder device 2 of the present embodiment includes an inversion unit 51 and a conversion unit corresponding to the inversion unit 11, the conversion unit 12, the integration unit 13, and the conversion unit 14 included in the precoder device 1 shown in FIG. 1. 52 (first conversion unit), integration unit 53, and conversion unit 54 (second integration unit), and a predetermined process for input information composed of 256 symbols S1 to S256 expressed in gray code To generate output information composed of 256 symbols S1001 to S1256 expressed in gray code.

  The inversion unit 51 inverts the value of the symbol that forms the input information, similarly to the inversion unit 11 shown in FIG. The point provided is different from the reversing unit 11. Similarly, the conversion unit 52 converts the symbols S1 to S256 expressed in gray code into symbols expressed in binary code, and the conversion unit 52 converts a value expressed in binary code into gray code. However, it is different from the converters 12 and 14 shown in FIG.

  Like the integration unit 13 shown in FIG. 1, the integration unit 53 accumulates and accumulates values from the last symbol to the respective symbols for each of the symbols constituting the input information converted into the binary code. However, the integration unit 53 is different from the integration unit 13 in that the integration circuits 53a, 53b, and 53c having three stages are provided and the integration is performed with three transfer clocks. Another difference is that each of the integration circuits 53a, 53b, and 53c includes 256 integration blocks each having eight input terminals shown in FIG.

  FIG. 8 is a diagram illustrating an internal configuration of an integration block included in the integration circuits 53a, 53b, and 53c. As shown in FIG. 8, the integration block includes an adder 61 that adds symbols for 8 bits, and a D flip-flop 62 whose input terminal is connected to the output terminal of the adder 61. Operates synchronously. Similarly to the integration blocks 21a to 21h and 22a to 22h shown in FIG. 1, the integration block having such a configuration also extends from the previous last symbol to the current final symbol (the final symbol of symbols input at the current clock). The symbol values in between are partially integrated. In FIG. 7, for the sake of simplification of illustration, illustration of connection lines connecting between integration blocks is omitted.

  In the above configuration, when input information composed of 256 symbols S1 to S256 expressed in gray code is input to the precoder device 2 in synchronization with the transfer clock, the symbols S1 to S256 constituting the input information are inverted. Each is input to an inverter circuit included in the unit 51 and the logic is inverted. Each symbol whose logic is inverted is input to a conversion circuit included in the conversion unit 52 and converted into a symbol represented by a binary code.

  Each symbol converted by the conversion circuit is input to an integration block included in the integration circuit 53a of the integration unit 53, and a partial integration value is obtained for one period of the synchronous clock. The 256 partial integration values obtained in the integration block provided in the integration circuit 53a are input to the integration block provided in the integration circuit 53b, and 256 partial integration values are obtained in the same manner for one period of the synchronous clock. . Then, the 256 partial integration values obtained by the integration block provided in the integration circuit 53b are input to the integration block provided in the integration circuit 53c, whereby the values from the previous last symbol to each symbol are cumulatively integrated. 256 accumulated integrated values are obtained during one period of the synchronous clock.

  The 256 cumulative integration values obtained by the integration block of the integration circuit 53c are output from the integration circuit 53c in synchronization with a transfer clock (not shown), and are input to the conversion circuit provided in the conversion unit 54, and are expressed in gray code. The converted symbols are output from the precoder 2 as symbols S1001 to S1256. As described above, the precoder apparatus 2 according to the present embodiment can obtain the same output information as before without causing a significant cost increase even when the number of symbols constituting the input information is as large as 256. it can.

Here, in a precoder apparatus including an integrating unit including an integrating circuit composed of a plurality of stages, the number of symbols constituting input information to be input is X, and the input end of an integrating block provided in each of the integrating circuits provided in the integrating unit When the number is Y and the number of stages of the integrating circuit is T, the relationship shown in the following equation (2) is satisfied.
(Y-1) · Y ^(T-1) ≧ X (2)
Here, rewriting the above equation (2) by paying attention to the number of stages T of the integrating circuit, the following equation (3) is obtained.
T ≧ LOG _Y (X / (Y−1)) + 1 (3)

  In the precoder apparatus 1 shown in FIG. 1, the number X of symbols constituting input information is “8”, and the number Y of input terminals of the integration block is “4”. By substituting these numerical values into the above equation (3), a relational expression T ≧ 1.7 is obtained. From this relational expression, it can be seen that the number T of stages of integration circuits provided in the integration unit 13 provided in the precoder device 1 is “2”. Further, in the precoder apparatus 2 shown in FIG. 7, the number X of symbols constituting the input information is “256”, and the number Y of input terminals of the integration block is “8”. By substituting these numerical values into the above equation (3), the relational expression T ≧ 2.7 is obtained. From this relational expression, it can be seen that the number T of stages of the integrating circuits included in the integrating unit 53 of the precoder device 2 is “3”. In the precoder device 2 shown in FIG. 7, when the number Y of input terminals of the integration block provided in each of the integration circuits of the integration unit 53 is changed to “4”, T ≧ 4.2 from the above equation (3). The following relational expression is obtained. As a result, it can be seen that the number T of stages of the integration circuit provided in the integration unit 53 of the precoder device 2 changes to “5”.

  Although the precoder device according to the embodiment of the present invention has been described above, the transmitter according to the present embodiment is provided with the precoder device 1 described above instead of the parallel precoder 102 included in the transmitter 100 illustrated in FIG. 9, for example. It is realized with. Alternatively, the transmission apparatus according to the present embodiment uses the framer function unit that outputs data for 256 channels, the precoder apparatus 2 described above, and phase shift keying (for example, DQPSK) using the data output from the precoder apparatus 2. This is realized by including a transponder that generates transmission data for 256 channels. According to such a transmission apparatus, since the costs of the precoder apparatuses 1 and 2 are reduced, the cost of the transmission apparatus is also reduced. In addition, since the precoder apparatuses 1 and 2 according to the present embodiment do not accumulate delay time unlike the conventional parallel precoder 102, the transmission apparatus according to the present embodiment including the precoder apparatuses 1 and 2 includes the accumulated delay time. There will be no malfunction caused by. Note that the transmission apparatus according to the present embodiment can be provided in an analyzer apparatus that analyzes and tests a communication state, for example.

  The precoder device and the transmission device according to the embodiment of the present invention have been described above, but the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above-described embodiment, the case where the integration unit is composed of 2, 3, and 5 stages of integration circuits has been described as an example, but the integration unit may be composed of other stages of integration circuits. Further, the integrating unit is not limited to a case where a plurality of stages of integrating circuits are provided, and may be configured to include only a single stage of integrating circuit. Note that the precoder device of this embodiment can cope with a transmission rate of 40 Gbps or higher.

It is a block diagram which shows the structure of the precoder apparatus by 1st Embodiment of this invention. It is a figure which shows the relationship between the phase in DQPSK, and a symbol. It is a figure for demonstrating the reason for providing the inversion part. It is a circuit diagram which shows the internal structure of conversion circuits 12a-12h. It is a figure which shows the internal structure of integrating | accumulating blocks 21a-21h and 22a-22h. It is a figure for demonstrating the accumulation process performed by the integration part. It is a block diagram which shows the structure of the precoder apparatus by 2nd Embodiment of this invention. It is a figure which shows the internal structure of the integration block with which the integration circuits 53a, 53b, and 53c are provided. It is a block diagram which shows the principal part structure of the conventional transmitter using differential four phase phase shift keying. 2 is a block diagram showing an internal configuration of a parallel precoder 102. FIG. 2 is a circuit diagram showing an internal configuration of a precoder 110 provided in a parallel precoder 102. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Precoder apparatus 12 Conversion part 13 Integration part 13a, 13b Integration circuit 14 Conversion part 21a-21h Integration block 22a-22h Integration block 51 Inversion part 52 Conversion part 53 Integration part 53a-53c Integration circuit 54 Conversion part S1-S8 Symbol S11 to S18 symbols

Claims (7)

In a precoder device that performs predetermined processing on input information composed of a predetermined number of symbols represented by a Gray code, and generates output information composed of a predetermined number of symbols represented by a Gray code.
A first conversion unit that converts the input information represented by a gray code into input information represented by a binary code;
For each of the symbols constituting the input information converted by the first conversion unit, an accumulation unit for accumulating and accumulating values from the previous last symbol to the symbol,
A precoder apparatus comprising: a second conversion unit that converts a value accumulated and accumulated for each symbol by the accumulation unit into output information represented by a Gray code.   2. The precoder apparatus according to claim 1, wherein the integration unit includes an integration circuit having a plurality of stages, and cumulatively integrates the value of the symbol with the number of clocks corresponding to the number of stages of the integration circuit.   3. The precoder apparatus according to claim 2, wherein the integration circuit includes the same number of integration blocks as the number of symbols constituting the input information.   4. The precoder device according to claim 3, wherein the integration block partially integrates symbol values between the last symbol of the previous time and the final symbol of the current time. When the number of symbols constituting the input information is X, the number of input ends of the integration block is Y, and the number of stages of the integration circuit is T,
(Y-1) · Y ^(T-1) ≧ X
The precoder apparatus according to claim 3 or 4, wherein the following relationship is satisfied.   6. The circuit according to claim 1, further comprising an inversion unit that is provided in a preceding stage of the first conversion unit and inverts the value of each symbol constituting the input information represented by a Gray code. The precoder device according to item. In a transmission apparatus comprising: a precoder that generates predetermined output information; and a transponder that generates transmission data by performing phase shift keying using the output information from the precoder.
A transmission device comprising the precoder device according to any one of claims 1 to 6 as the precoder device.

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