JP4877332B2 - Pulse booster circuit - Google Patents

Description

  The present invention relates to a pulse booster circuit that boosts a peak value of a periodic pulse to a power supply voltage or higher.

  Recent LSIs often require multiple power supplies such as 3V, 5V, and 10V inside the circuit. Conventionally, when such multiple power supplies are required, a plurality of power supplies are generated outside the LSI and supplied to the LSI. However, recently, the power supplied to the LSI is one power supply, and it is required to generate multiple power supplies inside the LSI.

In order to generate a voltage higher than the power supply voltage Vcc supplied from outside in the LSI, a periodic pulse having a peak value Vcc is generated by the power supply voltage Vcc, and the peak value of the periodic pulse is boosted and used as a power supply voltage. Is done. In circuit operation, a periodic pulse having a peak value higher than the power supply voltage Vcc may be required.
On the other hand, in recent cellular phones, for example, with the miniaturization of the device, the battery is further miniaturized. As a result, the output voltage of the battery is also lowered. For this reason, the need for a circuit that boosts the power supply voltage or a circuit that boosts the pulse peak value is increasing.
In addition, what is described in patent documents 1-4 is known as a prior art.

Japanese Patent Publication No. 7-3947 Japanese Examined Patent Publication No. 7-75466 Japanese Patent No. 2583948 Japanese Patent No. 3242564

  The present invention has been made in consideration of such circumstances, and an object thereof is to realize a pulse booster circuit capable of boosting the peak value of a periodic pulse with a simple configuration. Another object of the present invention is to provide a pulse booster circuit capable of boosting even when the peak value is extremely low, for example, 1 V (volt).

  The present invention has been made to solve the above-described problems, and the invention according to claim 1 boosts a periodic pulse that repeats the first and second levels, which is input to the input terminal, from the output terminal. In the pulse booster circuit for outputting, when the periodic pulse is at the first level, the charging circuit for charging the capacitor, and the first pulse according to the change of the periodic pulse at the input terminal that repeats the first and second levels. And a switching circuit that alternately outputs a voltage obtained by adding a power supply voltage to the charging voltage of the capacitor to an output terminal.

  According to a second aspect of the present invention, there is provided a pulse booster circuit that boosts a periodic pulse that repeats the first and second levels and is output from the output terminal, and inverts the voltage at the input terminal. And a capacitor having one end connected to the output terminal of the inverting circuit, a charging circuit for charging the capacitor when the voltage at the input terminal is at the first level, and the first and second levels are repeated. A pulse booster circuit comprising: a switching circuit that alternately outputs the first level and the voltage at the other end of the capacitor to an output terminal in accordance with a change in a periodic pulse at an input terminal. .

According to a third aspect of the present invention, in the pulse booster circuit according to the first or second aspect, the switching circuit includes first and second amplifying elements having different conductivity types connected in series. To do.
According to a fourth aspect of the present invention, in the pulse booster circuit according to the third aspect, the first periodic pulse that repeats the first and second levels and the rising edge slightly earlier than the rising edge of the first periodic pulse. A pulse generation circuit for outputting a second periodic pulse that falls slightly later than the falling edge of the first periodic pulse, and the first and second amplifying elements are respectively connected to the first and second periodic pulses. It is characterized by driving by.

As described above, according to the present invention, when the periodic pulse is at the first level, the charging circuit that charges the capacitor and the change of the periodic pulse at the input terminal that repeats the first and second levels, Since the first level and the switching circuit that alternately outputs the voltage obtained by adding the power supply voltage to the charging voltage of the capacitor to the output terminal are provided, the pulse boosting circuit capable of boosting the peak value of the periodic pulse is simplified. There is an effect that can be realized by a simple configuration. Further, the pulse booster circuit according to the present invention can operate if the power supply voltage Vcc is larger than the threshold voltage Vth (= about 0.7V) between the source and gate of the FET, and the power supply voltage is extremely low, for example, 1V. Can also be operated.
According to the invention of claim 4, there is an effect that a through current of the switching circuit can be prevented.

1 is a circuit diagram showing a configuration of a pulse booster circuit according to a first embodiment of the present invention. FIG. 3 is a timing chart for explaining the operation of the embodiment. It is a circuit diagram which shows the structure of the pulse booster circuit by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the pulse booster circuit by 3rd Embodiment of this invention. FIG. 6 is a circuit diagram for explaining the operation of the pulse generation circuit 20 in the same embodiment. 3 is a circuit diagram showing a configuration example of a pulse generation circuit 20 in the same embodiment. FIG. It is a circuit diagram which shows the structure of the pulse booster circuit by 4th Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a pulse booster circuit according to a first embodiment of the present invention. In this figure, symbol IN is an input terminal to which a rectangular periodic pulse having a peak value Vcc and a duty ratio of 50% is input, and the periodic pulse input to this input terminal IN is inverted by an inverter 8 and FET ( To the gate of the field effect transistor 3). The FET 3 is an N-channel FET, the drain thereof is connected to the power supply voltage Vcc, the source is connected to the input terminal IN via the capacitor 4, and is connected to the gate of the FET 5. The FET 5 is an N-channel FET, its drain is connected to the power supply voltage Vcc, and its source is connected to one end of the capacitor 6 and the source of the FET 7. The inverter 8 inverts the periodic pulse at the input terminal IN and outputs it to the other end of the capacitor 6. FET 7 and FET 9 are respectively a P-channel and an N-channel FET, and the gates and drains of these FETs 7 and 9 are connected in common, thereby constituting an inverter. The gates of the FETs 7 and 9 are connected to the input terminal IN, the drain is connected to the output terminal OUT, and the source of the FET 9 is grounded. The substrate of the FET 7 is commonly connected to the source.

  Next, the operation of the above-described circuit will be described with reference to the timing chart shown in FIG. 2, (IN) is the waveform of the input terminal IN, (A) is the waveform of the connection point A of the FETs 3 and 5, (B) is the waveform of the connection point B of the FETs 5 and 7, and (OUT) is the output terminal OUT. It is a waveform. In the figure, voltage “1” indicates Vcc, and voltage “2” indicates 2 Vcc.

First, when the voltage of the input terminal IN is “H” (high level = Vcc), the output of the inverter 8 is “L” (low = ground potential), and the FET 3 is turned off. At this time, “H” of the input terminal IN is supplied to the gate of the FET 5 through the capacitor 4 and the FET 5 is turned on. Here, as will be described later, since the connection point A is charged to Vcc−Vth (Vth is the threshold value of the FET 3) in advance, the connection point B becomes 2Vcc−Vth, which is higher than Vcc. Becomes triode operation.
When the FET 5 is turned on, the voltage Vcc is charged to the capacitor 6 via the FET 5 (see FIG. 2B). At this time, “H” is applied to the gates of the FETs 7 and 9, whereby the FET 9 is turned on, the FET 7 is turned off, and the output terminal OUT becomes the ground potential. At this time, the voltage at the connection point A is Vcc-Vth, which is lower than Vcc.

  Next, when the input terminal IN becomes “L”, the output of the inverter 8 becomes “H”, and the FET 3 is turned on. As a result, the charging current of the capacitor 4 flows from the FET 3, the gate of the FET 5 becomes “L”, and the FET 5 is turned off. At this time, since the voltage Vcc is charged in the capacitor 6, when the output of the inverter 8 becomes “H”, the voltage at the connection point B becomes 2 Vcc. At this time, the FET 7 is turned on and the FET 9 is turned off, so that the voltage 2Vcc is output from the output terminal OUT.

Next, when the input terminal IN becomes “H” again, the output terminal OUT becomes the ground potential again, and the capacitor 6 is charged. When the input terminal IN becomes “L”, the output terminal OUT becomes the voltage 2Vcc. Thereafter, this operation is repeated.
Thus, according to the pulse booster circuit of the above embodiment, the periodic pulse with the peak value Vcc can be converted into the periodic pulse with the peak value 2Vcc.

Next explained is the second embodiment of the invention.
FIG. 3 is a circuit diagram showing the configuration of the second embodiment of the present invention. In this figure, the periodic pulse input to the input terminal IN is inverted by the inverter 11 and supplied to one end of the capacitor 12. The drain of the N-channel FET 13 is connected to the power supply voltage Vcc, the gate is connected to the drain, and the source is connected to the other end of the capacitor 12 and the source of the P-channel FET 14. The FET 14 and the N-channel FET 15 constitute an inverter, the voltage of the input terminal IN is applied to the connection point of each gate, and the connection point of each drain is connected to the output terminal OUT.

In such a configuration, when the voltage of the input terminal IN is “H”, the output of the inverter 11 is “L”. As a result, the voltage (Vcc−Vth) is charged to the capacitor 12 via the FET 13. Here, the voltage Vth is a gate-source voltage of the FET 13 and is about 0.7V. At this time, the FET 14 is turned off, the FET 15 is turned on, and the output terminal OUT becomes the ground potential. Next, when the input terminal IN becomes “L”, the output of the inverter 11 becomes “H”. As a result, the source voltage of the FET 14 becomes Vcc + (Vcc−Vth) = 2Vcc−Vth.
It becomes. At this time, the FET 13 is reverse-biased between the source and the drain and cut off. At this time, the FET 14 is turned on and the FET 15 is turned off, so that the voltage (2Vcc−Vth) is output from the output terminal OUT.

  Thus, also in the pulse booster circuit of the above embodiment, the peak value of the periodic pulse can be boosted as in the circuit of FIG. If an FET having a threshold value of about 0 V is used for the FET 13, an output voltage of 2 Vcc can be obtained as in the first embodiment.

Next explained is the third embodiment of the invention.
FIG. 4 is a circuit diagram showing a configuration of a pulse booster circuit according to a third embodiment of the present invention. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals.
In the circuit of FIG. 1, a one-phase periodic pulse is supplied to the input terminal IN, and this periodic pulse is input to the gates of the FETs 7 and 9. However, in such a configuration, there is a possibility that a through current that passes through the FETs 7 and 9 flows when the FETs 7 and 9 are switched on / off. Therefore, in the third embodiment, a pulse generating circuit 20 that generates two-phase periodic pulses P1 and P2 having a peak value Vcc based on the periodic pulse at the input terminal IN is provided. FIG. 5 is a waveform diagram of the two-phase periodic pulses P1 and P2 output from the pulse generation circuit 20. As shown in this figure, after the periodic pulse P2 rises, the periodic pulse P1 rises after a lapse of a minute time, and the period After the pulse P1 falls, the periodic pulse P2 falls after a minute time.
Periodic pulses P1 and P2 are input to the gates of the FETs 9 and 7, respectively. The pulse generation circuit 20 is a known circuit, and an example thereof is shown in FIG. In this figure, reference numerals 31 to 38 denote inverters, and reference numerals 41 and 42 denote NAND gates.

  In this embodiment, a P-channel FET 21 and an N-channel FET 22 are provided in place of the inverter 8 of FIG. 1, a periodic pulse P2 is applied to the gate of the FET 21, the source is the power supply voltage Vcc, and the drain is the drain of the FET 22. In addition, a periodic pulse P1 is applied to the gate of the FET 22, and the source of the FET 22 is grounded. A capacitor 6 is connected between the common drain of the FETs 21 and 22 and the source of the FET 7. Further, the respective substrates of the FETs 7 and 21 are connected to the respective sources.

  According to such a configuration, after the periodic pulse P1 becomes “L” and the FET 9 is turned off, the periodic pulse P2 becomes “L” and the FET 7 turns on, and the periodic pulse P2 becomes “H”. After the FET 7 is turned off, the periodic pulse P1 becomes “H” and the FET 9 is turned on. As a result, no through current flows through the FETs 7 and 9.

FIG. 7 is a circuit diagram showing the configuration of the fourth embodiment of the present invention. In this figure, parts corresponding to those in FIG. 3 are given the same reference numerals. The pulse booster circuit shown in this figure is a circuit for preventing a through current of the FETs 14 and 15 in the circuit shown in FIG. That is, similarly to FIG. 4, a pulse generation circuit 20 that outputs a two-phase periodic pulse is provided, and periodic pulses P1 and P2 are input to the gates of the FETs 15 and 14, respectively. Further, a P-channel FET 24 and an N-channel FET 25 are provided in place of the inverter 11 of FIG. 3, a periodic pulse P2 is applied to the gate of the FET 24, the source of the FET 24 is connected to the power supply voltage Vcc, and the drain is connected to the drain of the FET 25. The periodic pulse P1 is applied to the gate of the FET 25, and the source of the FET 25 is grounded. The capacitor 12 is connected between the common drain of the FETs 24 and 25 and the source of the FET 14 .
This circuit can also prevent the through currents of the FETs 14 and 15 as in the circuit of FIG.

  8, 11 ... Inverter 3, 5, 9, 13, 15, 22, 25 ... N-channel FET 7, 14, 21, 24 ... P-channel FET 20 ... Pulse generation circuit IN ... Input terminal OUT ... Output terminal

Claims (1)

A pulse generation circuit that outputs a second periodic pulse and a third periodic pulse that are two-phase periodic pulses from a first periodic pulse input from the outside;
A first P-channel FET having a source connected to a power supply terminal and a gate receiving the third periodic pulse;
A first N-channel FET having a drain connected to a drain of the first P-channel FET, a source grounded, and a gate receiving the second periodic pulse;
A second N-channel FET whose drain and gate are connected to the power supply terminal;
A capacitor having one end connected to the drain of the first P-channel FET and the other end connected to the source of the second N-channel FET;
A second P-channel FET having a source connected to the other end of the capacitor and a gate receiving the third periodic pulse;
A third N-channel FET, the drain of which is connected to the drain of the second P-channel FET, the second periodic pulse is input to the gate, and the source is grounded,
The pulse generation circuit is
When the third periodic pulse is at H level, the capacitor is charged through the second N-channel FET, and when the third periodic pulse is at L level, the voltage charged in the capacitor is used, When boosting the source voltage of the second P-channel FET, the second P-channel FET and the third N-channel FET are simultaneously turned on so as not to discharge the charge charged in the capacitor. and 3 of the periodic pulses is in the L level state, as the second periodic pulse and the state is at the H level do not occur at the same time, the second periodic pulse, said third periodic pulse rises to H level was reluctant Tachinobo to H level after, the third periodic pulse, under stand L level after the second period pulse falls to the L level to wherein the Ru racemate Pulse booster circuit.

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