JP4880355B2 - Bus monitor circuit - Google Patents

Description

  The present invention relates to a bus monitor circuit that monitors and outputs the state of a system bus that is an observation target (bus monitor target).

  An example of this type of prior art (see, for example, Patent Document 1) is shown in FIG. This bus tracer receives the data on the system bus A ′ as an input, and outputs a trace enable signal B ′ and a transfer phase signal C ′ as a data acquisition control signal for the monitored system bus A ′ that satisfies the trace condition. In response to the control circuit 2 ′, the trace mode Reg4 ′ for setting the trace conditions of the trace control circuit 2 ′, and the transfer phase signal C ′ from the trace control circuit 2 ′, the operation is started and the data on the system bus A ′ is transferred. Trigger control circuit 1 ′ that outputs an interrupt signal H ′ and a trigger condition satisfaction signal D ′ as a trace stop control signal for the system bus A ′ when a trigger condition is satisfied as input, and a trigger that sets a trigger condition for the trigger control circuit 1 ′ Mode Reg3 'and memory to store data on system bus A' And the MPU 5 ′ for controlling the entire bus trace such as read control for outputting the data stored in the memory 6 ′ to the local bus E ′, and the data from the outside by the trace enable signal B from the trace control circuit 2 ′. It is composed of a communication controller 7 'for sending and receiving.

  When the trace condition set in the trace mode Reg4 ′ matches the data on the system bus A ′, the trace control circuit 2 ′ outputs the transfer phase signal C ′ to operate the trigger control circuit 1, and also enables the trace. The signal B ′ is output and data storage (writing) of the system bus A ′ to the memory 6 is started. The trigger control circuit 1 ′ that has started the operation monitors data on the system bus A ′ that matches the trigger condition set in the trigger mode Reg 3 ′, and detects data on the system bus A ′ that matches the trigger condition. The establishment signal D ′ and the interrupt signal H ′ are output.

  The trace control circuit 2 ′ to which the trigger condition satisfaction signal D ′ is input stops outputting the trace enable signal B ′ (disables) and stops storing the system bus A ′ data in the memory 6 ′. . Further, the MPU 5 ′ to which the interrupt signal H ′ is input receives the interrupt signal H ′, determines that the acquisition of the system bus data is completed, and reads the system bus A data after tracing stored in the memory 6 ′. Start control. The traced system bus data read from the memory 6 'is output to the outside of the bus tracer via the communication controller 7'.

  Another example of this type of prior art (see, for example, Patent Document 2) is shown in FIG. In this packet distribution selection method, the input terminals 1a and 1b, the packet reception interfaces 2a and 2b, the filter circuits 3a and 3b, the time stamp addition circuits 4a and 4b, the FIFOs 5a and 5b, and the DMA correspond to the two channels a and b. Control circuits 6a and 6b are provided, and a timing control circuit 7, a CPU 8, a memory 9, an I / O control circuit 10, and an external processing unit 11 are provided in common for the two channels a and b.

  The packet reception interface circuits 2a and 2b receive packets from the input terminals 1a and 1b, select packet information to be observed by the filter circuits 3a and 3b, and based on start triggers and end triggers such as sequence numbers. Retrieve packet information. Only the sequence number is extracted from the packets output from the filter circuits 3a and 3b, the arrival time is added as time stamp information by the time stamp addition circuits 4a and 4b, and the information including the sequence number and the time stamp is sequentially sent to the FIFOs 5a and 5b. Written. Information written in the FIFOs 5a and 5b is accumulated in the memory 9 by the DMA control circuits 6a and 6b, and output to the external arithmetic processing unit 11 connected to the outside via the I / O control circuit 10 by the read control by the CPU 8. Is done. The processing between 2a to 6a and 2b to 6b is performed in parallel with two channels, and the two channels a and b are written in the memory 9 in a time-sharing manner.

JP-A-2-284249 (pages 3 to 6, FIG. 2) Japanese Patent Laid-Open No. 4-260248 (page 2 to page 3, FIG. 1)

  However, in the conventional technique described above, all data selected by the trace trigger condition or filter condition is stored once in the memory, so the data stored in the memory is collected by the trace trigger condition or filter condition. Even if it is data, when observing the state of multiple system buses inside the integrated circuit, the data stored in the memory increases, and the data selected by the trace trigger condition or filter condition does not disappear (leak) It is necessary to output to the outside, etc., and the memory must have a capacity that can store the maximum amount of data to be collected, so that the capacity of the memory for writing the collected data increases and the circuit scale increases. There is a first problem.

  Further, since the CPU and DAM control circuit are used as means for outputting the system bus data stored in the memory, the write / read control to the memory becomes complicated, the circuit scale increases, and the CPU and DMA control circuit. Since the circuit scale of itself is large, there is a second problem that the circuit scale increases even when these circuits are used.

  The trace control circuit, trigger control circuit, or filter circuit that is a control circuit for collecting system bus data or packet input is provided for each system bus or packet input to be observed and operates individually. When the target is a plurality of system buses or packet inputs, the amount of collected data for each observation target is reduced by the trace trigger condition or the filter condition.

  However, since the amount of collected data that is finally output is the sum of individual collected data of a plurality of observation target system buses or packet inputs, the capacity of the memory for storing collected data increases and the circuit scale increases. However, since the collected data of the multiple observation targets that are finally output is simply the data collected under the individual trace trigger conditions or filter conditions, the relationship between [observation target-observation target] Is unclear and the system bus data A ′ or packet input A ′ is generated (detected) in the observation target A, and the state of the system bus data B ′ or packet input B ′ in the observation target B is obtained from the collected data. There is a third problem that becomes complicated.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the problems of an increase in the size of a bus monitor circuit, an increase in the number of bus monitor external terminals external to an integrated circuit, and a decrease in monitoring capability caused by an increase in the number of observation target buses. An object of the present invention is to provide a bus monitor circuit that monitors and outputs a plurality of bus states inside an integrated circuit to the outside of the integrated circuit with high speed and minimum external terminals without going through the circuit.

  The bus monitor circuit of the present invention is a bus monitor circuit that monitors and outputs the state of a system bus to be observed at least one of the objects to be monitored. Unit (1 in FIG. 1), a FIFO unit (3 in FIG. 1) having a memory (31 in FIG. 1) corresponding to the system bus for storing bus data extraction data, and a FIFO write enable signal A FIFO write control unit (2 in FIG. 1) that generates and outputs to the FIFO unit together with the bus data extraction data, and a FIFO read control unit (6 in FIG. 1) that generates a FIFO read enable signal and outputs it to the FIFO unit. The FIFO unit (3 in FIG. 1) has a one-to-one correspondence with the memory. When a FIFO write enable signal is input, a memory write enable signal and a memory write address are generated and output to the memory. When the rewrite control unit (32 in FIG. 1) and the FIFO read enable signal are input, the memory read address is generated and output to the memory, the FIFO empty flag signal indicating the memory read empty state, and the memory A memory read control unit (33 in FIG. 1) is provided to output a FIFO almost empty flag signal indicating a read-almost-empty state when it is read. The FIFO read control unit (FIG. 1) is provided. No. 6) is characterized in that only the FIFO read enable signal for the memory not indicating the empty state is made active by the FIFO empty flag signal and the FIFO almost empty flag signal.

  The FIFO write control unit (2 in FIG. 1) controls or selects a combination of filter / trigger match data corresponding to different system buses according to the set link information in response to the trigger condition detection signal input from the bus data detection unit. A link control circuit (23 in FIG. 1) for performing control and generating a link control signal for controlling the start and end of writing of system bus extraction data to the memory, and the FIFO overflow control signal and link control circuit from the FIFO unit 1 is provided with a write enable generation circuit (22 in FIG. 1) that generates an FFIFO write enable signal based on a filter condition detection signal input from the bus data detection unit using the link control signal from as a generation condition.

  When the memory write control unit (32 in FIG. 1) detects the data write full state of the memory from the comparison result of the generated write pointer value and the memory read address, the memory write enable signal, and the FIFO read enable signal, the FIFO full flag is detected. A signal is written in a memory.

  Further, the bus monitor circuit adds a bus identification code addition circuit (4 in FIG. 1) for adding identification data unique to the system bus to the FIFO read data read from the memory, and adds a bus identification code by the FIFO read enable signal. A data multiplexing control unit (5 in FIG. 1) is provided which multiplexes the output of the circuit and outputs the bus monitor output.

  The first effect of the present invention is that the FIFO read enable signal that controls the read control of the memory of the FIFO unit continues the active state only for the memory that is not in the empty state, and the read control of the memory in the empty state is skipped. As a result, the read control that always maximizes the ratio of the read control to the write control of the memory that is not in the empty state is possible, and the retention time (period) of the extracted data of the memory, which determines the memory capacity, is reduced. This means that the scale of the monitor circuit can be reduced. In addition, because the empty memory is read control that is skipped, the extracted data of the observation target system bus is continuously output to the monitor, and the observer can easily observe the extraction data of the target system bus from the monitor output. It is possible to improve the data collection of the system bus to be observed.

  The second effect of the present invention is that the overflow information of the memory is output to the monitor together with the extracted data of the plurality of system buses to be observed detected by the bus data detection unit, and the observer observes the overflow information output by the monitor. By doing so, it becomes possible to check the bus data acquisition status of multiple observation target system buses, and easily identify the period (event) in which the extracted observation target system bus data was missed from the monitor output This means that the monitoring capability (efficiency) of the bus monitor circuit can be improved. In addition, it is possible to easily (re) set filter conditions and trigger conditions, which are detection / extraction conditions for the system bus to be observed, to appropriate conditions from the monitor output.

  The third effect of the present invention is that not only the trigger condition set for each of the plurality of system buses to be observed is set as the trigger detection condition for one observation system bus, but also the data extraction of the observation system bus A ( (Monitor output) is started by data detection of the observation target system bus B, and similarly, the combination of trigger conditions is stopped to stop the data extraction (monitor output) of the observation target system bus A by data detection of the observation target system bus C. Since the data of the target system bus can be extracted and the data to be extracted can be narrowed down based on the correlation between the different target system buses by selection, the data volume of the target system bus extracted by the bus monitor circuit can be reduced. Is to become. This also reduces the memory capacity of the FIFO unit, reduces the scale of the bus monitor circuit in the system integrated circuit, and restricts unnecessary data output from the monitor output of the system bus to be monitored. An effect of improving the monitoring capability (efficiency) of the observation target system bus by the circuit is also obtained, and it becomes possible to provide an advanced observation means.

  The fourth effect of the present invention is that the bus monitor circuit is configured by a circuit that controls the reading and writing of the FIFO and FIFO without using a complicated circuit such as a CPU or a DMA controller. The scale of the circuit can be reduced, and as a result, it is a bus monitor circuit that consists only of hardware and automatically outputs the collected data of multiple system buses to be observed. It becomes possible.

  The fifth effect of the present invention is a FIFO read enable in which a continuous active state is continued only for a memory that is not in an empty state for read control of a memory in which extracted data of a plurality of system buses to be observed are temporarily stored. Since signals are used, it is possible to easily multiplex the FIFO read data from the memory, and to reduce the circuit scale of the data multiplexing control unit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of configuration]
(1) Outline Description FIG. 1 shows a first embodiment of a bus monitor circuit of the present invention. This bus monitor circuit is a circuit that monitors and outputs the status of a plurality of system buses to be observed (bus monitor target) inside the integrated circuit to the outside of the integrated circuit. The bus data detection unit 1, FIFO write (Write) control 2, a FIFO unit 3, n bus identification code adding circuits 4, a data multiplexing control unit 5 and a FIFO read control unit 6.

  The bus data detection unit 1 monitors the data transmitted and received on the n system buses (1) to (n) to be observed, and the filter conditions set as detection / extraction conditions for each system bus , Data suitable for a trigger (start trigger, stop trigger) condition is extracted from data transmitted and received on the system buses (1) to (n). Then, the extracted data is used as system bus extraction data A, and detection signals for detection / extraction conditions used for data extraction (referred to as detection / extraction setting condition detection signals, each of n filter condition detection signals D and trigger condition detection). Output to the FIFO write controller 2 together with the signal E).

  The FIFO write control unit 2 is located at the subsequent stage of the bus data detection unit 1, adds time stamp information for each system bus extraction data A, and outputs it as FIFO write data B to the FIFO unit 3. The time stamp information is a count value of a counter that counts up freely regardless of the presence or absence of the system bus extraction data A. The filter condition detection signal D, the trigger condition detection signal E, and the FIFO full flag signal I from the FIFO unit 3 Is latched together with the system bus extraction data A as an enable signal.

  Also, the FIFO write control unit 2 uses the filter condition detection signal D and trigger condition detection signal E from the bus data detection unit 1 and the FIFO overflow control signal F from the FIFO unit 3 to correspond to the FIFO write data B. A write enable signal G is generated and output to the FIFO unit 3. As will be described later, the trigger condition detection signal E is detected corresponding to the system bus, and the FIFO write enable signal G is generated corresponding to the system bus, but the trigger condition detection signal E for one system bus is generated for the other system bus. A FIFO write enable signal G linked to the trigger condition detection signal E can also be used.

  The FIFO unit 3 is located after the FIFO write control unit 2 and includes n memories 31 provided corresponding to the system buses (1) to (n). Data B is stored by write control independently and sequentially corresponding to the system bus by the memory write enable signal J1 and the FIFO full flag signal I by the memory write enable signal J2. The FIFO full flag signal I indicates a data write state of the memory 31 as overflow information indicating a write error occurrence state to the FIFO unit 3.

  The FIFO write data B and the FIFO full flag signal I stored in the n memories 31 of the FIFO unit 3 are read for each memory 31 by the FIFO read enable signal P from the FIFO read control unit 6 as the FIFO read data C. The data is output to the data multiplexing control unit 5.

  The FIFO unit 3 outputs a memory write enable signal J1, a FIFO empty flag (Memory Empty Flag) signal N, and a FIFO Almost Empty Flag (FIFO Almost Empty Flag) signal O to the FIFO read control unit 6. The FIFO empty flag signal N is output when there is no data to be read in the memory (empty), and the FIFO almost-empty flag signal O is output when the next data is read. Is done.

  The FIFO read control unit 6 is located at the subsequent stage of the FIFO unit 3, and the memory write enable signal J 1, the FIFO empty flag signal N, the FIFO almost empty flag signal O, and the FIFO read control unit 6 from the FIFO unit 3. The FIFO read enable signal P generated in step 1 detects the data read state of the memory 31 of the FIFO unit 3 in advance, and generates a FIFO read enable signal P that is active only for the memory 31 that is not in the empty state. Output to part 3. In this case, the FIFO read enable signal P is skipped for the memory 31 that is in an empty state.

  The bus identification code adding circuit 4 is located after the FIFO unit 3 and adds identification data specific to the system bus to the FIFO read data C read from the memory 31 of the FIFO unit 3. This addition is for facilitating identification of the system bus extraction data multiplexed and monitored by the subsequent data multiplexing control unit 5. If the multiplexed system bus extraction data can be easily identified by an address or the like, this circuit is deleted.

  The data multiplex control unit 5 is located at the subsequent stage of the bus identification code adding circuit 4, and the FIFO read data C for each system bus is received from the FIFO read control unit 6 according to the FIFO read enable signal P from the FIFO read control unit 6. Multiplexed by the read enable signal P and output to the outside of the integrated circuit as a bus monitor output.

  As described above, the bus monitor circuit of the present invention uses the FIFO write control unit 2 to add the time stamp information to the system bus extraction data A extracted for each of a plurality of system buses to be observed by the bus data detection unit 1. Overflow information is added by the FIFO unit 3, and write control for writing to the memory 31 of the FIFO unit 3 is performed based on the FIFO write enable signal G output from the FIFO write control unit 2.

  Then, read control for reading the system bus extraction data to which the time stamp information and overflow information written in the memory 31 is added is performed by the FIFO read enable signal P output from the FIFO read control unit 6. Further, a unique identification code is added to the FIFO read data C read from the memory 31 by the bus identification code adding circuit 4 located at the subsequent stage of the FIFO unit 3, and the FIFO read enable is performed in the data multiplexing control unit 5. The FIFO read data C is multiplexed by the signal P, and is output to the outside of the integrated circuit as a monitor output of a plurality of system bus states to be observed inside the integrated circuit.

(2) Detailed Description Details of the FIFO write control unit 2, the FIFO unit 3, and the FIFO read control unit 6 will be described below.

  The FIFO write control unit 2 includes a latch & time stamp addition circuit 21, a write enable generation circuit 22, and a link control circuit 23.

  The latch time stamp adding circuit 21 uses the filter condition detection signal D, the trigger condition detection signal E from the bus data detection unit 1 and the FIFO full flag signal I from the FIFO unit 3 as enable conditions, and the bus data detection unit 1 The system bus extraction data A and the internally generated time stamp information are latched, and n FIFO write data B are output to the FIFO unit 3.

  The link control circuit 23 performs combination control or selection control in accordance with the set link information with respect to the input of n trigger condition detection signals E from the bus data detection unit 1, and the system bus for the memory 31 of the FIFO unit 3. A link control signal H for controlling the writing start and writing end of the extracted data is generated and output to the write enable generation circuit 22.

  The write enable generation circuit 22 uses the n FIFO overflow control signals F from the FIFO unit 3 and the link control signal H from the link control circuit 23 as generation conditions, based on the filter condition detection signal D from the bus data detection unit 1. N FFIFO write enable signals G used for write control in the FIFO unit 3 are generated.

  The FIFO unit 3 includes n memories 31, n memory write control circuits 32, and n memory read control circuits 33 provided corresponding to the n system buses to be observed. However, in FIG. 1, only one set of the memory write control circuit 32 and the memory read control circuit 33 is shown in order to avoid complication of the drawing.

  The memory 31 includes a system bus extraction data memory for storing the FIFO write data B and an overflow information memory for storing the FIFO full flag signal I. The FIFO full flag signal I is a signal indicating the data write state of the n memories 31 as overflow information indicating a write error occurrence state to the FIFO unit 3.

  The memory write control circuit 32 includes a write control circuit 321, an overflow control circuit 322, and a memory full detection circuit 323.

  The write control circuit 321 generates the write pointer value L and the memory read enable signal J1 using the FIFO write enable signal G from the FIFO write control unit 2 as an enable condition and the FIFO full flag signal I as a generation condition. The write pointer value L is output to the memory read control circuit 33, and the memory write enable signal J1 is output to the system bus extraction data memory of the memory 31, the memory read control circuit 33, and the FIFO read control unit 6.

  The overflow control circuit 322 generates the FIFO overflow control signal F, the memory write enable signal J2, and the memory write address K using the FIFO write enable signal G from the FIFO write control unit 2 as an enable condition and the FIFO full flag signal I as a generation condition. . The FIFO overflow control signal F is sent to the write enable generation circuit 22 of the FIFO write control unit 2, the memory write enable signal J2 is sent to the overflow information memory of the memory 31, and the memory write address K is sent to the system bus extraction data memory and overflow information memory of the memory 31, respectively. Is output.

  The memory full detection circuit 323 is based on the comparison result of the write pointer value L and the memory read address M from the memory read control unit 33, and the state of the memory read enable signal J1 and the FIFO read enable signal P from the FIFO read control unit 6. The data write full state of the memory 31 is detected and the FIFO full flag signal I is output to the FIFO write control unit 2.

  The memory read control unit 33 includes a read control circuit 331, a memory empty detection circuit 332, and a memory almost empty detection circuit 333.

  The read control circuit 331 generates a memory read address M using the FIFO read enable signal P from the FIFO read control unit 6 as an enable condition, and outputs it to the memory 31 and the memory write control unit 32.

  The memory empty detection circuit 332 detects the data read empty state of the memory 31 based on the comparison result between the write pointer value L and the memory read address M, and the state of the memory write enable signal J1 and the FIFO read enable signal P, and detects the FIFO empty state. The flag signal N is output to the FIFO read control unit 6.

  Similarly, the memory / almost / empty detection circuit 333 detects the data read / almost / empty / empty state of the memory 31 and outputs the FIFO / almost / empty flag signal O to the FIFO read control unit 6. As described above, the write pointer value L is used to detect the full state, the empty state, and the almost-empty state of the memory 31. The memory read enable signal J1 is used not only for writing the FIFO write data B to the system bus extraction data memory, but also for detecting an empty state and an almost-empty state of the memory 31.

  As shown in FIG. 2, the memory write control unit 32 and the memory read control unit 33 are provided in a one-to-one correspondence with the n memories 31a to 31n, and the n FIFO write enable signals G and n In response to the FIFO read enable signal P, the write control of n FIFO write data B and the output of n FIFO read data C by read control are performed independently for each of the memories 31a to 31n, and the FIFO full flag signal I, FIFO empty flag signal N, and FIFO ormost empty flag signal O are also output for each of the memories 31a to 31n.

  When the FIFO write data B is written by the FIFO write enable signal G when the memory 31 is full, the overflow information indicating the occurrence of the write error of the FIFO write data B is overwritten in the overflow information memory of the memory 31. Write control is performed.

  The FIFO write data B and overflow information stored in the system bus extraction data memory and overflow information memory of the memories 31a to 31n are read only to the FIFO which is not in an empty state by n FIFO read enable signals P. Control is performed, the FIFO is read, and data C is output to the data multiplexing control unit 5.

  The FIFO read control unit 6 includes a read enable generation circuit 61 and a FIFO state detection circuit 62.

  The FIFO state detection circuit 62 includes a FIFO empty flag signal N from the FIFO unit 3, a FIFO almost empty flag signal O and a FIFO write enable signal J1, and a FIFO read enable from the read enable generation circuit 61 of the FIFO read control unit 6. The signal P is constantly monitored, and the data read state of the memory 31 after the read / write control is detected and detected by the FIFO write enable signal J1 and the FIFO read enable signal P before and after the read / write control. .

  The read enable generation circuit 61 becomes active only for the memory 31 that is not in the empty state by the FIFO state detection signal Q indicating the data reading state of all the memory 31 from the FIFO state detection circuit 62, and for the memory 31 in the empty state. The FIFO read enable signal P, which is in a disabled state, is generated and output to the memory write control unit 32, the memory read control unit 33, the data multiplexing control unit 5 and the FIFO state detection circuit 62 of the FIFO unit 3.

  As described above, the FIFO read control unit 6 continues the n FIFO read enable signals P in which the active state continues only for the memory 31 that is not in the empty state until all the memories 31 are in the empty state. The data read state of the n number of memories 31 is determined from the read-ahead detection result every time the read control performed for the memory 31 that is not in the empty state makes a round, and the empty state in which the next read control is performed. By identifying the memory 31 that is not present, reading to the memory 31 in the empty state is skipped, and read control can be performed only on the memory 31 that is not in the empty state.

[Description of operation]
Next, the operation of the bus monitor circuit configured as described above will be described separately for the case of writing extracted data to the FIFO and reading the write data of the FIFO.

(1) Writing extracted data to FIFO First, the bus data detection unit 1 monitors bus data transmitted / received on the n system buses (1) to (n) to be observed and detects them for input. By detecting bus data that matches the filter condition set as the condition, and by detecting bus data that matches the trigger condition set as the extraction condition, start extraction of the bus data detected by the filter condition (start trigger) Condition) and stop extraction (stop trigger condition). The n system bus extraction data A, the filter condition detection signal D, and the trigger condition detection signal E are output to the FIFO write control unit 2. The operation of writing the extracted data to the FIFO is performed by the FIFO write control unit 2 and the memory write control unit 32 of the FIFO unit 3.

  In the FIFO write control unit 2, the latch time stamp adding circuit 21 provided therein includes n filter condition detection signals D, n trigger condition detection signals E from the bus data detection unit 1, and FIFO unit 3. Using the n FIFO full flag signals I from the memory full detection circuit 323 as enable conditions, the n system bus extraction data A are individually latched for each system bus. Further, as time stamp information indicating the fetch time of the system bus extraction data A, the value of the counter provided in the latch time stamp addition circuit 21 is set for each system bus under the same latch enable condition as the system bus extraction data A. Latch individually. The latched system bus extraction data A is added with time stamp information and is output to the FIFO unit 3 as n FIFO write data B. In addition, the FIFO write control unit 2 generates n FIFO write enable signals G and outputs the FIFO write data B to the FIFO unit 3 in order to write the FIFO write data B to the n memories 31.

  Generation of the FIFO write enable signal G will be described with reference to FIG. The link control circuit 23 generates a link control signal H based on the trigger condition detection signal E from the bus data detection unit 1. That is, the first trigger of the trigger condition detection signal E is set as a start trigger and the second as a stop trigger. The write enable generation circuit 22 shifts the filter condition detection signal D from the bus data detection unit 1 using the link control signal H as an enable condition for timing adjustment with the system bus extraction data. The FIFO write enable signal G is generated by performing mask control with the FIFO overflow control signal F from the overflow control circuit 322 of the FIFO unit 3. 3, the filter condition detection signals D1, D2, D10 and D11 while the link control signal H is “L”, and the filter condition detection signals D6 and D7 masks when the FIFO overflow control signal F is “H”. The filter condition detection signals D3, D4, D5, D8, and D9 are shifted to FIFO write enable signals G1, G2, G3, G4, and G5.

  The trigger condition detection signal E used to generate the link control signal H in the link control circuit 23 is a signal detected for each of a plurality of system buses to be observed. Combination control and selection control can be performed, and the result is reflected in the FIFO write enable signal G, and the FIFO write data B is written in the FIFO unit 3. Therefore, as shown in FIG. The system bus data can be extracted and the data to be extracted can be narrowed down.

  The upper part of FIG. 4 shows the case where there is no link condition setting. A filter trigger match data 1 to 7 on the system bus A, B filter trigger match data 8 to 10 on the system bus B, and C on the system bus C. All of the filter trigger match data 11 to 12 are output to the bus monitor in time series. On the other hand, the lower part of FIG. 4 shows the case where the link condition is set. The C filter trigger match data 11 is set as the A filter trigger match data 3 as the start link destination, and the B filter trigger match is set as the A filter trigger match data 6 as the stop link destination. Data 10 is set. In this case, only the A filter trigger match data 3 to 6, the B filter trigger match data 9, 10, and the C filter trigger match data 11, 12 are output to the bus monitor.

  In the write control circuit 321 in the memory write control unit 32, the FIFO full flag signal I from the memory full detection circuit 323 counts up with the FIFO write enable signal G when the memory full is not detected, and counts when the memory full is detected. A write pointer is provided to stop up. The count value of the write pointer is output as the write pointer value L to the read control circuit 331 of the memory read control unit 33.

  In order to stop the write control to the memory 31 when the memory full is detected, the FIFO write enable signal from the FIFO write control unit 2 is used by using the FIFO full flag signal I in the write control circuit 321 as shown in the lower part of FIG. A memory write enable signal J1 subjected to mask control for G is output to the system bus extraction data memory of the memory 31. In FIG. 3, the FIFO write enable signal G3 is masked in the FIFO write enable signal G, and the memory write enable signals J1-1, J1-2, J1-4, and J1-5 are output as the memory write enable signal J. ing.

  The FIFO full flag signal I indicating the full state of the memory 31 is detected by the memory full detection circuit 323 based on the comparison result between the write pointer value L and the memory read address M and the states of the memory write enable signal J1 and the memory read enable signal P. The FIFO write control circuit 321, the overflow control circuit 322, and the overflow information memory of the memory 31 are output.

  The use of the FIFO full flag signal I in the write control circuit 321 is as described above. As shown in the lower part of FIG. 3, the FIFO full flag signal I output to the overflow control circuit 322 is shifted to enable the FIFO write enable signal G and differentiated to obtain the FIFO overflow control signal F as the FIFO write control unit 2. Is output to the write enable generation circuit 22.

  The FIFO full flag signal I is written to the overflow information memory of the memory 31 as overflow information data indicating the occurrence of a write error when writing data to the FIFO unit 3. The control is performed by the overflow control circuit 322 of the memory control unit 32. When the FIFO write enable signal G is input when the memory full is detected, the address of the overflow information memory in which the overflow non-occurrence information is written immediately before the memory full is detected. Thus, the overwrite control is performed to overwrite the FIFO full flag signal I as overflow occurrence information.

  In the lower part of FIG. 3, the memory write address K output from the overflow control circuit 322 as the write address of the memory 31 is the same value as the write pointer value L generated by the write control circuit 321 when the memory full state is not detected. Yes, when the memory full detection circuit 323 detects the memory full state and outputs the memory full detection signal I, the memory full detection signal I is used as a select control signal to switch to the memory write address value immediately before the memory full state is detected. Is output. In FIG. 3, the memory write address K should be changed from (n−1) to n, but is retained while the FIFO full flag signal I is “H”.

  The overwrite control shown in FIG. 5 is performed by the memory write address K which is switched when the memory is full and the FIFO write enable signal G which is not masked by the FIFO overflow control signal F when the memory is full. FIG. 5 is an operation schematic diagram showing the operation of the overwrite control performed by the overflow control circuit 322.

  In FIG. 5, the system bus data 1 to (N-1) written in the memory 31 is not read-controlled, and the system bus data N is controlled to be written ((1) in FIG. 5). Shows the state in which the system bus data is written, and at this time, the FIFO full flag signal I is generated ((2) in FIG. 5).

  In this state, if the next system bus data (N + 1) is write-controlled to the memory 31 without reading the system bus data 1 to N ((3) in FIG. 5), the FIFO is fully detected. Since the system bus data is write-controlled, a value (FIFO full flag signal I) indicating the occurrence of overflow is overwritten in the overflow information bit storage area of the system bus data N to be overflow control (FIG. 5). (4)). After the occurrence of overflow control, when system bus data write control is performed without performing read control on the memory 31, the system bus data (N + 1) is discarded (FIG. 5). (5)).

(2) Reading FIFO write data
The FIFO write data read operation is performed by the FIFO read control unit 6 and the memory read control unit 33 of the FIFO unit 3.

  The FIFO read control unit 6 includes a FIFO empty flag signal N from the memory empty detection circuit 332 of the FIFO unit 3, a FIFO almost empty flag signal O from the memory almost empty detection circuit 333, and a write control circuit 321. The FIFO state detection circuit 62 constantly monitors the memory write enable signal J1 and the FIFO read enable signal P from the read enable generation circuit 61 of the FIFO read control unit 6.

  Then, the memory read enable signal J1 from the FIFO empty flag signal N and the data read state of the memory 31 after the read / write control by the FIFO read enable signal P are detected. Also, before the read / write control by the FIFO write enable signal J and the FIFO read enable signal P is performed, the read from the FIFO almost empty flag signal O, the memory write enable signal J1, and the FIFO read enable signal P is read. / The data read state of the memory 31 after the write control is pre-read and detected.

  The result detected by the FIFO state detection circuit 62 is generated as a FIFO state detection signal Q indicating the data read state of all the memories 31. This generation cycle is continuously repeated until all the memories 31 are in an empty state, with one period as a unit for continuously performing read control for each memory 31 that is not in an empty state without competition. It is. The FIFO state detection signal Q is input to the read enable generation circuit 61 and is used between generation cycles of the FIFO read enable signal P that is continuously repeated as shown in FIG.

  That is, the FIFO state detection signal Q is used as a generation condition of the FIFO read enable signal P in the next generation cycle at the same time when the last FIFO read enable signal P in one generation cycle becomes active. At the same time as the FIFO read enable signal P that has become active becomes disabled, control is performed to activate the first FIFO read enable signal P in the next generation cycle.

  In FIG. 6, the memory write enable signal J1 is “L” from the first to fifth read enable generation cycles. In the first read enable generation cycle, since all the FIFO empty flag signals N1 to N5 are “L”, all the FIFO read enable signals P1 to P5 are active. In the second read enable generation cycle, the FIFO empty flag signal N2 becomes “H”, but since this is after the read control, the FIFO read enable signals P1 to P5 remain active in this cycle.

  In the third read enable generation cycle, since the FIFO empty flag signal N2 is maintained at “H”, the FIFO read enable signal P2 is disabled by detection after the read control. Further, since the FIFO empty flag signal N5 is “H” at the start of the cycle, the FIFO read enable signal P5 is disabled due to the prefetch detection before the read control. Further, although the FIFO empty flag signal N3 becomes “H”, since it is after the read control, the FIFO read enable signal P3 is not disabled in this cycle.

  In the fourth read enable generation cycle, since the FIFO empty flag signals N2, N3, and N5 are maintained at “H”, the FIFO read enable signals P2, P3, and P5 are disabled. Further, the FIFO empty flag signal N1 becomes “H”, but since this is after the read control, the FIFO read enable signal P1 is not disabled in this cycle.

In the fifth read enable generation cycle, since the FIFO empty flag signals N1, N2, N3, and N5 are maintained at “H”, the FIFO read enable signals P1, P2, P3, and P5 are disabled. Since the FIFO empty flag signal N4 maintains “L”, the FIFO read enable signal P4 remains active. In this active state, the FIFO empty flag signal N4 becomes “H” or one of the FIFO empty flag signals N1, N2, N3, and N5.
It lasts until one or more becomes “L”. That is, the FIFO read enable signal P in the case where there is one memory 31 that is not in the empty state is an output that holds the active state until the memory 31 becomes empty or there are two or more memories 31 that are not empty. Become.

  In FIG. 6, the FIFO empty flag signals N1, N2, N3, and N5 are “H” until the seventh read enable generation cycle, but the memory write enable signal J1 is “H” in the seventh read enable generation cycle. Accordingly, in the eighth read enable generation cycle, the FIFO empty flag signal N1 becomes “L” due to the prefetch detection of the data read state of the memory 31. Therefore, in the subsequent read enable generation cycles, the FIFO read enable signals P1 and P4 remain active. However, when the right end of FIG. 6 is approached, the FIFO empty flag signal N1 becomes “H” again, the FIFO empty flag signal N4 also becomes “H”, and all the memories 31 become empty. The read enable signal is gone.

  Thus, the read control of the memory 31 is continuously performed only for the memory 31 that is not in the empty state, and is skipped for the memory 31 that is in the empty state. FIG. 7A shows that not all of the memories 1 to N are in an empty state, and therefore the FIFO read enable signal is repeatedly output to all of the memories 1 to N. However, FIG. 7B shows that the memory 1 and the memory (N-1) are in an empty state, and the FIFO read enable signal for the memory 1 and the memory (N-1) is skipped.

  The read control circuit 331 in the memory read control unit 33 is provided with a read pointer that counts up by the FIFO read enable signal P when the memory empty is not detected and stops counting up when the memory empty is detected. The count value is output to the memory 31 as the memory read address M.

  Further, the FIFO empty detection signal N detected by the memory empty detection circuit 332, and the FIFO almost empty detection signal O detected by the memory / almost / empty detection circuit 333 are the read pointer value of the read control circuit 331, the memory write It is generated based on the comparison result of the write pointer value L from the write control circuit 321 of the control unit 32 and the state of the memory write enable signal J1 and the memory read enable signal P.

  The read data multiplexing operation is performed by the data multiplexing control unit 5. The data multiplex control unit 5 is read out from the FIFO unit 3) using the n FIFO read enable signals P from the FIFO read control unit 6 as a select control signal, and the bus identification code addition circuit 4 performs the reading for each observation system bus. A simple operation of the n to 1 select circuit that multiplexes n FIFO read data C, to which a unique code is added, into one data string is performed.

  FIG. 8 shows a second embodiment of the bus monitor circuit of the present invention. This bus monitor circuit has the same basic configuration as the above-described bus monitor circuit, but devised a monitor output method when the number of integrated circuit terminals allocated to the monitor output from the bus monitor circuit is limited. Yes.

  Referring to FIG. 8, this bus monitor circuit has a configuration in which a second FIFO unit 7 and a parallel / serial conversion unit 8 are added to the final stage of the lower bus monitor circuit shown in FIG. The added parallel / serial conversion unit 8 is a control function unit for dividing the data width of the system bus to be observed into set data widths for serial output, and the second FIFO unit 7 The speed adjustment is performed between the data extraction speed of the system bus to be observed from the data multiplexing control unit 5 and the serial output speed that is divided by the parallel / serial conversion unit 8 and output to the outside of the integrated circuit. It is a control function part to perform.

  The second FIFO unit 7 is a FIFO unit that deletes only the memory / almost / empty detection function of the FIFO unit 3 and has the same other functions. Therefore, overflow control is possible, and the bus monitor multiplexed data R from the data multiplexing control unit 5 is stored using the read enable signal P of the FIFO unit 3 as a write enable signal.

  The parallel / serial conversion unit 8 constantly monitors the second FIFO empty flag signal U output from the second FIFO unit 7, and the bus monitor multiplexed data R from the data multiplexing control unit 5 is written to the second FIFO unit 7 to be in an empty state. When the second FIFO read enable signal T is detected, the bus monitor multiplexed data R stored in the second FIFO unit 7 is read out as the second FIFO read data S. At the same time, the second FIFO read data S is latched by the parallel / serial converter 8 and the second FIFO read data S divided by the set data width is monitored and output as serial output data from the bus monitor circuit.

  The second FIFO read enable signal T output from the parallel / serial conversion unit 8 to the second FIFO unit 7 is latched by the parallel / serial conversion unit 8, and all the second FIFO read data S divided by the set data width are serial. Until the data is output, the generation and output of the second FIFO read enable signal T is stopped even when the bus FIFO multiplexed data R is stored in the second FIFO unit 7 and is not in an empty state.

  For this reason, the second FIFO read enable signal T generated and output from the parallel / serial conversion unit 8 is data set with the second FIFO read data S read from the second FIFO unit 7 and latched in the parallel / serial conversion unit 8. It is generated for each final cycle divided into widths and serially output, and is output to the second FIFO unit 7. The parallel / serial converter 8 has a padding function for the case where the data widths of a plurality of system buses to be observed are different, and the data extracted from the system bus to be observed is divided and output. The number of output cycles to be serially output is variable.

  Therefore, although there is a demerit that the memory capacity of the FIFO section of the entire bus monitor is increased by the memory capacity of the added second FIFO section 7, the bus monitor output signal output from the bus monitor circuit and connected to the terminal of the integrated circuit As shown in FIG. 9, the signal width can be reduced. FIG. 9 shows an example in which the signal width of the data multiplexing control unit output is n bits, and the signal width of the bus monitor output signal connected to the terminal of the integrated circuit is 4 bits. Is m (= n / 4) times every 4 bits.

1 is a block diagram showing a first embodiment of a bus monitor circuit of the present invention. Detailed block diagram of FIFO unit 3 in the first embodiment Timing chart of FIFO write operation in embodiment 1 The figure which shows the bus monitor output by the link setting conditions in the link control circuit 23 in Example 1. Schematic of overflow control by FIFO unit 3 overflow control circuit 322 in the first embodiment Timing chart for generating FIFO read enable signal P in the first embodiment Schematic of memory read control in Embodiment 1 Block diagram showing a second embodiment of the bus monitor circuit of the present invention Comparison diagram of bus monitor output in Example 1 and Example 2 Block diagram showing an example of the prior art Block diagram showing another example of the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bus data detection part 2 FIFO write control part 3 FIFO part 4 Bus identification code addition circuit 5 Data multiplexing control part 6 FIFO read control part 7 Second FIFO part 8 Parallel / serial conversion part
21 Latch time stamp addition circuit
22 Write enable generation circuit
23 Link control circuit
31,31a to 31n memory
32, 32a to 32n Memory write controller
33,33a to 33n Memory read controller
61 Read enable generation circuit
62 FIFO status detection circuit
321 Light control circuit
322 Overflow control circuit
323 Memory full detection circuit
331 Lead control circuit
332 Memory Empty Detection Circuit
333 Memory Almost Empty Detection Circuit A System Bus Extracted Data B FIFO Write Data C FIFO Read Data D Filter Condition Detection Signal E Trigger Condition Detection Signal F FIFO Overflow Control Signal G FIFO Write Enable Signal H Link Control Signal I FIFO Full Flag Signal J1 , J2 Memory write enable signal K Memory write address L Write pointer value M Memory read address N FIFO empty flag signal O FIFO almost empty flag signal P FIFO read enable signal Q FIFO status detection signal R Bus monitor multiplexed data S Second FIFO read Data T Second FIFO read enable signal U Second FIFO empty flag signal

Claims (4)

In a bus monitor circuit that monitors and outputs the status of at least one system bus to be observed,
A bus data detection unit for extracting data suitable for a filter condition for detecting data transmitted and received on the system bus and a trigger condition for controlling extraction start and stop of the detected data from the system bus;
A FIFO unit having a one-to-one correspondence with the system bus to store the bus data extraction data;
A FIFO write control unit that generates a FIFO write enable signal and outputs the FIFO data together with the bus data extraction data to the FIFO unit;
A FIFO read control unit that generates a FIFO read enable signal and outputs it to the FIFO unit,
The FIFO unit has a one-to-one correspondence with the memory.
A memory write control unit that generates a memory write enable signal and a memory write address when the FIFO write enable signal is input, and outputs the memory write address to the memory;
When the FIFO read enable signal is input, a memory read address is generated and output to the memory. Also, a FIFO empty flag signal indicating the read empty state of the memory, and the read empty state when the memory is read next time. A memory read control unit is provided that outputs a FIFO ormost empty flag signal indicating the read or most empty state to be the FIFO read control unit,
The FIFO read control unit activates only a FIFO read enable signal for a memory that does not indicate an empty state by the FIFO empty flag signal and the FIFO almost empty flag signal. . The FIFO light control unit
Controlling the start and end of writing of the system bus extraction data to the memory by logically combining a plurality of trigger condition detection signals corresponding to the system bus indicating that the detected data meets the trigger condition A link control circuit for generating a link control signal of
Using the FIFO overflow control signal from the FIFO unit and the link control signal from the link control circuit as a generation condition, the FFIFO is detected by a filter condition detection signal indicating that data transmitted and received on the system bus meets the filter condition. 2. The bus monitor circuit according to claim 1, further comprising a write enable generation circuit for generating a write enable signal.
  When the memory write control unit detects a data write full state of the memory based on a comparison result between the write pointer value to be generated and the memory read address, and the memory write enable signal and the FIFO read enable signal, the memory write control unit outputs a FIFO full flag signal. 3. The bus monitor circuit according to claim 1, wherein the bus monitor circuit is written in a memory. A bus identification code adding circuit for adding identification data specific to the system bus to the FIFO read data read from the memory;
4. The bus monitor circuit according to claim 1, further comprising a data multiplex control unit that multiplexes the output of the bus identification code adding circuit in response to the FIFO read enable signal and outputs the bus monitor output.

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