JP4882962B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device that enables miniaturization of a pixel size without reducing a saturation charge amount (Qs) or a sensitivity.

  As a solid-state imaging device, a CMOS type solid-state imaging device is known. This CMOS type solid-state imaging device is configured by forming one pixel by a photodiode and a plurality of transistors, so-called MOS transistors, and arranging the plurality of pixels in a required pattern. The photodiode is a photoelectric conversion element that generates and accumulates signal charges according to the amount of received light, and the plurality of MOS transistors are elements for transferring signal charges from the photodiodes.

  FIG. 8 shows an example of a conventional CMOS solid-state imaging device applied to an image sensor. FIG. 8 shows the main part of the pixel. In this CMOS type solid-state imaging device 51, a pixel isolation region 65 for partitioning each pixel is formed on the surface side of a first conductivity type, for example, p-type silicon semiconductor substrate 52, and a plurality of photodiodes 53 and a plurality of photodiodes 53 are formed in each partition region. The unit pixel 60 is formed by forming four MOS transistors, that is, a charge readout transistor 54, a reset transistor 55, an amplifier transistor 56, and a vertical selection transistor (not shown). A large number of the pixels 60 are arranged in a two-dimensional matrix.

  The photodiode 53 includes a second conductivity type n-type semiconductor region 61 [n + region 61a, n region 61b] formed by ion implantation from the surface of the p-type semiconductor substrate 52 to a required depth, and the n-type semiconductor. A p-type semiconductor region (p + region) 62 having a high impurity concentration formed on the surface of the region 61 is formed.

Each MOS transistor 54, 55, 56 is configured as follows. High impurity concentration n-type semiconductor regions, that is, n + source / drain regions 57, 58 and 59 are formed on the surface of the p-type semiconductor substrate 52 by ion implantation so as to be adjacent to the photodiode 53.
The charge readout transistor 54 is formed via the gate insulating film 71 on the n + source / drain region 57, the high impurity concentration n + region 61a on the surface side of the photodiode 53, and the substrate 52 between the regions 57 and 61a. And a gate electrode 72.
The reset transistor 55 includes n + source / drain regions 57 and 58 and a gate electrode 73 formed on the substrate 52 between the regions 57 and 58 via a gate insulating film 71. Here, the n + source / drain region 57 is called floating diffusion (FD).
The amplifier transistor 56 includes n-type source / drain regions 58 and 59 and a gate electrode 74 formed on the substrate 52 between the regions 58 and 59 via a gate insulating film 71.
Although not shown, the vertical selection transistor is composed of a pair of source / drain regions and a gate electrode formed on the substrate 52 therebetween via a gate insulating film.

  Since the circuit wiring of each MOS transistor described above is the same as that described later, description thereof is omitted. The n-type source / drain region 58 that connects the reset transistor 55 and the amplifier transistor 56 of each pixel is connected to the power supply wiring 76 via the connection conductor 75. Further, a multilayer wiring 77 including a power supply wiring 76 is formed on the substrate 52 via an interlayer insulating film 78.

  In the CMOS type solid-state imaging device 51, light is incident on the photodiode 53 from the surface side of the semiconductor substrate 52, and photoelectric conversion is performed in the photodiode 53 to accumulate signal charges corresponding to the amount of received light.

Also in FIG. 5 of Patent Document 1, a solid-state MOS image sensor in which a photodiode, a charge readout transistor, a reset transistor, an amplifier transistor, and a vertical transfer transistor constituting the unit pixel as described above are formed on the same plane on the same substrate. An image sensor has been proposed (see Patent Document 1 and FIG. 5).
JP-A-11-122532

  In the above-described CMOS solid-state imaging device 51, miniaturization is performed in order to highly integrate a large number of pixels 60. In particular, in each pixel region, a plurality of transistors such as a photodiode 53 and a charge readout transistor are provided on the same plane. In order to arrange, the area on a plane is needed respectively, and the area of one pixel tends to increase. For this reason, it is difficult to reduce the pixel size, or when the pixel size is reduced, the area of the photodiode 53 is reduced, thereby reducing the saturation charge amount (Qs) and the sensitivity. There were problems such as mixing.

  In view of the above, the present invention provides a solid-state imaging device capable of miniaturizing the pixel size without reducing the saturation charge amount (Qs) or the sensitivity.

In a solid-state imaging device according to the present invention, a pixel including a photodiode and a transistor is formed on a semiconductor substrate, a transistor is formed on the surface of the semiconductor substrate, and a pn junction formed between the high-concentration regions of the photodiode is a semiconductor substrate. And a part of the pn junction of the photodiode is formed so as to extend below the transistor formed on the surface of the semiconductor substrate , and the charge for reading out the signal charge of the photodiode in the pixel The channel portion of the read transistor is formed in the depth direction with respect to the surface of the semiconductor substrate, and in the portion corresponding to the bottom of the gate electrode of the charge read transistor, the second conductivity type semiconductor region and the charge read transistor constituting the photodiode A first conductivity type constituting a photodiode between the gate insulating film and In a state in which separated from the semiconductor region, a first conductivity type or semiconductor regions of the second conductivity type is formed, characterized in that incident from the back surface of the semiconductor substrate a light to the photodiode.

As a preferred embodiment of the solid-state imaging device of the present invention, it is appropriate to form the gate electrode of the charge readout transistor and the bottom of the gate insulating film at a position deeper than the depth of the pn junction of the photodiode.

As a preferred form of the solid-state imaging device of the present invention, it is appropriate to position the gate electrode corresponding to the connection portion between the charge readout transistor and the photodiode in the central portion of the photodiode.
As a preferred form of the solid-state imaging device of the present invention, it is appropriate to make one second conductivity type source / drain region of the charge readout transistor also serve as the second conductivity type semiconductor region constituting the photodiode.

As a preferred embodiment of the solid-state imaging device of the present invention, the second conductivity type semiconductor region constituting the photodiode formed by ion implantation and the other second conductivity type formed on the surface of the semiconductor substrate of the charge readout transistor. the distance between the source and drain regions, Ru is suitably der to determine the effective channel length of the charge readout transistor.

  As a preferred embodiment of the solid-state imaging device of the present invention, the first conductivity type high-concentration semiconductor region constituting the photodiode and the gate insulating film of the charge readout transistor have a lower concentration than the high-concentration semiconductor region. It is appropriate to form a semiconductor region of one conductivity type.

  According to the solid-state imaging device of the present invention, the pn junction formed between the high-concentration regions of the photodiode is provided inside the semiconductor substrate so as to extend partially below the transistor formed on the semiconductor surface. Thus, even if the pixel area is reduced, the area of the photodiode can be maintained large. Therefore, the pixel size can be reduced without reducing the saturation charge amount (Qs) and sensitivity.

In the pixel, by forming the channel portion of the charge readout transistor in the depth direction with respect to the surface of the semiconductor substrate, the transistor and the photodiode can be formed in three dimensions so as to overlap each other, thereby increasing the area of the photodiode. Thus, the pixel size can be reduced.
By forming the gate electrode of the charge readout transistor and the bottom of the gate insulating film at a position deeper than the depth of the pn junction of the photodiode, the channel portion is reliably formed between the photodiode and the source / drain region, The operation of the charge readout transistor can be ensured.

By forming the gate electrode of the charge readout transistor at the center of the photodiode, the distance between the periphery of the photodiode and the gate electrode can be made the same, and all the signal charges of the photodiode remain untransferred. And efficiently transferred to the charge readout transistor.
Since the second conductivity type source / drain region of one of the charge readout transistors also serves as the second conductivity type semiconductor region constituting the photodiode, the effective channel length of the charge readout transistor can be determined.

The distance between the second conductivity type semiconductor region of the photodiode formed by ion implantation and the other second conductivity type source / drain region formed on the substrate surface of the charge readout transistor is the effective channel length is determined, even if there is some variation in the bottom position of the gate electrode of the charge readout transistor, no variation in the effective channel length, Ru can this be provided a highly reliable solid-state imaging device.

  The charge storage capacity of the photodiode is maintained by forming a first conductivity type semiconductor region having a lower concentration than the high concentration semiconductor region between the first conductivity type high concentration semiconductor region of the photodiode and the gate insulating film. However, it is possible to facilitate the transfer of the signal charge in the charge reading transistor.

  A semiconductor region of the first conductivity type or the second conductivity type is formed between the second conductivity type semiconductor region of the photodiode and the gate insulating film of the charge read transistor in a portion corresponding to the bottom of the gate electrode of the charge readout transistor. By doing so, it is possible to suppress the occurrence of leakage current due to a defect of the photodiode. Further, by forming a first conductivity type semiconductor region having a lower concentration than the high concentration semiconductor region between the first conductivity type high concentration semiconductor region of the photodiode and the gate insulating film, the charge storage capacitor of the photodiode is formed. It is possible to facilitate the transfer of signal charges in the charge reading transistor.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2 shows an embodiment of an equivalent circuit of a unit pixel applied to a solid-state imaging device according to the present invention, that is, a CMOS solid-state imaging device. As shown in FIG. 2, the unit pixel 20 of the CMOS type solid-state imaging device includes a photodiode 3 and four MOS transistors, that is, a charge readout transistor 4, a reset transistor 5, an amplifier transistor 6, and a vertical selection transistor 7. Is done. The photodiode 3 is connected to one main electrode of the charge reading transistor 4, and the other main electrode of the charge reading transistor 4 is connected to one main electrode of the reset transistor 5. The other main electrode of the reset transistor 5 is connected to one main electrode of the amplifier transistor 6, and the other main electrode of the amplifier transistor 6 is connected to one main electrode of the vertical selection transistor 7.

An FD (floating diffusion) corresponding to the midpoint of connection between the charge readout transistor 4 and the reset transistor 5 is connected to the gate electrode of the amplifier transistor 6. The midpoint of connection between the reset transistor 5 and the amplifier transistor 6 is connected to the power supply wiring 8 from the power supply Vdd. Further, the other main electrode of the vertical selection transistor 7 is connected to the vertical signal line 9. A horizontal selection transistor 17 is connected between the vertical signal line 9 and a horizontal signal line (not shown).
A vertical read pulse φTG is applied to the gate electrode of the charge read transistor 4, a reset pulse φR is applied to the gate electrode of the reset transistor 5, and a vertical select pulse φSEL is applied to the gate electrode of the vertical select transistor 7. The

  A large number of such unit pixels 20 are arranged in a two-dimensional matrix to constitute a CMOS solid-state imaging device.

  In the unit pixel 20, signal charges are accumulated in the photodiode 4 by photoelectric conversion. When the vertical read pulse φTG is applied to the gate electrode of the charge read transistor 4, the charge read transistor 4 becomes conductive, and the signal charge of the photodiode 3 is transferred to the FD, so that the potential of the FD changes. The signal voltage of the FD is applied to the gate electrode of the amplifier transistor 6 and converted into a signal current by the amplifier transistor 6. On the other hand, when the vertical selection pulse φSEL is applied to the gate electrode of the vertical selection transistor 7, the vertical selection transistor 7 becomes conductive, and a signal current appears on the vertical signal line 9. This signal current flows to the horizontal signal line through the horizontal selection transistor 17 by the horizontal selection pulse, and is output from the output unit.

  Next, an embodiment of a solid-state imaging device according to the present invention, that is, a CMOS solid-state imaging device will be described with reference to FIG. Although this example is applied to the CMOS type solid-state imaging device including the unit pixel 20 composed of one photodiode and four transistors shown in FIG. 2, the present invention is not limited to this, and other numbers of MOS transistors may be different. The present invention can also be applied to a CMOS type solid-state imaging device provided with unit pixels.

FIG. 1 shows a main part of a pixel. In a unit pixel, the photodiode 3 and components of a charge readout transistor 4, a reset transistor 5 and an amplifier transistor 6 which are three MOS transistors are shown.
The CMOS type solid-state imaging device 1 according to the present embodiment forms a pixel isolation region 25 for partitioning each pixel on the surface side of a first conductivity type, for example, p-type silicon semiconductor substrate 2, and The unit pixel 20 is configured by forming a photodiode 3 and a plurality of MOS transistors, in this example, four MOS transistors of a charge readout transistor 4, a reset transistor 5, an amplifier transistor 6 and a vertical selection transistor (not shown). A large number of the pixels 60 are arranged in a two-dimensional matrix. The pixel isolation region 25 is formed of, for example, a field insulating film (SiO ₂ film).

  In this embodiment, in particular, a plurality of MOS transistors, that is, a charge readout transistor 4, a reset transistor 5, an amplifier transistor 6, and a vertical selection transistor (not shown) are formed on the surface of the semiconductor substrate 2, and a photodiode. 3 is formed inside the semiconductor substrate 2 so as to be positioned below these charge readout transistor 4, reset transistor 5, amplifier transistor 6 and vertical selection transistor (not shown). At this time, the channel portion of the charge reading transistor 4 for reading the signal charge of the photodiode 3 is formed in the depth direction, preferably in the vertical direction with respect to the surface of the semiconductor substrate 2.

  The photodiode 3 includes a high impurity concentration p-type semiconductor region (p + region) 12 formed on the front surface side of the substrate 2 and a high concentration impurity formed in a depth direction toward the back surface side of the substrate 2 in contact therewith. The n-type semiconductor region 11 is composed of a region (n + region) 11A and a low impurity concentration region (n region) 11B. The main pn junction j of the photodiode 3 is formed by the p + region 12 and the n + region 11A. Therefore, the pn junction j is formed in the semiconductor substrate 2 so that a part of the pn junction extends below the MOS transistor. In this case, as apparent from FIG. 1, when viewed from the substrate surface side, the photodiode 3 is formed across the region of the adjacent unit pixels 20 and 20 partitioned by the pixel separation region. When viewed from the back side of the substrate, the region of the photodiode 3 corresponds to the region of the unit pixel 20.

  In the charge readout transistor 4, a high impurity concentration n-type semiconductor region, so-called n + source / drain region 14 is formed on the surface of the semiconductor substrate 2, and the semiconductor substrate 2 is in contact with the n + source / drain region 14. A groove 18 is formed at a position deeper than, for example, the pn junction j of the photodiode 3 from the surface. That is, a groove 18 is formed in a depth direction that reaches the inside of the n + region 11A beyond the pn junction j, preferably in a direction perpendicular to the substrate surface. A gate insulating film (for example, a silicon oxide film) 10 is formed on the inner wall of the groove portion 18 so as to extend between the n + source / drain region 14 and the n + region 11A of the photodiode 3, and the groove portion 18 is formed on the gate insulating film 10. A buried columnar gate electrode 19 is formed. As a result, the channel portion 21 of the charge readout transistor 4 is formed in the depth direction, preferably perpendicular to the semiconductor substrate surface, corresponding to the inner wall of the groove portion 18. The bottoms of the gate electrode 19 and the gate insulating film 10 may be formed corresponding to the depth position of the pn junction j of the photodiode 3.

  Further, in the portion corresponding to the lower peripheral portion including the bottom portion of the gate electrode 19 of the charge reading transistor 4, the impurity concentration is lower than that of the p + semiconductor region 12 between the n + region 11 </ b> A constituting the photodiode 3 and the gate insulating film 10. P-type semiconductor region (p-region) or n-type semiconductor region (n-region) 13a, in this example, a p-region is formed. Further, in the high impurity concentration p-type semiconductor region (p + region) 12 constituting the photodiode 3, a portion 13b in the vicinity of the gate insulating film 10 is formed as a low impurity concentration p-type region (p− region). In this case, the p-region 13a and the p-region 13b can be formed at the same concentration.

  The charge reading transistor 4 is configured by one n + source / drain region 14, the n + region 11A of the photodiode 3 also serving as the other n + source / drain region, and the gate electrode 19. This n + source / drain region 14 becomes FD (floating diffusion).

  Here, it is necessary to efficiently read out all the signal charges photoelectrically converted and accumulated by the photodiode 3 to the charge reading transistor 4. Therefore, the gate portion of the charge readout transistor 4 corresponding to the connection portion between the charge readout transistor 4 and the photodiode 3, that is, the gate electrode 19 has the same distance from the periphery of the photodiode 3 as shown in FIG. 1. It is desirable to form in the central part. In FIG. 1, the gate electrode 19 is formed in contact with the source / drain region 14 and the pixel isolation region 25 through the gate insulating film 10.

At the same time as the n + source / drain regions 14, high impurity concentration n-type semiconductor regions, that is, n + source / drain regions 15, 16 are formed on the other surface of the p-type semiconductor substrate 2.
The reset transistor 5 includes n + source / drain regions 14 and 15 and a gate electrode 24 formed on the p-type semiconductor substrate 2 between the n + source / drain regions 14 and 15 via the gate insulating film 10. Composed. The amplifier transistor 6 includes n + source / drain regions 15 and 16 and a gate electrode 24 formed on the p-type semiconductor substrate 2 between the n + source / drain regions 15 and 16 via the gate insulating film 10. Is done. The vertical selection transistor 7 (see FIG. 2) is also composed of a pair of n + source / drain regions and a gate electrode formed on the p-type semiconductor substrate 2 with a gate insulating film 10 therebetween, though not shown. Is done.

  Each of the gate electrodes 19, 23, and 24 described above can be formed of a polysilicon film, for example. Further, the connection conductor 29 and the wirings 27 and 28 can also be formed of, for example, a polysilicon film.

  On the semiconductor substrate 2 on which the MOS transistors 4 to 6 and the vertical selection transistor are formed, a multilayer wiring 27 including a power supply wiring 28 is formed via an interlayer insulating film 26. Of the multilayer wiring, the power supply wiring 28 is connected via the connection conductor 29 to the n + source / drain region 14 which becomes the FD (floating diffusion) of each pixel.

  In the above-described embodiment, a low impurity concentration is provided between the n + region 11A constituting the photodiode 3 and the gate insulating film 10 in the portion corresponding to the lower peripheral portion including the bottom portion of the gate electrode 19 of the charge reading transistor 4. P-type semiconductor region (p-region) 13a was formed. However, in addition, as shown in FIG. 3, only in the portion corresponding to the bottom of the gate electrode 19 of the charge readout transistor 4, there is a low impurity concentration between the n + region 11A constituting the photodiode 3 and the gate insulating film 10. The p-type semiconductor region (p− region) 13c can be formed.

  In the CMOS solid-state imaging device 1 described above, light L is incident from the back surface of the semiconductor substrate 2 and the light L is received by the photodiode 3. Although not shown, a color filter and an on-chip microlens or the like are formed on the back surface of the semiconductor substrate 2 at positions corresponding to the respective pixels 20 on the color filter.

Next, an embodiment of a method for manufacturing the above-described CMOS type solid-state imaging device 1, particularly a method for manufacturing a main part including the photodiode 3 and the charge readout transistor 4, will be described with reference to FIGS.
First, as shown in FIG. 4A, an n-type semiconductor region (n + region 11A, n region 11B) 11 to be the photodiode 3 is formed at a required depth position of each pixel formation region of the p-type semiconductor substrate 2, and p A p-type semiconductor region, that is, a central p− region 13b and p + regions 12 on both sides of the p− region 13b are selectively formed by ion implantation.
Next, as shown in FIG. 4B, columnar grooves 18 are formed in the substrate depth direction, preferably in the vertical direction, so as to reach the n + region 11A from the surface of the substrate 2 corresponding to the central portion of the p− region 13b. For example, it is formed by selective etching. Next, a gate insulating film (for example, a silicon oxide film) 10 is formed on the inner wall surface of the columnar groove 18 and the surface of the substrate 2 by a CVD method or a thermal oxidation method.

Next, as shown in FIG. 5C, a low-concentration p-type impurity is introduced by, for example, oblique ion implantation, so that the n + region 11A of the photodiode 3 has a portion corresponding to the lower peripheral portion including the bottom of the groove portion 18. A p-region 13a is formed.
Next, as shown in FIG. 6D, for example, a polysilicon film 31 is deposited on the entire surface of the substrate so as to fill the groove 18, and a resist mask 32 is formed on the region where the gate electrode is to be formed.

Next, as shown in FIG. 7E, the polysilicon film 31 is patterned through the resist mask 32 to form the columnar gate electrode 19 embedded in the groove 18.
Next, as shown in FIG. 7F, the pixel isolation region 25 and the n + source / drain regions 14, 15 and 16 of each MOS transistor are formed by ion implantation. Next, gate electrodes 23 and 24 made of other polysilicon films are formed. The gate electrodes 19, 23, 24, etc. can be formed simultaneously.
It is also possible to form the columnar gate electrode 19 by forming the groove 18 after forming each MOS transistor.

  In this manufacturing method, the photodiode 3 is formed by ion implantation before the charge reading transistor 4 is formed, so that the effective gate length d can be easily and accurately determined even if the groove portion 18 is formed unevenly. That is, the effective gate length d is determined by the distance between the n + region 11 A constituting the photodiode 3 and the bottom of the n + source / drain region 14 of the charge reading transistor 4.

  According to the above-described CMOS solid-state imaging device according to the present embodiment, the photodiode 3 in the pixel region 20 has a plurality of MOS transistors formed on the substrate surface, for example, the readout transistor 4, the reset transistor 5, the amplifier transistor 6, Since it is three-dimensionally arranged so as to be positioned below a vertical transfer transistor (not shown) or the like, the pixel area can be reduced while increasing the area of the photodiode 3. That is, since the area of the photodiode is increased and light is received from the back surface of the substrate, the pixel size can be reduced without reducing the saturation charge amount (Qs) and sensitivity.

  Reading of charges from the photodiode 3 can be realized by the charge reading transistor 4 in which the channel portion 21 is formed in the depth direction, preferably in the vertical direction, with respect to the surface of the semiconductor substrate 2. Further, by positioning the gate electrode 19 of the charge readout transistor 4 at the center of the photodiode 3, the signal charge in the entire area of the photodiode 3 can be efficiently read out to the charge readout transistor 4 through the channel portion 21. Therefore, it is easy to electrically read out the charge from the photodiode 3.

Since the n + source / drain region 14 of the charge readout transistor 4 also serves as the n + region 11A constituting the photodiode 3, the effective channel length d of the charge readout transistor 4 can be determined.
By forming the gate electrode 19 of the charge readout transistor 4 and the bottom of the gate insulating film 10 at the same position as the depth of the pn junction j of the photodiode 3 or at a position deeper than the pn junction j, the channel portion 21 becomes a photodiode. 3 and the n + source / drain region 14 are reliably formed, and the operation of the charge readout transistor 4 can be ensured.

The n + region 11A of the photodiode 3 also serves as the other n + source / drain region of the charge readout transistor 4, and the lower part of the columnar gate electrode 19 of the charge readout transistor 4 is located from the position of the pn junction j of the photodiode 3. Further, by forming the charge readout transistor 4 after the formation of the photodiode 3, the effective gate length d of the charge readout transistor 4 can be determined by the depth position of the n + region 11A of the photodiode 3. .

  In other words, the accurate effective gate length d can be determined even if there is variation in the formation of the groove 18. By providing the p− region 13 a between the gate insulating film 10 of the charge readout transistor 4 and the n + region 11 </ b> A of the photodiode 3, it is possible to suppress the occurrence of leakage current due to a defect of the photodiode 3. Further, by providing a p− region 13b between the gate insulating film 10 of the charge readout transistor 4 and the p + semiconductor region 12 of the photodiode 3, the charge storage capacity of the photodiode 3 is maintained and the charge readout transistor 4 Charge transfer can be facilitated.

As a preferred form of the solid-state imaging device of the present invention, it is appropriate to make light incident on the photodiode from the back surface of the semiconductor substrate.
By making light incident on the photodiode from the back side of the semiconductor region, the pixel size can be reduced without reducing the saturation charge amount and sensitivity, coupled with the large area of the photodiode. Can do.

1 is a cross-sectional view showing an embodiment of a solid-state imaging device according to the present invention. 3 is an equivalent circuit illustrating an embodiment of a unit pixel of the solid-state imaging device according to the present invention. It is a principal part which shows other embodiment of the solid-state imaging device concerning this invention. A and B are process diagrams showing an embodiment of a method of manufacturing a solid-state imaging device according to the present invention. It is process drawing which shows one Embodiment of the manufacturing method of the solid-state imaging device which concerns on C this invention. FIG. 4D is a process diagram showing an embodiment of a method for manufacturing a solid-state imaging device according to the present invention. E and F are process diagrams showing an embodiment of a method for manufacturing a solid-state imaging device according to the present invention. It is sectional drawing of the principal part of the conventional solid-state imaging device.

Explanation of symbols

1..CMOS type solid-state imaging device 2 ... semiconductor substrate 3..photodiode 4 ... charge readout transistor 5 ... reset transistor 6 ... amplifier transistor 7 ... vertical selection transistor 8 ... Power wiring, 9... Vertical signal line, 10... Gate insulating film, 11... N-type semiconductor region, 12... High impurity concentration p-type semiconductor region (p + region), 14. 15, 16 ... n + source / drain regions, 17 .... horizontal selection transistor, 18 .... trench, 19, 23, 24 ... gate electrode, 20 .... unit pixel, 21 ... channel, 25 ... pixel separation .., 26..interlayer insulating film, 27, 28..wiring, 29..connection conductor, 32..resist mask, 60..pixel, 51..CMOS solid-state imaging device, 52 .. Semiconductor substrate, 53..photodiode, 54..charge readout transistor, 55..reset transistor, 56..amplifier transistor, 57, 58, 59..n + source / drain region, 61..n-type semiconductor region , 62 .. p-type semiconductor region, 74 .. Gate electrode, 75 .. Connection conductor, 76 .. Power supply wiring, 77 .. Multi-layer wiring, 78.

Claims (6)

A pixel composed of a photodiode and a transistor is formed on a semiconductor substrate,
The transistor is formed on a surface of the semiconductor substrate;
A pn junction formed between the high-concentration regions of the photodiode is inside the semiconductor substrate, and a part of the pn junction of the photodiode extends under the transistor formed on the surface of the semiconductor substrate. Formed to exist ,
In the pixel, a channel portion of a charge reading transistor for reading a signal charge of the photodiode is formed in a depth direction with respect to the semiconductor substrate surface,
In a portion corresponding to the bottom of the gate electrode of the charge readout transistor, the first conductivity constituting the photodiode is disposed between the second conductivity type semiconductor region constituting the photodiode and the gate insulating film of the charge readout transistor. A semiconductor region of the first conductivity type or the second conductivity type is formed in a state of being separated from the semiconductor region of the mold,
A solid-state imaging device , wherein light is incident on the photodiode from the back surface of the semiconductor substrate . The solid-state imaging device of the bottom of the gate electrode and the gate insulating film, according to claim 1, characterized in that it is formed at a position deeper than the depth of the pn junction of the photodiode of the charge readout transistor. 3. The solid-state imaging device according to claim 1, wherein a gate electrode corresponding to a connection portion between the charge readout transistor and the photodiode is located at a central portion of the photodiode. 4. One of the second conductivity type source and drain regions of said charge readout transistor, according to claim 1, characterized in that also serves as the second conductivity type semiconductor region constituting the photodiode Solid-state imaging device. The distance between the second conductivity type semiconductor region constituting the photodiode formed by ion implantation and the other second conductivity type source / drain region formed on the surface of the semiconductor substrate of the charge readout transistor. in solid-state imaging device according to any one of claims 1 to 4, characterized in that the effective channel length of the electric charge readout transistor is determined. The first conductivity type semiconductor region having a lower concentration than the high concentration semiconductor region is formed between the first conductivity type high concentration semiconductor region constituting the photodiode and the gate insulating film of the charge readout transistor. The solid-state imaging device according to claim 1, wherein:

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