JP4885521B2 - パッケージ統合された薄膜led - Google Patents
パッケージ統合された薄膜led Download PDFInfo
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- JP4885521B2 JP4885521B2 JP2005342796A JP2005342796A JP4885521B2 JP 4885521 B2 JP4885521 B2 JP 4885521B2 JP 2005342796 A JP2005342796 A JP 2005342796A JP 2005342796 A JP2005342796 A JP 2005342796A JP 4885521 B2 JP4885521 B2 JP 4885521B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/018—Bonding of wafers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
- H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/8506—Containers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
- H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/533—Cross-sectional shape
- H10W72/534—Cross-sectional shape being rectangular
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
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- Led Devices (AREA)
- Led Device Packages (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
Description
12 パッケージ基板
14 サファイア成長基板
16 n−型層
18 活性層
20 p−型層
22 金属コンタクトパッド
24 金属
26 電極
Claims (21)
- 第1導電型の第1エピタキシャル層と、成長基板上に形成された第2導電型の第2エピタキシャル層と、前記第1及び第2エピタキシャル層の間に配置された活性層とを含む発光ダイオード(LED)層を前記成長基板上に成長させる段階であって、前記第1エピタキシャル層の第1の側にある一次発光面が、実質的に前記活性層と平行であり、前記LED層が少なくとも1つの個別のLEDを形成していることを特徴とする段階と、
パッケージ基板を準備する段階であって、前記パッケージ基板の横方向の範囲が個々のLEDの横方向の範囲を越えており、前記パッケージ基板が、前記第1及び第2エピタキシャル層を電気的に接続するための1つ又はそれ以上の電気的コンタクトパッドを有する支持面を含み、前記コンタクトパッドがパッケージ端子に接続するための金属リードと電気的に接続されていることを特徴とする段階と、
前記成長基板に取り付けられた前記LED層を、前記第2エピタキシャル層が前記パッケージ基板上の第1コンタクトパッドに面するように前記パッケージ基板上に載置する段階と、
前記パッケージ基板と前記第2エピタキシャル層との間に配置された金属境界面を用いて、前記第2エピタキシャル層を前記第1コンタクトパッドに結合する段階であって、前記一次発光面と前記パッケージ基板の一部分との間の最短距離が50ミクロンより大きくないことを特徴とする段階と、
前記成長基板を除去する段階と、
前記成長基板が除去された後に更に前記LED層を処理する段階と、
を含み、
前記LED層を更に処理する段階が、前記第1エピタキシャル層を薄化する段階を含む、方法。 - 前記成長基板がサファイアであり、前記成長基板を除去する段階がレーザリフトオフプロセスを実施する段階を含む請求項1に記載の方法。
- 前記成長基板がシリコンを含み、前記成長基板を除去する段階がエッチングプロセスを実施する段階を含む請求項1に記載の方法。
- 前記LED層がAlInGaPを含み、前記成長基板がGaAs又はGeを含む請求項1に記載の方法。
- 前記LED部分及びパッケージ基板を囲むハウジング内にこれらをマウントし、前記ハウジングから前記パッケージ基板上のコンタクト領域へ延びる金属リードを電気的に接続する段階を更に含む請求項1に記載の方法。
- 前記LED層を載置する段階が、前記パッケージ基板上の複数のLEDを載置する段階を含む請求項1に記載の方法。
- 前記パッケージ基板を保護するために、前記パッケージ基板上に前記LED層が載置された後に前記パッケージ基板の上に保護層を堆積させる段階と、
前記第1エピタキシャル層の一部をエッチングする段階と、
を更に含む請求項1に記載の方法。 - 前記第1エピタキシャル層の一部をエッチングする段階が、前記第1エピタキシャル層の厚さの少なくとも50%をエッチングする段階を含む請求項7に記載の方法。
- 前記第1エピタキシャル層と前記パッケージ基板上のコンタクトパッドとの間に電気コネクタを準備する段階を更に含む請求項1に記載の方法。
- 前記電気コネクタがワイヤーであることを特徴とする請求項9に記載の方法。
- 前記電気コネクタが金属ブリッジであることを特徴とする請求項9に記載の方法。
- 前記LEDがフリップチップであり、前記電気コネクタを準備する段階が、前記第1エピタキシャル層を前記パッケージ基板上のコンタクトパッドに結合する段階を含む請求項9に記載の方法。
- 前記成長基板が除去された後に前記パッケージ基板をダイシングする段階を更に含み、各パッケージ基板のダイがそこにマウントされた1つ又はそれ以上のLEDを有することを特徴とする請求項1に記載の方法。
- LED層を成長させる段階が窒化ガリウムベースのLED層を成長させる段階を含む請求項1に記載の方法。
- 第1導電型の第1エピタキシャル層と、成長基板上に形成された第2導電型の第2エピタキシャル層と、前記第1及び第2エピタキシャル層の間に配置された活性層とを含む発光ダイオード(LED)層を前記成長基板上に成長させる段階であって、前記第1エピタキシャル層の第1の側にある一次発光面が、実質的に前記活性層と平行であり、前記LED層が少なくとも1つの個別のLEDを形成していることを特徴とする段階と、
パッケージ基板を準備する段階であって、前記パッケージ基板の横方向の範囲が個々のLEDの横方向の範囲を越えており、前記パッケージ基板が、前記第1及び第2エピタキシャル層を電気的に接続するための1つ又はそれ以上の電気的コンタクトパッドを有する支持面を含み、前記コンタクトパッドがパッケージ端子に接続するための金属リードと電気的に接続されていることを特徴とする段階と、
前記LED層を前記パッケージ基板に載置する前に、前記LED層及び成長基板をダイシングする段階と、
前記成長基板に取り付けられた前記LED層を、前記第2エピタキシャル層が前記パッケージ基板上の第1コンタクトパッドに面するように前記パッケージ基板上に載置する段階と、
前記パッケージ基板と前記第2エピタキシャル層との間に配置された金属境界面を用いて、前記第2エピタキシャル層を前記第1コンタクトパッドに結合する段階であって、前記一次発光面と前記パッケージ基板の一部分との間の最短距離が50ミクロンより大きくないことを特徴とする段階と、
前記成長基板を除去する段階と、
前記成長基板が除去された後に更に前記LED層を処理する段階と、
を含む方法。 - 前記LED層を前記パッケージ基板上に載置する段階が、前記LED層及び前記成長基板をダイシングする前に前記LED層を前記パッケージ基板上に載置する段階を含み、前記成長基板を除去する段階が前記成長基板全体を完全な状態のまま除去する段階を含み、前記成長基板を除去した後に前記パッケージ基板をダイシングする段階を更に含む請求項1に記載の方法。
- 前記第1エピタキシャル層が前記第1導電型の複数のエピタキシャル層を含み、前記第2エピタキシャル層が前記第2導電型の複数のエピタキシャル層を含むことを特徴とする請求項1に記載の方法。
- 前記LED層が3ミクロンより大きくない厚さを有するように前記成長基板を除去した後に前記第1エピタキシャル層をエッチングする段階を更に含む請求項1に記載の方法。
- 前記LED層が10ミクロンより大きくない厚さを有するように、前記成長基板を除去した後に前記第1エピタキシャル層をエッチングする段階を更に含む請求項1に記載の方法。
- 前記LED層を更に処理する段階が、前記一次発光面内に光取り出し構造部を形成する段階を含む請求項1に記載の方法。
- 光取り出し構造部を形成する段階が、一次発光面を粗面化し、パターン化し、ディンプル加工し、或いはフォトニック結晶を形成する段階からなることを特徴とする請求項20に記載の方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/977294 | 2004-10-28 | ||
| US10/977,294 US7256483B2 (en) | 2004-10-28 | 2004-10-28 | Package-integrated thin film LED |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006128710A JP2006128710A (ja) | 2006-05-18 |
| JP4885521B2 true JP4885521B2 (ja) | 2012-02-29 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005342796A Expired - Lifetime JP4885521B2 (ja) | 2004-10-28 | 2005-10-28 | パッケージ統合された薄膜led |
Country Status (4)
| Country | Link |
|---|---|
| US (5) | US7256483B2 (ja) |
| EP (1) | EP1653523B1 (ja) |
| JP (1) | JP4885521B2 (ja) |
| TW (1) | TWI413273B (ja) |
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- 2005-10-27 TW TW094137652A patent/TWI413273B/zh not_active IP Right Cessation
- 2005-10-28 JP JP2005342796A patent/JP4885521B2/ja not_active Expired - Lifetime
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- 2006-05-31 US US11/421,350 patent/US7488621B2/en not_active Expired - Lifetime
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| US7875533B2 (en) | 2011-01-25 |
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| JP2006128710A (ja) | 2006-05-18 |
| US20110084301A1 (en) | 2011-04-14 |
| US7256483B2 (en) | 2007-08-14 |
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